Patents Examined by Zandra Smith
  • Patent number: 10367001
    Abstract: Provided herein a semiconductor device including a stack including conductive layers and insulating layers that are alternately stacked, and a slit insulating layer passing through the stack in a stacking direction, the slit insulating layer including a first main pattern extending in a first direction, and a first protruding pattern protruding in a second direction crossing the first direction at an end of the first main pattern.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: July 30, 2019
    Assignee: SK hynix Inc.
    Inventors: Ki Hong Lee, Seung Ho Pyi, Seok Min Jeon
  • Patent number: 10096614
    Abstract: Provided herein a semiconductor device including a stack including conductive layers and insulating layers that are alternately stacked, and a slit insulating layer passing through the stack in a stacking direction, the slit insulating layer including a first main pattern extending in a first direction, and a first protruding pattern protruding in a second direction crossing the first direction at an end of the first main pattern.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: October 9, 2018
    Assignee: SK hynix Inc.
    Inventors: Ki Hong Lee, Seung Ho Pyi, Seok Min Jeon
  • Patent number: 10056530
    Abstract: In one aspect, a phosphor converted white light LED comprising a narrow green phosphor rather than a conventional broad green phosphor may simultaneously exhibit high R9, and high Luminance Efficacy of Radiation, optionally without use of a deep red phosphor to maintain desired red color rendering. In another aspect, a phosphor converted white light LED comprising a narrow green phosphor rather than a conventional broad green phosphor may provide an emission spectrum exhibiting a significant dip in the yellow region of the spectrum and thereby provide high red-green contrast without use of a filter. The yellow dip may be shallower than in conventional devices, and the device may therefore be brighter, while maintaining desired CRI and R9.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: August 21, 2018
    Assignee: EIE MATERIALS, INC.
    Inventors: Jonathan Melman, Robert Nordsell, Kristen Baroudi, Evan Thomas, Yong Bok Go
  • Patent number: 9997440
    Abstract: A three-dimensional integrated circuit (3DIC) including a first substrate having a first surface and a second surface opposite to the first surface and a second substrate attached to the first surface of the first substrate. The 3DIC further includes an interconnect between attached to the first surface of the first substrate and the second substrate and a plurality of through vias formed in the first substrate and electrically coupled to the interconnect. The 3DIC further includes a protection layer over the second surface of the first substrate, wherein each of the plurality of through vias protrudes through the protection layer and a plurality of dies, each die of the plurality of dies attached to at least one through via of the plurality of through vias.
    Type: Grant
    Filed: April 17, 2013
    Date of Patent: June 12, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wen-Chih Chiou, Weng-Jin Wu, Shau-Lin Shue
  • Patent number: 9991461
    Abstract: Multiple organic layers (120) are located between a first electrode (110) and a second electrode (130), each organic layer including a light emitting layer. A charge generation layer (200) is located between mutually adjacent organic layers (120). In other words, the multiple organic layers (120) are mutually laminated and the charge generation layer (200) is located between the multiple organic layers (120). The charge generation layer (200) includes a first layer, a second layer, and a third layer. The first layer contains an electron transport material and the second layer contains a metal and a hole injection material. The third layer is formed using a hole transport material. The charge generation layer (200) contains an electron injection material for improving electron injection properties of the first layer, the charge generation layer provided on the first layer side than the second layer.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: June 5, 2018
    Assignee: PIONEER CORPORATION
    Inventor: Akihiro Tanaka
  • Patent number: 9991132
    Abstract: A technique for patterning a workpiece such as an integrated circuit workpiece is provided. In an exemplary embodiment, the method includes receiving a workpiece having a material layer disposed on a substrate. A first set of fins is formed on the material layer, and a second set of fins is formed on the material layer interspersed between the first set of fins. The second set of fins have a different etchant sensitivity from the first set of fins. A first etching process is performed on the first set of fins and configured to avoid substantial etching of the second set of fins. A second etching process is performed on the second set of fins and configured to avoid substantial etching of the first set of fins. The material layer is etched to transfer a pattern defined by the first etching process and the second etching process.
    Type: Grant
    Filed: April 17, 2015
    Date of Patent: June 5, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Yuan Tseng, Chi-Cheng Hung, Chun-Kuang Chen, De-Fang Chen, Ru-Gun Liu, Tsai-Sheng Gau, Wei-Liang Lin
  • Patent number: 9985202
    Abstract: A method of fabricating a memory device, the method including forming a first magnetization layer; forming a tunnel barrier layer on the first magnetization layer; forming a second magnetization layer on the tunnel barrier layer; forming a magnetic tunnel junction (MTJ) structure by patterning the first magnetization layer, the tunnel barrier layer, and the second magnetization layer; and forming a boron oxide in a sidewall of the MTJ structure by implanting boron.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: May 29, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jeong-heon Park, Se-chung Oh, Byoung-jae Bae, Jong-chul Park
  • Patent number: 9978878
    Abstract: Disclosed is a semiconductor device using an oxide semiconductor, with stable electric characteristics and high reliability. In a process for manufacturing a bottom-gate transistor including an oxide semiconductor film, dehydration or dehydrogenation is performed by heat treatment and oxygen doping treatment is performed. The transistor including a gate insulating film subjected to the oxygen doping treatment and the oxide semiconductor film subjected to the dehydration or dehydrogenation by the heat treatment is a transistor having high reliability in which the amount of change in threshold voltage of the transistor by the bias-temperature stress (BT) test can be reduced.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: May 22, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 9978846
    Abstract: A method for forming a steeped oxide on a substrate is described: successively forming a first pad oxide layer, a nitride layer, a second pad oxide layer and a poly layer on the substrate; etching the poly layer to have an opening for the stepped oxide region; isotropically etching the second pad oxide layer to the nitride layer through the opening to form a stepped trench; isotropically etching the nitride layer to the first pad oxide layer through the opening to expand the stepped trench; filling the stepped trench with dielectric material to form a dielectric layer; planarizing the dielectric layer; removing the poly layer; removing the second pad oxide layer; removing the nitride layer; removing the portion of the first pad oxide layer uncovered by the dielectric layer such that the remaining first pad oxide layer together the remaining dielectric layer forms the stepped oxide.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: May 22, 2018
    Assignee: Chengdu Monolithic Power Systems Co., Ltd.
    Inventor: Yanjie Lian
  • Patent number: 9972724
    Abstract: An acceleration sensor includes: a semiconductor substrate that includes a support substrate and a semiconductor layer; a first-direction movable electrode; a second-direction movable electrode; a first-direction fixed electrode; a second-direction fixed electrode; and a support member. The acceleration sensor is configured to detect acceleration in a first direction in the surface direction of the semiconductor substrate and acceleration in a second direction orthogonal to the first direction and parallel to the surface direction.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: May 15, 2018
    Assignee: DENSO CORPORATION
    Inventor: Kiyomasa Sugimoto
  • Patent number: 9972697
    Abstract: A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over the area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; depositing a sacrificial layer over the thin metal layer; performing a first rapid thermal anneal; removing the sacrificial layer; and depositing a metal layer of low resistivity metal for gap fill.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: May 15, 2018
    Assignees: International Business Machines Corporation, GLOBALFOUNDRIES Inc.
    Inventors: Takashi Ando, Eduard A. Cartier, Kisik Choi, Vijay Narayanan
  • Patent number: 9966252
    Abstract: Provided is a method of manufacturing a semiconductor device.
    Type: Grant
    Filed: April 7, 2015
    Date of Patent: May 8, 2018
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Ryota Sasajima, Yoshiro Hirose, Yosuke Ota, Naonori Akae, Kojiro Yokozawa
  • Patent number: 9960252
    Abstract: A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over the area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; depositing a sacrificial layer over the thin metal layer; performing a first rapid thermal anneal; removing the sacrificial layer; and depositing a metal layer of low resistivity metal for gap fill.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: May 1, 2018
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Takashi Ando, Eduard A. Cartier, Kisik Choi, Vijay Narayanan
  • Patent number: 9954075
    Abstract: Memory devices and methods of making memory devices are shown. Methods and configurations as shown provide folded and vertical memory devices for increased memory density. Methods provided reduce a need for manufacturing methods such as deep dopant implants.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: April 24, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, John K. Zahurak, Michael P. Violette
  • Patent number: 9954142
    Abstract: Disclosed herein are a material layer stack, a light emitting element, a light emitting package, and a method of fabricating a light emitting element. The material layer stack includes: a substrate having a first lattice constant; and a semiconductor layer grown on the substrate, the semiconductor layer having a second lattice constant that is different from the first lattice constant. Using the material layer stack, a light emitting element having a low leakage current, a low operation voltage, and an excellent luminous efficiency can be obtained.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: April 24, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Keon-Hun Lee, Eun-Deok Sim, Suk-Ho Yoon, Jeong-Wook Lee, Do-Young Rhee, Kee-Won Lee, Chul-Min Kim, Tae-Bang Nam
  • Patent number: 9947636
    Abstract: A method for making a semiconductor device may include bonding a top lead frame component, having recesses, with a bottom lead frame component to form a lead frame, the top and bottom lead frame components each including metal. The method may include mounting an IC on the lead frame, encapsulating the IC and the lead frame, and removing portions of the bottom lead frame component to define contacts for the IC.
    Type: Grant
    Filed: June 2, 2014
    Date of Patent: April 17, 2018
    Assignee: STMICROELECTRONICS, INC.
    Inventor: Jefferson Talledo
  • Patent number: 9947570
    Abstract: Various embodiments process semiconductor devices. In one embodiment, a release layer is applied to a handler. The release layer comprises at least one additive that adjusts a frequency of electro-magnetic radiation absorption property of the release layer. The additive comprises, for example, a 355 nm chemical absorber and/or chemical absorber for one of more wavelengths in a range comprising 600 nm to 740 nm. The at least one singulated semiconductor device is bonded to the handler. The at least one singulated semiconductor device is packaged while it is bonded to the handler. The release layer is ablated by irradiating the release layer through the handler with a laser. The at least one singulated semiconductor device is removed from the transparent handler after the release layer has been ablated.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: April 17, 2018
    Assignee: International Business Machines Corporation
    Inventors: Paul S. Andry, Bing Dang, Jeffrey Donald Gelorme, Li-Wen Hung, John U. Knickerbocker, Cornelia Tsang Yang
  • Patent number: 9947784
    Abstract: An integrated circuit and method having an extended drain MOS transistor with a buried drift region, a drain end diffused link between the buried drift region and the drain contact, and a concurrently formed channel end diffused link between the buried drift region and the channel, where the channel end diffused link is formed by implanting through segmented areas to dilute the doping to less than two-thirds the doping in the drain end diffused link.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: April 17, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Philip Leland Hower, Sameer Pendharkar, Marie Denison
  • Patent number: 9947740
    Abstract: A method for forming an on-chip capacitor with complementary metal oxide semiconductor (CMOS) devices includes forming a first capacitor electrode between gate structures in a capacitor region while forming contacts to source and drain (S/D) regions in a CMOS region. Gate structures are cut in the CMOS region and the capacitor region by etching a trench across the gate structures and filling the trench with a dielectric material. The gate structures and the dielectric material in the trench in the capacitor region are removed to form a position for an insulator and a second electrode. The insulator is deposited in the position. Gate metal is deposited to form gate conductors in the CMOS region and the second electrode in the capacitor region.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: April 17, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Peng Xu
  • Patent number: 9941196
    Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate having a first surface, and a second surface opposite to the first surface. The second surface defines a redistribution trench. The substrate has a via hole extending therethrough. The semiconductor device also includes a through via disposed in the via hole. The through via may include a via hole insulating layer, a barrier layer, sequentially formed on an inner wall of the via hole. The through via may further include a conductive connector adjacent the barrier layer. The semiconductor device additionally includes an insulation layer pattern formed on the second surface of the substrate. The insulation layer pattern defines an opening that exposes a region of a top surface of the through via. The semiconductor devices includes a redistribution layer disposed in the trench and electrically connected to the through via. The insulation layer pattern overlaps a region of the conductive connector.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: April 10, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ho-Jin Lee, Tae-Je Cho, Dong-Hyeon Jang, Ho-Geon Song, Se-Young Jeong, Un-Byoung Kang, Min-Seung Yoon