Abstract: A method for selective bump formation on a wafer includes performing a wafer test on the wafer. Known good dies (KGDs) on the wafer are identified based on the wafer test performed. Solder bumps are formed on the KGDs.

Abstract: A process for fabricating an Integrated Circuit (IC) and the IC formed thereby is disclosed. The process comprises providing a substrate. The process further comprises forming a plurality of longitudinal trenches in the substrate and depositing a layer of a first conductive material on at least one longitudinal trench of the plurality of longitudinal trenches. A first layer of a second conductive material is deposited on the layer of the first conductive material. Thereafter, the process includes depositing a second layer of the second conductive material on the first layer of the second conductive material. The second layer of the second conductive material at least partially fills the at least one longitudinal trench. The first conductive material is selected such that a reduction potential of the first conductive material is less than a reduction potential of the second conductive material.

Abstract: A semiconductor device with an increased effective gate length or an increased effective channel width, and a method of forming the same are provided. The effective gate length or the effective channel width of the device is increased by lowering a top surface of an oxide isolation structure below the gate of the semiconductor device.

Abstract: A magnetic device for magnetic random access memory (MRAM), spin torque MRAM, or spin torque oscillator technology is disclosed wherein a perpendicularly magnetized magnetic tunnel junction (p-MTJ) with a sidewall is formed between a bottom electrode and a top electrode. A first dielectric layer is 3 to 400 Angstroms thick, and formed on the p-MTJ sidewall with a physical vapor deposition RF sputtering process to establish a thermally stable interface with the p-MTJ up to temperatures around 400° C. during CMOS fabrication. The first dielectric layer may comprise one or more of B, Ge, and alloys thereof, and an oxide, nitride, carbide, oxynitride, or carbonitride. The second dielectric layer is up to 2000 Angstroms thick and may be one or more of SiOYNZ, AlOYNZ, TiOYNZ, SiCYNZ, or MgO where y+z>0.

Abstract: A leadframe with pre-molded cavities includes an outer frame and a plurality of units. Each unit includes a die pad and a plurality of leads. For each unit, a molding compound extends over a first portion of an upper surface of each of the leads that is located farthest from the die pad. The molding compound may also extend over an upper surface of the die pad. A second portion of the upper surface of each of the plurality of leads that is located nearest the die pad remains exposed outside the molding compound. A thickness of the molding compound covering the first portion of the upper surface of each of the leads is greater than a thickness of the molding compound covering the upper surface of the die pad.

Abstract: A near-infrared light emitting device can include semiconductor nanocrystals that emit at wavelengths beyond 1 ?m. The semiconductor nanocrystals can include a core and an overcoating on a surface of the core.

Abstract: Provided is a method of forming fine patterns, which is capable of easily forming a plurality of patterns repeatedly with a fine pitch when forming patterns necessary for manufacturing a highly integrated semiconductor device exceeding a resolution limit of a photolithography process.

Abstract: A method of forming a semiconductor device that includes forming an in-situ doped semiconductor material on a semiconductor substrate, and forming fin structures from the in-situ doped semiconductor material. A sacrificial channel portion of the fin structures may be removed, wherein a source region and a drain region portion of the fin structures of the in-situ doped semiconductor material remain. The sacrificial channel portion of the fin structure may then be replaced with a functional channel region.

Abstract: Semiconductor devices packages and methods are disclosed. In one embodiment, a package for a semiconductor device includes a substrate and a contact pad disposed on a first surface of the substrate. The contact pad has a first side and a second side opposite the first side. A conductive trace is coupled to the first side of the contact pad, and an extension of the conductive trace is coupled to the second side of the contact pad. A plurality of bond pads is disposed on a second surface of the substrate.

Abstract: A process is used for fabricating a final structure comprising in succession a useful semiconductor layer, a dielectric layer and a carrier substrate. The process comprises providing an intermediate structure including an upper layer, the dielectric layer and the carrier substrate, and finishing the intermediate structure to form the final structure by performing a treatment nonuniformly modifying the thickness of the dielectric layer following a predetermined dissolution profile. The dielectric layer of the intermediate structure has a thickness profile complementary to the predetermined dissolution profile.

Abstract: A method is disclosed of removing a first material disposed over a second material adjacent to a field effect transistor gate having a gate sidewall layer that comprises an etch-resistant material on a gate sidewall. The method includes subjecting the first material to a gas cluster ion beam etch process to remove first material adjacent to the gate, and detecting exposure of the second material during the gas cluster ion beam (GCIB) etch process.

Abstract: Method and devices are disclosed for device manufacture of gallium nitride devices by growing a gallium nitride layer on a silicon substrate using Atomic Layer Deposition (ALD) followed by rapid thermal annealing. Gallium nitride is grown directly on silicon or on a barrier layer of aluminum nitride grown on the silicon substrate. One or both layers are thermally processed by rapid thermal annealing. Preferably the ALD process use a reaction temperature below 550° C. and preferable below 350° C. The rapid thermal annealing step raises the temperature of the coating surface to a temperature ranging from 550 to 1500° C. for less than 12 msec.

Abstract: A semiconductor wafer has a plurality of semiconductor die. First and second conductive layers are formed over opposing surfaces of the semiconductor die, respectively. Each semiconductor die constitutes a WLCSP. A TSV is formed through the WLCSP. A semiconductor component is mounted to the WLCSP. The first semiconductor component is electrically connected to the first conductive layer. A first bump is formed over the first conductive layer, and a second bump is formed over the second conductive layer. An encapsulant is deposited over the first bump and first semiconductor component. A second semiconductor component is mounted to the first bump. The second semiconductor component is electrically connected to the first semiconductor component and WLCSP through the first bump and TSV. A third semiconductor component is mounted to the first semiconductor component, and a fourth semiconductor component is mounted to the third semiconductor component.

Abstract: An integrated circuit has two parallel digital transistors and a perpendicular analog transistor. The digital transistor gate lengths are within 10 percent of each other and the analog gate length is at least twice the digital transistor gate length. The first digital transistor and the analog transistor are implanted by a first LDD implant which includes a two sub-implant angled halo implant process with twist angles perpendicular to the first digital transistor gate edge and parallel to the analog transistor gate edge. The second digital transistor and the analog transistor are implanted by a second LDD implant which includes a two sub-implant angled halo implant process with twist angles perpendicular to the second digital transistor gate edge and parallel to the analog transistor gate edge. The first halo dose is at least 20 percent more than the second halo dose.

Abstract: A method of fabrication of an array of optoelectronic structures. The method first provides a crystalline substrate having cells corresponding to individual optoelectronic structures to be obtained. Each of the cells comprises an opening to the substrate. Then, several first layer portions of a first compound semiconductor material are grown in each the opening to at least partly fill a respective one of the cells and form an essentially planar film portion therein. Next, several second layer portions of a second compound semiconductor material are grown over the first layer portionsthat coalesce to form a coalescent film extending over the first layer portions. Finally, excess portions of materials are removed, to obtain the array of optoelectronic structures. Each optoelectronic structure comprises a stack protruding from the substrate of: a residual portion of one of the second layer portions; and a residual portion of one of the first layer portions.

Abstract: Embodiments of a method for generating ions in an ion source are provided. The method for generating ions in an ion source includes introducing a dopant gas and a diluent gas into an ion source arc chamber. The method for generating ions in an ion source further includes generating plasma in the ion source arc chamber based on the dopant gas and the diluent gas. In addition, the dopant gas includes carbon monoxide, and the diluent gas includes xenon and hydrogen.

Abstract: A manufacturing method of a flexible display apparatus includes forming a sacrificial layer on a carrier, forming a flexible substrate on the sacrificial layer, forming a display element on the flexible substrate, forming a first protection layer on the display element, forming, on the first protection layer, a second protection layer, which has an opposite sign of a thermal expansion coefficient to the first protection layer, separating the flexible substrate from the carrier by removing at least a portion of the sacrificial layer, and separating the first protection layer from the first protection layer.

Abstract: Packaged semiconductor assemblies including interconnect structures and methods for forming such interconnect structures are disclosed herein. One embodiment of a packaged semiconductor assembly includes a support member having a first bond-site and a die carried by the support member having a second bond-site. An interconnect structure is connected between the first and second bond-sites and includes a wire that is coupled to at least one of the first and second bond-sites. The interconnect structure also includes a third bond-site coupled to the wire between the first and second bond-sites.

Abstract: The invention relates to a method for fabricating an array substrate, an array substrate and a display device. The method for fabricating an array substrate may comprise: forming a metal thin film layer for a source electrode, a drain electrode and a data line; forming a non-crystalline semiconductor thin film layer on the metal thin film layer; and performing annealing, so as to at least partly convert the non-crystalline semiconductor thin film layer into a metal semiconductor compound. By at least partly converting the non-crystalline semiconductor thin film layer into a metal semiconductor compound, the resulting metal semiconductor compound may prevent oxidative-corrosion of the metal thin film layer, such as a low-resistance metal (e.g., Cu or Ti) layer, in the subsequent procedures, which is favorable for the fabrication of a metal oxide thin film transistor using Cu or Ti.

Abstract: A method of manufacturing a wafer. The method includes providing a wafer and testing the wafer. Based on a test result, a substance is selectively provided on the wafer to obtain an altered wafer that has at least one selected portion altered. The method includes forming a structural layer over the altered wafer.