Abstract: The present invention discloses a manufacturing method to reduce the surface roughness of the low temperature poly-silicon, including: a surface pretreatment is performed to a substrate with a a-Si layer on it, to form an oxidation layer on the a-Si layer. A first excimer laser annealing is performed on the substrate to make the a-Si layer into a poly-silicon layer; an acid liquid clean is used on the poly-silicon layer to remove the protrusions on the poly-silicon layer; a second excimer laser annealing is performed to the poly-silicon layer to obtain a low temperature poly-silicon layer with lower surface roughness. The manufacturing method is easy to operation and reduce the surface roughness of the low temperature poly-silicon layer with efficiency to obtain a low temperature poly-silicon layer with low roughness, uniform surface and well crystallization. A low temperature poly-silicon layer formed according to the present invention is also provided.

Abstract: A method of manufacturing a wafer. The method includes providing a wafer and testing the wafer. Based on a test result, a substance is selectively provided on the wafer to obtain an altered wafer that has at least one selected portion altered. The method includes forming a structural layer over the altered wafer.

Abstract: A test probe structure having a planar surface and contact locations matched to test hardware is provided. The fabrication of the test probe structure addresses problems related to the possible deformation of base substrates during manufacture. Positional accuracy of contact locations and planarity of base substrates is achieved using dielectric layers, laser ablation, injection molded solder or redistribution layer wiring, and planarization techniques.

Abstract: The present disclosure provides a device having a doped active region disposed in a substrate. The doped active region having an elongate shape and extends in a first direction. The device also includes a plurality of first metal gates disposed over the active region such that the first metal gates each extend in a second direction different from the first direction. The plurality of first metal gates includes an outer-most first metal gate having a greater dimension measured in the second direction than the rest of the first metal gates. The device further includes a plurality of second metal gates disposed over the substrate but not over the doped active region. The second metal gates contain different materials than the first metal gates. The second metal gates each extend in the second direction and form a plurality of respective N/P boundaries with the first metal gates.

Abstract: A light emitting device includes a metal layer, a light emitting structure, an electrode disposed on a first upper portion of a second conductive type semiconductor layer, a current spreading portion disposed on a second upper portion of the second conductive type semiconductor layer, an adhesive layer disposed under a first conductive type semiconductor layer, an insulating layer disposed between the electrode and the adhesive layer, a passivation layer disposed on a side surface of the light emitting structure and on a at least one upper surface of the light emitting structure, and a reflective layer disposed between the metal layer and the first conductive type semiconductor layer.

Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); an upper low-k (LK) dielectric layer over the lower ESL; a first conductive feature in the upper LK dielectric layer, wherein the first conductive feature has a first metal line and a dummy via contiguous with the first metal line, the dummy via extending through the lower ESL; a first gap along an interface of the first conductive feature and the upper LK dielectric layer; and an upper ESL over the upper LK dielectric layer, the first conductive feature, and the first gap.

Abstract: A method of manufacturing a semiconductor device includes forming a lower metal layer, forming an interfacial oxide film on the lower metal layer, providing a metal precursor on the interfacial oxide film at a first pressure to adsorb the metal precursor into the interfacial oxide film, performing a first purge process at a second pressure to remove the unadsorbed metal precursor, the second pressure lower than the first pressure, providing an oxidizing gas at the first pressure to react with the adsorbed metal precursor, performing a second purge process at the second pressure to remove the unreacted oxidizing gas and form a dielectric film, and forming an upper metal layer on the dielectric film.

Abstract: Embodiments of the present invention are directed to semiconductor electronic devices formed of 2-D van der Waals material whose free charge carrier concentration is determined by adjacent semiconductor's polarization. According to one particular embodiment, a semiconductor electronic device is composed of one or more layers of two dimensional (2-D) van der Waals (VDW) material; and one or more layers of polarized semiconductor material adjacent to the one or more layer of 2-D VDW material. The polarization of the adjacent semiconductor material establishes the free carrier charge concentration of the 2-D VDW material.

Abstract: The present invention relates to a method for manufacturing a light extraction substrate for an organic light emitting element, a light extraction substrate for an organic light emitting element, and an organic light emitting element that includes the same and, more specifically, to a method for manufacturing a light extraction substrate for an organic light emitting element, a light extraction substrate for an organic light emitting element, and an organic light emitting element that includes the same, which can enhance the light extraction efficiency of an organic light emitting element and, in particular, can reduce the process cost.

Abstract: According to one embodiment, a method is disclosed for manufacturing an integrated circuit device, the method can include forming a mask member on a first film, the mask member having a pattern, performing a first etching on the first film using the mask member as a mask to form a recessed section in the first film, forming a second film covering an inner side surface of the recessed section. The second film has a film thickness of preventing blockage of the recessed section, and performing a second etching on the second film and the first film via the recessed section. The performing of the second etching includes performing a third etching in a condition of an etching rate at a place smaller in curvature radius in the recessed section being lower than an etching rate at a place larger in curvature radius in the recessed section.

Abstract: A method for fabricating a capacitor includes following steps: providing a substrate and a first conducting material layer which is disposed on the substrate; removing a part of the first conducting material layer to expose a part of the substrate to form a plurality of first inner electrodes, wherein the first inner electrodes are arranged along a first direction, and the adjacent first inner electrodes have an interval therebetween; forming a dielectric layer along a second direction by a chemical vapor deposition process, wherein the first direction is perpendicular to the second direction so that the dielectric layer covers the first inner electrodes and the exposed part of the substrate, and the dielectric layer does not fully fill the intervals; and forming a second conducting material layer to fill the intervals that are not fully filled by the dielectric layer to form a plurality of second inner electrodes.

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first semiconductor layer, an insulating layer, and a second semiconductor layer; forming an active device on the substrate; forming an interlayer dielectric (ILD) layer on the substrate and the active device; forming a mask layer on the ILD layer; removing part of the mask layer, part of the ILD layer, and part of the insulating layer to form a first contact hole; forming a patterned mask on the mask layer and into the first contact hole; and removing part of the mask layer and part of the ILD layer to form a second contact hole exposing part of the active device.

Abstract: A hard mask stack for etching a magnetic tunneling junction (MTJ) structure is described. An electrode layer is deposited on a stack of MTJ layers on a bottom electrode. A photoresist mask is formed on the electrode layer. The electrode layer is etched away where it is not covered by the photoresist mask to form a metal hard mask. The metal hard mask is passivated during or after etching to form a smooth hard mask profile. Thereafter, the photoresist mask is removed and the MTJ structure is etched using the metal hard mask wherein the metal hard mask remaining acts as a top electrode. The resulting MTJ device has smooth sidewalls and uniform device shape.

Abstract: A silicon carbide semiconductor device includes an n+-type SiC substrate, a gate oxide film formed on a portion of the surface of the n+-type SiC substrate, a gate electrode formed on the gate oxide film, an interlayer insulating film formed so as to cover the gate electrode, a TiN film formed so as to cover the interlayer insulating film, and a Ni silicide layer formed on a surface of the n+-type SiC substrate not covered by the interlayer insulating film. The TiN film has two or more layers.

Abstract: To control temperature of a sample in plasma processing with high accuracy while securing an electrostatic chucking force 5 without breakdown of an electrostatic chucking film. When radio-frequency power is time modulated, a high-voltage side Vpp detector detects a first voltage value which is a peak-to-peak voltage value of a radio-frequency voltage applied to a sample stage in a first period of the time modulation having a 10 first amplitude. A low-voltage side Vpp detector detects a second voltage value which is a peak-to-peak voltage value of a radio-frequency voltage applied to the sample stage in a second period having a second amplitude smaller than the first amplitude. Then, an ESC power supply control unit controls output voltages from 15 ESC power supplies based on the first voltage value, the second voltage value and a duty ratio of the time modulation.

Abstract: A method and structure for forming a 3D chip stack using a vacuum chuck. The method may include: forming a first bonding layer on a first wafer and first chips, where the first chips are on a first substrate; forming a second bonding layer on a second wafer and second chips, where the second chips are on a second substrate; separating the second chips from the second wafer, wherein a portion of the second bonding layer remains on the second chips; moving the separated second chips to a cleaning chamber using a vacuum chuck; cleaning the separated second chips in the cleaning chamber; and bonding the second bonding layer on the separated second chips to the first bonding layer on the first chips.

Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a structure having an n-channel gate stack and a p-channel gate stack formed over a semiconductor substrate. The method includes forming halo implant regions in the semiconductor substrate adjacent the p-channel gate stack and forming extension implant regions in the semiconductor substrate adjacent the p-channel gate stack. The method further includes annealing the halo implant regions and the extension implant regions in the semiconductor substrate adjacent the p-channel gate stack. Also, the method forms extension implant regions in the semiconductor substrate adjacent the n-channel gate stack.

Abstract: The present invention provides a method for manufacturing a TFT substrate, in which after induced crystallization is conducted by implanting ions into an amorphous silicon layer, there is no need to completely remove the ion induction layer formed on the surface of a poly-silicon layer so obtained and instead, a half-tone mask based operation is applied to remove only a portion of the ion induction layer corresponding to a channel zone and there is no need for re-conducting ion implantation subsequently for source/drain contact zones, thereby saving the mask necessary for re-conducting ion implantation. Further, the source/drain electrodes are also formed with the half-tone mask based operation so as to save the mask necessary for making the source/drain electrodes. Further, the source/drain electrodes are formed first so that the formation of an interlayer insulation layer can be omitted thereby saving the mask necessary for forming the interlayer insulation layer.

Abstract: An electronic component, an optoelectronic component, a component arrangement, and a method for producing an electronic component are disclosed. In an embodiment, the method includes forming a sacrificial structure on a top side of a carrier by a photolithographic process from a photoresist layer, arranging an electronic semiconductor chip on the carrier after exposing the photoresist layer, molding a molded body around the sacrificial structure and around the electronic semiconductor chip such that a surface of the electronic semiconductor chip is at least partly not covered by the molded body, detaching the molded body from the carrier and removing the sacrificial structure, wherein removing the sacrificial structure results in a cutout being formed in the molded body.

Abstract: A method of manufacturing a nanowire device is disclosed. The method includes providing a substrate, wherein the substrate comprises a pair of support pads, a recess disposed between the support pads, a second insulating layer disposed on the support pads, a third insulating layer disposed on a bottom of the recess, and at least one nanowire suspended between the support pads at a top portion of the recess; forming a first insulating layer on the nanowire; depositing a dummy gate material over the substrate on the first insulating layer, and patterning the dummy gate material to form a dummy gate structure surrounding a channel region; forming a first oxide layer on laterally opposite sidewalls of the dummy gate; and extending the nanowire on laterally opposite ends of the channel region to the respective support pads, so as to form a source region and a drain region.