Patents Examined by Zandra Smith
  • Patent number: 9871105
    Abstract: A method includes forming an isolation structure in a well of a substrate. A portion of the isolation structure protrudes from a top surface of the well. The isolation structure is partially removed, thereby forming a modified isolation structure. An upper surface of the modified isolation structure is lower than the upper surface of the substrate.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: January 16, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Chih Chou, Kong-Beng Thei
  • Patent number: 9871098
    Abstract: A semiconductor device may include a semiconductor substrate in which a semiconductor element is provided, and an insulation film provided on the semiconductor substrate, in which the semiconductor substrate may include a first portion and a second portion which has a thickness thinner than a thickness of the first portion, an upper surface of the second portion may be positioned lower than an upper surface of the first portion, a recess extending in a thickness direction of the semiconductor substrate may be provided on the upper surface of the second portion located at a position where the first portion and the second portion adjoin to each other, and the insulation film may extend over from the first portion to the second portion, and fill the recess.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: January 16, 2018
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Jun Saito, Atsushi Onogi, Sachiko Aoi, Shoji Mizuno
  • Patent number: 9871122
    Abstract: A method of fabricating a semiconductor device includes providing a substrate that includes first and second main regions and a dummy region, and forming dummy active patterns on the dummy region. The first and second main regions are spaced apart from each other in a first direction and the dummy region includes a dummy connection region between the first and second main regions and first and second dummy cell regions spaced apart from each other in a second direction. First dummy active patterns, second dummy active patterns, and connection dummy active patterns connecting some of the first dummy active patterns to some of the second dummy active patterns are provided on the first and second dummy cell regions and the dummy connection region, respectively.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: January 16, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: In-Wook Oh, Hyunjae Lee, Jaeseok Yang
  • Patent number: 9865809
    Abstract: According to one embodiment, a nonvolatile resistance change element includes a first electrode, a second electrode and a first layer. The first electrode includes a metal element. The second electrode includes an n-type semiconductor. The first layer is formed between the first electrode and the second electrode and includes a semiconductor element. The first layer includes a conductor portion made of the metal element. The conductor portion and the second electrode are spaced apart.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: January 9, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hidenori Miyagawa, Akira Takashima, Shosuke Fujii
  • Patent number: 9865575
    Abstract: Methods of forming conductive and insulating layers for semiconductor devices and packages. Substrate is provided with integrated circuit device and interconnect structure mounted thereon, the interconnect structure adjacent the integrated circuit device. The integrated circuit device and portions of the interconnect structure can be covered with an encapsulation exposing a portion of the interconnect structure. Conductive material is formed over the exposed portion of the interconnect structure by a depositing process followed by a heating process to alter the chemical properties of the conductive material. Optionally, a dispersing process may be incorporated.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: January 9, 2018
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: HeeJo Chi, HanGil Shin, KyungMoon Kim
  • Patent number: 9865638
    Abstract: A semiconductor device includes a first semiconductor substrate having a first wiring layer which includes a first conductive pad, a second semiconductor substrate disposed on the first semiconductor substrate and including a second wiring layer which includes a second conductive pad, a first oxide layer disposed on the second semiconductor substrate and containing a second end of an intermediate connection which extends vertically through the second semiconductor substrate and has a first end electrically connected to the second conductive pad, and a third semiconductor substrate disposed on the first oxide layer and including a third wiring layer which includes a third conductive pad. The second end of the intermediate connection layer is electrically connected to the third conductive pad via a metal bond.
    Type: Grant
    Filed: November 16, 2016
    Date of Patent: January 9, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Doo Won Kwon
  • Patent number: 9865816
    Abstract: A solution contains a functional material for constituting a function layer, and a solvent. The solvent contains a high-boiling-point solvent composed of one or more solvent components having a boiling point of not less than 200° C. The high-boiling-point solvent has a viscosity of from 13 mPa·s to 25 mPa·s, inclusive, and a surface tension of from 33 mN/m to 37 mN/m, inclusive.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: January 9, 2018
    Assignee: JOLED INC.
    Inventors: Masakazu Takata, Hirotaka Nanno
  • Patent number: 9865486
    Abstract: Systems and methods for optimizing timing/power risk SVB using a customer-supplied, non-linear voltage slope. Chips are manufactured according to an integrated circuit design. The minimum operating voltage and hardware variations for each device in the design is determined and a process distribution for the chips is divided into process windows. Vmax and Vmin to support system frequency are determined for each process window. Vmin vs. process-bin mean and sigma sensitivity is calculated using information about specific devices. The voltage for each process window that generates Vmin for specific devices is identified. Power at the slow end and fast end of each process window is evaluated using the voltage to support system frequency. Pmax is determined. Vmax for each process window that generates Pmax is determined. A voltage is identified between Vmin and Vmax that maximizes the timing margin for system frequency while minimizing risk for Pmax.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: January 9, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Igor Arsovski, Jeanne P. Bickford, Mark W. Kuemerle, Susan K. Lichtensteiger, Jeanne H. Raymond
  • Patent number: 9865522
    Abstract: Composite heat sink structures and methods of fabrication are provided, with the composite heat sink structures including: a thermally conductive base having a main heat transfer surface to couple to, for instance, at least one electronic component to be cooled; a compressible, continuous sealing member; and a sealing member retainer compressing the compressible, continuous sealing member against the thermally conductive base; and an in situ molded member. The in situ molded member is molded over and affixed to the thermally conductive base, and is molded over and secures in place the sealing member retainer. A coolant-carrying compartment resides between the thermally conductive base and the in situ molded member, and a coolant inlet and outlet are provided in fluid communication with the coolant-carrying compartment to facilitate liquid coolant flow through the compartment.
    Type: Grant
    Filed: November 18, 2014
    Date of Patent: January 9, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Levi A. Campbell, Milnes P. David, Dustin W. Demetriou, Michael J. Ellsworth, Jr., Roger R. Schmidt, Robert E. Simons
  • Patent number: 9859485
    Abstract: A method for packaging a thermoelectric module may include thermoelectric module accommodation, of accommodating at least one thermoelectric module in a housing having a base and a sidewall, electric wire sealing, of sealing an electric wire of the thermoelectric module with a sealing tube, bonding member interposing, of placing a cover having a top portion and a sidewall on top of the housing and interposing a bonding member between the sidewall of the housing and the sidewall of the cover, and bonding, of bonding the sidewall of the housing and the sidewall of the cover that are hermetically sealed by the bonding member, in which the bonding member may be formed of a resin material.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: January 2, 2018
    Assignee: Hyundai Motor Company
    Inventors: Byung Wook Kim, Kyong Hwa Song, Jin Woo Kwak, Gyung Bok Kim, In Woong Lyo, Han Saem Lee
  • Patent number: 9859299
    Abstract: Provided herein is a semiconductor device including: a channel layer; a data storage layer surrounding the channel layer and extending along the channel layer; interlayer insulating layers surrounding the data storage layer and stacked along the channel layer, wherein the interlayer insulating layers are spaced apart from each other, wherein a conductive area is disposed between the interlayer insulating layers; a conductive pattern disposed in the conductive area and surrounding the data storage layer; buffer patterns disposed between the interlayer insulating layers and the data storage layer and surrounding the data storage layer, wherein each of the buffer patterns includes a densified area, wherein the buffer patterns are separated from each other by the conductive area; and a blocking insulating pattern disposed between the conductive pattern and the data storage layer and surrounding the data storage layer.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: January 2, 2018
    Assignee: SK Hynix Inc.
    Inventors: In Su Park, Ki Hong Lee, Hye Jeong Cheon
  • Patent number: 9859283
    Abstract: A semiconductor memory structure includes a substrate including a memory cell region, a peripheral circuit region and a cell edge region defined thereon, and the cell edge region is defined in between the memory cell region and the peripheral circuit region. The semiconductor memory structure includes a plurality of active regions formed in the memory cell region, the cell edge region and the peripheral circuit region, and at least a dummy bit line formed on the active regions in the cell edge region. The dummy bit line is extended along a first direction and overlaps at least two active regions in a second direction. And the first direction and the second direction are perpendicular to each other. The dummy bit line includes a first inner line portion and an outer line portion, and the first inner line portion and the outer line portion include different widths and different spacers.
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: January 2, 2018
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Li-Wei Feng, Chien-Ting Ho, Yu-Cheng Tung
  • Patent number: 9859492
    Abstract: A patterning method includes forming an etch-target layer on a substrate, forming mask patterns on the etch-target layer, and etching the etch-target layer using the mask patterns as an etch mask to form patterns spaced apart from each other. The etching process of the etch-target layer includes irradiating the etch-target layer with an ion beam, whose incident energy ranges from 600 eV to 10 keV. A recess region is formed in the etch-target layer between the mask patterns, and the ion beam is incident onto a bottom surface of the recess region at a first angle with respect to a top surface of the substrate and is incident onto an inner side surface of the recess region at a second angle with respect to the inner side surface of the recess region. The first angle ranges from 50° to 90° and the second angle ranges from 0° to 40°.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: January 2, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jongchul Park, Hyungjoon Kwon, Inho Kim, Jongsoon Park
  • Patent number: 9851379
    Abstract: A test probe structure having a planar surface and contact locations matched to test hardware is provided. The fabrication of the test probe structure addresses problems related to the possible deformation of base substrates during manufacture. Positional accuracy of contact locations and planarity of base substrates is achieved using dielectric layers, laser ablation, injection molded solder or redistribution layer wiring, and planarization techniques.
    Type: Grant
    Filed: March 25, 2017
    Date of Patent: December 26, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bing Dang, John U. Knickerbocker, Jae-Woong Nah, Robert E. Trzcinski, Cornelia Kang-I Tsang
  • Patent number: 9847316
    Abstract: A method of producing optoelectronic components includes providing an auxiliary carrier, forming separate connection elements on the auxiliary carrier, forming a molded body on the auxiliary carrier with recesses, arranging optoelectronic semiconductor chips on connection elements in the recesses of the molded body, removing the auxiliary carrier, and severing the molded body to form singulated optoelectronic components.
    Type: Grant
    Filed: February 18, 2015
    Date of Patent: December 19, 2017
    Inventors: Martin Brandl, Tobias Gebuhr
  • Patent number: 9847253
    Abstract: A semiconductor package-on-package (PoP) device includes a first die incorporating a through-hole via (THV) disposed along a peripheral surface of the first die. The first die is disposed over a substrate or leadframe structure. A first semiconductor package is electrically connected to the THV of the first die, or electrically connected to the substrate or leadframe structure. An encapsulant is formed over a portion of the first die and the first semiconductor package.
    Type: Grant
    Filed: April 9, 2010
    Date of Patent: December 19, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Byung Tai Do, Heap Hoe Kuan, Seng Guan Chow
  • Patent number: 9842780
    Abstract: A method for ensuring wafer level reliability is provided. The method involves: forming a gate oxide layer having a thickness of less than 50 ? on a semiconductor substrate; forming a PMOS element having a channel length of less than 0.13 ?m on the semiconductor substrate; and assessing hot carrier injection (HCl) for the PMOS element.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: December 12, 2017
    Assignee: Magnachip Semiconductor, Ltd.
    Inventors: KyeNam Lee, HyunHo Jang
  • Patent number: 9842795
    Abstract: A power device includes a semiconductor chip provided over a substrate, and a patterned lead. The patterned lead includes a raised portion located between a main portion and an end portion. At least part of the raised portion is positioned over the semiconductor chip at a larger height than both the main portion and the end portion. A bonding pad may also be included. The end portion may include a raised portion, bonded portion, and connecting portion. At least part of the bonded portion is bonded to the bonding pad and at least part of the raised portion is positioned over the bonding pad at a larger height than the bonded portion and connecting portion. The end portion may also include a plurality of similarly raised portions.
    Type: Grant
    Filed: July 1, 2014
    Date of Patent: December 12, 2017
    Assignee: IXYS Corporation
    Inventors: Nathan Zommer, Kang Rim Choi
  • Patent number: 9825004
    Abstract: A semiconductor device includes a package interface including N numbers of first group of data balls which are disposed on a first side thereof, N numbers of second group of data balls which are disposed on a second side thereof, and M numbers of command/address balls which are disposed between the first side and the second side; a first semiconductor chip which is stacked on the first side over the package interface, and includes 2N numbers of first group of data pads and M numbers of first command/address pads; and a second semiconductor chip which is stacked on the second side over the package interface, and includes 2N numbers of second group of data pads and M numbers of second command/address pads.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: November 21, 2017
    Assignee: SK Hynix Inc.
    Inventor: Ho-Don Jung
  • Patent number: 9825118
    Abstract: A high voltage metal-oxide-metal (HV-MOM) layout includes a first conductive element. The first element includes a first leg extending in a first direction, a second leg connected to the first leg, the second leg extending in a second direction different from the first direction, and a third leg connected to the second leg, the third leg extending in a first direction. The HV-MOM layout further includes a second conductive element separated from the first conductive element by a space. The second conductive element includes a serpentine structure, wherein the serpentine structure is enclosed on at least three sides by the first conductive element. The HV-MOM layout further includes a dielectric material filling the space between the first conductive element and the second conductive element.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: November 21, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Chung Chen, Shu Fang Fu, Chang-Sheng Liao