Patents Examined by Zandra V. Smith
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Patent number: 11133328Abstract: A semiconductor device includes: a stack structure including horizontal conductive patterns and interlayer insulating layers, which are alternately stacked; gate patterns overlapping with both ends of the stack structure under the stack structure, the gate patterns being spaced apart from each other; and a channel pattern including vertical parts penetrating the stack structure, and a connection part disposed under the stack structure, the connection part connecting the vertical parts.Type: GrantFiled: June 26, 2019Date of Patent: September 28, 2021Assignee: SK hynix Inc.Inventor: Kang Sik Choi
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Patent number: 11127668Abstract: A semiconductor device comprises a first semiconductor package including a conductive layer. A substrate including an interconnect structure is disposed over the conductive layer. The interconnect structure of the substrate with the conductive layer of the first semiconductor package are self-aligned. A plurality of openings is formed in the substrate. An adhesive is disposed between the substrate and the first semiconductor package and in the openings of the substrate. A redistribution layer (RDL) is formed over the first semiconductor package opposite the substrate. A pitch of the substrate is different from a pitch of the RDL. The adhesive extends to the interconnect structure of the substrate. A second semiconductor package is disposed over the substrate and the first semiconductor package.Type: GrantFiled: September 13, 2019Date of Patent: September 21, 2021Inventors: Il Kwon Shim, Pandi C. Marimuthu, Won Kyoung Choi, Sze Ping Goh, Jose A. Caparas
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Patent number: 11127660Abstract: Methods are disclosed for forming flat no-leads packages (e.g., QFN packages) with soldering surfaces that are fully coated, e.g., by a tin immersion process, for improved solder connections of the packages to a PCB or other structure. The method includes forming a flat no-leads package structure including a leadframe terminal structure having an exposed top or bottom surface; forming a first coating of a first coating material (e.g., tin) on the exposed top or bottom surface; cutting through a full thickness of the leadframe terminal structure to define an exposed terminal sidewall surface; and forming a second coating of a second coating material (e.g., tin) over the full height of the exposed terminal sidewall surface. The coating (e.g., tin immersion coating) covering the full height of the leadframe terminal sidewall may enhance the flow of solder material, e.g., when soldering to a PCB, to provide an improved solder connection.Type: GrantFiled: December 19, 2019Date of Patent: September 21, 2021Assignee: Microchip Technology IncorporatedInventors: Rangsun Kitnarong, Vichanart Nimibutr, Pattarapon Poolsup, Chanyuth Junjuewong
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Patent number: 11127755Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a gate electrode above the substrate, a blocking layer on the gate electrode, a plurality of charge trapping layers on the blocking layer, a tunneling layer on the plurality of charge trapping layers, and a plurality of channel layers on the tunneling layer. The plurality of charge trapping layers are discrete and disposed at different levels. The plurality of channel layers are discrete and disposed at different levels. Each of the channel layers corresponds to a respective one of the charge trapping layers.Type: GrantFiled: December 26, 2019Date of Patent: September 21, 2021Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventor: Hongbin Zhu
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Patent number: 11127694Abstract: A physical unclonable functions (PUF) device including a first copper electrode, a second electrode, and a silicon oxide layer positioned directly between the first copper electrode and the second electrode; a method of producing a PUF device; an array comprising a PUF device; and a method of generating a secure key with a plurality of PUF devices.Type: GrantFiled: March 23, 2018Date of Patent: September 21, 2021Assignee: ARIZONA BOARD OF REGENTS ON BEHALF OF ARIZONA STATE UNIVERSITYInventors: Michael Kozicki, Wenhao Chen
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Patent number: 11127825Abstract: A method of forming a semiconductor structure includes forming a first portion of a source/drain contact over a source/drain region of a fin-type field-effect transistor (FinFET), the source/drain region being formed over a fin providing a channel region of the FinFET and being adjacent a gate spacer surrounding a gate region of the FinFET. The method also includes forming a first interlayer dielectric (ILD) layer over the first portion of the source/drain contact, the gate spacer and the gate region, and forming a second ILD layer over the first ILD layer. The method further includes forming a second portion of the source/drain contact over the first portion of the source/drain contact in a first opening in the first ILD layer, and forming a third portion of the source/drain contact over the second portion of the source/drain contact in a second opening in the second ILD layer. The second opening is larger than the first opening.Type: GrantFiled: March 22, 2019Date of Patent: September 21, 2021Assignee: International Business Machines CorporationInventors: Chanro Park, Kangguo Cheng, Ruilong Xie, Hari Prasad Amanapu
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Patent number: 11127857Abstract: Semiconductor devices and methods of manufacturing semiconductor devices are provided. In embodiments a treatment process is utilized in order to introduce silicon into a p-metal work function layer. By introducing silicon into the p-metal work function layer, subsequently deposited layers which may comprise diffusable materials such as aluminum can be prevented from diffusing through the p-metal work function layer and affect the operation of the device.Type: GrantFiled: April 12, 2019Date of Patent: September 21, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsin-Yi Lee, Da-Yuan Lee, Ching-Hwanq Su
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Patent number: 11121146Abstract: A termination opening can be formed through the stack alternating dielectrics concurrently with forming contact openings through the stack. A termination structure can be formed in the termination opening. An additional opening can be formed through the termination structure and through the stack between groups of semiconductor structures that pass through the stack. In another example, an opening can be formed through the stack so that a first segment of the opening is between groups of semiconductor structures in a first region of the stack and a second segment of the opening is in a second region of the stack that does not include the groups of semiconductor structures. A material can be formed in the second segment so that the first segment terminates at the material. In some instances, the material can be implanted in the dielectrics in the second region through the second segment.Type: GrantFiled: October 15, 2018Date of Patent: September 14, 2021Assignee: Micron Technology, Inc.Inventors: Matthew J. King, Anilkumar Chandolu, Indra V. Chary, Darwin A. Clampitt, Gordon Haller, Thomas George, Brett D. Lowe, David A. Daycock
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Patent number: 11121026Abstract: Methods of patterning openings for conductive contacts in a target layer of a semiconductor device and methods of forming conductive contacts. The method of patterning openings may be used to form contact openings in an inter-layer dielectric (ILD) layer of a semiconductor substrate for contacts to source/drain regions of FinFET devices. A hard mask layer may be patterned to form a cut mask by transferring slotted openings of a first middle layer of a tetra-layer photoresist and a cut MD pattern of a photoresist layer formed over the first middle layer of the tetra-layered photoresist using photolithography techniques. Once the cut mask is formed, contact openings are formed within the ILD layer down to the source/drain regions of the FinFET devices of the semiconductor substrate. The contact openings may be filled with conductive material(s) to define conductive contacts (e.g., conductive plugs).Type: GrantFiled: December 3, 2018Date of Patent: September 14, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Yu-Lien Huang
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Patent number: 11121033Abstract: A method for fabricating a semiconductor device includes forming a through-hole penetrating through an alternating stack pattern and forming a gap-fill layer, wherein a sacrificial gap-fill layer of the gap-fill layer fills the through-hole. The method also includes forming a mask layer over the alternating stack pattern and over the gap-fill layer, wherein the mask layer includes a self-aligned opening overlapping the filled through-hole and overlapping a portion of an uppermost material layer of the alternating stack pattern adjacent to the filled through-hole. The method further includes forming a first contact hole through the alternating stack pattern by performing a single etch using both the mask layer and the portion of the uppermost material layer as etch barriers to remove, through the self-aligned opening, the sacrificial gap-fill layer filling the through-hole.Type: GrantFiled: September 17, 2019Date of Patent: September 14, 2021Assignee: SK hynix Inc.Inventors: Ki-Hong Yang, Ki-Hong Lee
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Patent number: 11121144Abstract: A method used in forming a memory array comprises forming a stack comprising vertically-alternating first tiers and second tiers. First insulator material is above the stack. The first insulator material comprises at least one of (a) and (b), where (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide. Channel-material strings are in and upwardly project from an uppermost material that is directly above the stack. Conducting material is directly against laterally-inner sides of individual of the upwardly-projecting channel-material strings and project upwardly from the individual upwardly-projecting channel-material strings. A ring comprising insulating material is formed individually circumferentially about the upwardly-projecting conducting material. Second insulator material is formed above the first insulator material, the ring, and the upwardly-projecting conducting material.Type: GrantFiled: November 13, 2019Date of Patent: September 14, 2021Assignee: Micron Technology, Inc.Inventors: Bharat Bhushan, David Daycock, Subramanian Krishnan, Leroy Ekarista Wibowo
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Patent number: 11121029Abstract: The present disclosure provides a semiconductor device and a method for preparing the semiconductor device. The method includes forming a first conductive layer over a substrate, forming a first dielectric structure over the first conductive layer, transforming a sidewall portion of the first conductive layer into a first transformed portion, removing the first transformed portion such that a width of the first dielectric structure is greater than a width of a remaining portion of the first conductive layer, and forming an inter-layer dielectric (ILD) layer covering sidewalls of the first dielectric structure such that a first air spacer is formed between the ILD layer and the remaining portion of the first conductive layer.Type: GrantFiled: August 21, 2019Date of Patent: September 14, 2021Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Jung-Hsing Chien
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Patent number: 11121004Abstract: A method for producing a power semiconductor module arrangement includes forming a pre-layer by depositing inorganic filler on a first surface within a housing, the inorganic filler being impermeable to corrosive gases. The method further includes filling casting material into the housing to fill spaces present in the inorganic filler of the pre-layer with the casting material, and hardening the casting material to form a first layer.Type: GrantFiled: January 15, 2019Date of Patent: September 14, 2021Assignee: Infineon Technologies AGInventors: Gopalakrishnan Trichy Rengarajan, Sebastian Michalski
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Patent number: 11121142Abstract: A method of manufacturing a memory structure including the following steps is provided. A spacer layer is formed on sidewalls of gate stack structures. A protective material layer covering the spacer layer and the gate stack structures is formed. A mask material layer is formed on the protective material layer. There is a void located in the mask material layer between two adjacent gate stack structures. A first distance is between a top of the protective material layer and a top of the mask material layer. A second distance is between a top of the void and a top of the mask material layer above the void. A third distance is between a bottom of the void and a bottom of the mask material layer below the void. The first distance is greater than a sum of the second and third distances.Type: GrantFiled: December 31, 2019Date of Patent: September 14, 2021Assignee: Winbond Electronics Corp.Inventors: Che-Jui Hsu, Chun-Sheng Lu, Ying-Fu Tung, Chen-Wei Liao
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Patent number: 11121304Abstract: A method of making a Josephson junction for a superconducting qubit includes providing a substructure having a surface with first and second trenches perpendicular to each other defined therein. The method further includes evaporating a first superconducting material to deposit the first superconducting material and evaporating a second superconducting material to deposit the second superconducting material in the first trench to provide a first lead, and forming an oxidized layer on the first and second superconducting materials. The method includes evaporating a third superconducting material at an angle substantially perpendicular to the surface of the substructure to deposit the third superconducting material in the second trench without rotating the substructure to form a second lead. A vertical Josephson junction is formed at the intersection of the first and second trenches electrically connected through the first lead and through the second lead.Type: GrantFiled: November 14, 2019Date of Patent: September 14, 2021Assignee: International Business Machines CorporationInventors: Vivekananda P. Adiga, Benjamin B. Wymore, Keith Fogel, Martin O. Sandberg
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Patent number: 11114394Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes an article having a substrate, a semiconductor die thereon, a routing carrier attached to the substrate, and a transmission pathway electrically connected to the semiconductor die and the substrate, wherein the transmission pathway runs through the routing carrier. In selected examples, the article is made by manufacturing a substrate, attaching a semiconductor die to the substrate, fabricating a routing carrier comprising a transmission pathway, and integrating the routing carrier into the substrate.Type: GrantFiled: August 9, 2019Date of Patent: September 7, 2021Assignee: Intel CorporationInventors: Lijiang Wang, Jianyong Xie, Sujit Sharan, Robert L. Sankman
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Patent number: 11107748Abstract: A semiconductor module is provided to downsize the module, the semiconductor module including a terminal case made of a resin for housing a semiconductor chip; and a cooling portion including a refrigerant circulating portion through which a refrigerant flows and a joining portion surrounding the refrigerant circulating portion, the refrigerant circulating portion being arranged below the terminal case, and the cooling portion being arranged directly or indirectly in close contact with the terminal case at the joining portion, wherein the terminal case is provided above the joining portion, and has a side wall provided so as to surround the semiconductor chip when seen in a top view, and a temperature sensor for sensing a temperature of the refrigerant is provided on the side wall.Type: GrantFiled: August 1, 2019Date of Patent: August 31, 2021Assignee: FUJI ELECTRIC CO., LTD.Inventor: Shinichiro Adachi
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Patent number: 11107834Abstract: Embodiments of staircase and contact structures of a three-dimensional (3D) memory device and fabrication method thereof are disclosed. The 3D memory device includes a semiconductor substrate and a plurality of through-substrate-trenches penetrating the semiconductor substrate. The 3D memory device also includes a film stack disposed on a first surface of the semiconductor substrate extending through the through-substrate-trenches to a second surface of the semiconductor substrate, wherein the film stack includes alternating conductive and dielectric layers. The 3D memory device also includes a staircase structure formed at an edge of the film stack.Type: GrantFiled: August 25, 2020Date of Patent: August 31, 2021Assignee: Yangtze Memory Technologies Co., Ltd.Inventor: Li Hong Xiao
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Patent number: 11107697Abstract: A floating gate fabrication method is disclosed. The method includes: providing a substrate, and depositing an oxide layer on the substrate; fabricating a shallow trench isolation in the substrate, a top surface of the shallow trench isolation being higher than a top surface of the oxide layer; depositing a polysilicon layer on the oxide layer and the shallow trench isolation; performing a first thermal annealing process on the polysilicon layer, thereby repairing cavities formed after the deposition of the polysilicon layer; implanting ions into the polysilicon layer; performing a second thermal annealing process on the polysilicon layer, thereby activating the implanted ions and repairing again the cavities formed after the deposition of the polysilicon layer; and planarizing the polysilicon layer to form a floating gate.Type: GrantFiled: December 5, 2018Date of Patent: August 31, 2021Assignee: WUHAN XINXIN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chaoran Zhang, Jun Zhou, Yun Li
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Patent number: 11101130Abstract: A method of forming a pattern of metallic material on a substrate includes providing a plurality of void regions on a surface of the substrate. At a first temperature, a first layer of a first metallic material of a eutectic-forming pair of metallic materials is deposited on the substrate to form a conformal metallic film over the substrate and over the surfaces of the plurality of void regions. The substrate and conformal metallic film are warmed to a second temperature greater than a eutectic-liquid-formation temperature of the eutectic pair of metallic materials. At the second temperature, the second metallic material of the eutectic-forming pair of metallic materials is deposited on the conformal metallic film to initiate a eutectic-liquid-forming reaction, such that the plurality of void regions are filled with a mixture of the first and second metallic materials of the eutectic-forming pair of metallic materials.Type: GrantFiled: September 13, 2019Date of Patent: August 24, 2021Assignee: RAYTHEON COMPANYInventors: Andrew Clarke, Robert M. Emerson, George Grama, June-Marie Boll