Abstract: The invention provides a lighting device configured to provide white lighting device light, the lighting device comprising (i) a light source, configured to provide blue light source light, and (ii) a luminescent material element, configured to absorb at least part of the blue light source light and to convert into luminescent material light, wherein the luminescent material element comprises a luminescent material which consists for at least 80 wt. % of a M2-2xEu2xSi5-yAlyOyN8-y phosphor, wherein M comprises one or more of Mg, Ca, Sr, Ba, with a molar ratio of (Mg+Ca+Sr)/(Ba)?0.1, wherein x is in the range of 0.001-0.02, wherein y is in the range of ?0.2, and wherein the white lighting device light comprises said blue light source light and said luminescent material light.

Abstract: Methods are disclosed for forming flat leads packages (e.g., QFP or SOT packages) having leads coated with a solder-enhancing material for improved solder mounting to a PCB or other structure. The method may include forming a flat leads package structure including an array of encapsulated IC structures formed on a common leadframe. An isolation cutting process may be performed to electrically isolate the IC structures from each other and define a plurality of leadframe leads extending from each IC structure. After the isolation cutting process, an immersion coating process is performed to coat exposed surfaces of the leadframe leads, including the full surface area of a distal end of each leadframe lead. The coating (e.g., tin coating) covering the distal ends of the leadframe leads may enhance the flow of solder material, e.g., when soldering to a PCB, to provide an improved solder connection.

Abstract: A semiconductor device includes a first active pattern extending lengthwise along a first direction and a second active pattern extending lengthwise along the first direction and spaced apart from the first active pattern in the first direction. The device also includes a field insulating film between the first active pattern and the second active pattern. An upper surface of the field insulating film is lower than or coplanar with upper surfaces of the first and second active patterns. The device further includes an element isolation structure in an isolation trench in the first active pattern and the field insulating film. An upper surface of the element isolation structure is higher than the upper surfaces of the first and second active patterns.

Abstract: Example methods for fabricating a semiconductor device and example semiconductor devices are disclosed. An example method may include forming a sacrificial gate structure on a substrate, and the sacrificial gate structure may include a first portion and a second portion. The method may further include, removing the first portion of the sacrificial gate structure and forming an oxide film by oxidizing an upper surface of the second portion of the sacrificial gate structure after removing the first portion of the sacrificial gate structure. The method may additionally include, forming a trench on the substrate by removing the oxide film and the second portion of the sacrificial gate structure; and forming a gate electrode that fills the trench.

Abstract: A waterjet nozzle is provided for deflashing a leadless package device. The waterjet nozzle has a central core having a conically shaped passage between a nozzle inlet, lying in a first plane, and a nozzle outlet, lying in a second plane. The nozzle includes a groove, in the waterjet nozzle, above a third plane defining an end of the waterjet nozzle, along a first line in the third plane. A tube connects the nozzle outlet to the groove. The nozzle includes a flange, lying below the third plane along a second line, in the third plane, intersecting the first line. The waterjet nozzle may be used to deflash a leadframe package by inserting the flange from a waterjet nozzle into a singulation cut on a lead frame; and injecting a waterjet through the conically-shaped passage from the nozzle inlet through the nozzle outlet.

Abstract: The invention discloses a transistor, a three dimensional memory device including such transistors and a method of fabricating such memory device. The transistor according to the invention includes a pillar of a semiconductor material, extending in a normal direction of a semiconductor substrate, a gate dielectric layer and a gate conductor. The pillar of the semiconductor material has a base side face parallel to the normal direction, a tapered side face opposite to the base side face, a top face perpendicular to the normal direction, a bottom face opposite to the top face, a front side face adjacent to the base side face and the tapered side face, and a rear side face opposite to the front side face. A first elongated portion, sandwiched among the base side face, the front side face, the bottom face and the top face, forms a source region. A second elongated portion, sandwiched among the base side face, the rear side face, the bottom face and the top face, forms a drain region.

Abstract: Group III nitride based light emitting diode (LED) structures include multiple quantum wells with barrier-well units that include Ill nitride interface layers. Each interface layer may have a thickness of no greater than about 30% of an adjacent well layer, and a comparatively low concentration of indium or aluminum. One or more interface layers may be present in a barrier-well unit. Multiple barrier-well units having different properties may be provided in a single active region.

Abstract: An electronic device is provided, which includes a window including a transparent area and an opaque area; a panel disposed below the transparent area and including multiple pixels; a substrate disposed below the panel; an optical adhesive member disposed between the window and the panel; and a filler member disposed in at least a portion of a space formed between the opaque area and the substrate. The filler member transmits a light of a designated band, which is for curing the optical adhesive member, to a portion of the optical adhesive member disposed below the opaque area through a separation space between the filler member and the portion of the optical adhesive member.

Abstract: An image sensor device is provided. The image sensor device includes a substrate having a front surface, a back surface, and a light-sensing region. The image sensor device includes a first isolation structure extending from the front surface into the substrate. The first isolation structure includes a first insulating layer and an etch stop layer, the first insulating layer extends from the front surface into the substrate, the etch stop layer is between the first insulating layer and the substrate, and the etch stop layer, the first insulating layer, and the substrate are made of different materials. The image sensor device includes a second isolation structure extending from the back surface into the substrate. The second isolation structure is in direct contact with the etch stop layer, the second isolation structure surrounds the light-sensing region, and the second isolation structure includes a light-blocking structure.

Abstract: An object of the present invention is to improve manufacturing efficiency of a semiconductor device. The method of manufacturing a semiconductor device includes a sealing step of sealing a semiconductor chip mounted on the wiring substrate. The sealing step includes a step of arranging the wiring substrate between an upper mold and a lower mold, suctioning a lower surface of the wiring substrate with the plurality of suction holes, thereby holding the wiring substrate the upper mold, and a step of sealing the semiconductor chip, an upper surface of the wiring substrate, and the plurality of side surfaces of the wiring substrate such that each of the semiconductor chip, the upper surface of the wiring substrate, and the plurality of side surfaces of the wiring substrate is covered with the resin in the lower mold.

Abstract: An electronic device includes a package structure with opposite first and second sides spaced apart along a first direction, opposite third and fourth sides spaced apart along a second direction, opposite fifth and sixth sides spaced apart along a third direction, the first, second, and third directions being orthogonal to one another. A set of first leads extend outward from the first side along the first direction, a set of second leads extend outward from the second side along the first direction, and a thermal pad includes a first portion that extends along a portion of the fifth side, and a second portion that extends along a portion of the third side to facilitate cooling and visual solder inspection when soldered to a host printed circuit board.

Abstract: A method of manufacturing a device in a semiconductor body includes forming a first field stop zone portion of a first conductivity type and a drift zone of the first conductivity type on the first field stop zone portion. An average doping concentration of the drift zone is smaller than 80% of that of the first field stop zone portion. The semiconductor body is processed at a first surface and thinned by removing material from a second surface. A second field stop zone portion of the first conductivity type is formed by implanting protons at one or more energies through the second surface. A deepest end-of-range peak of the protons is set in the first field stop zone portion at a vertical distance to a transition between the drift zone and first field stop zone portion in a range from 3 ?m to 60 ?m. The semiconductor body is annealed.

Abstract: A gate structure is formed over a substrate. The gate structure includes a gate electrode and a hard mask located over the gate electrode. The hard mask comprises a first dielectric material. A first interlayer dielectric (ILD) is formed over the gate structure. The first ILD comprises a second dielectric material different from the first dielectric material. A first via is formed in the first ILD. Sidewalls of the first via are surrounded by spacers that comprise the first dielectric material. A second ILD is formed over the first ILD. A via hole is formed in the second ILD. The via hole exposes the first via. A protective layer is formed in the via hole. A bottom segment of the protective layer is removed. Thereafter, an etching process is performed. A remaining segment of the protective layer prevents an etching of the spacers during the etching process.

Abstract: A semiconductor device and a fabricating method of the same are provided. The semiconductor device a substrate including an active region defined by an element isolation film, an impurity region having a first conductivity type in the active region, a first semiconductor film of a second conductivity type on the impurity region, a buried insulating film on the first semiconductor film, a second semiconductor film on the buried insulating film, and a well contact connected to the first semiconductor film. The level of a lowermost surface of the first semiconductor film is higher than a level of a lowermost surface of the element isolation film.

Abstract: The present disclosure discloses an organic light-emitting diode display panel and a manufacturing method thereof and a display device, and relates to the field of display technologies. The organic light-emitting diode display panel comprises: a base substrate; a pixel defining layer and a plurality of first electrodes on the base substrate, wherein the pixel defining layer defines, on the base substrate, a plurality of sub-pixel regions arranged in an array, one of the first electrodes is located in each of the sub-pixel regions, and the work function of a middle portion of the first electrode is less than the work function of a peripheral portion; an organic light-emitting layer on each of the first electrodes; and a second electrode electrically connected to the organic light-emitting layer, wherein the first electrode is an anode and the second electrode is a cathode.

Abstract: A method of producing an optoelectronic semiconductor component includes A) providing at least three source substrates, wherein each of the source substrates is equipped with a specific type of radiation-emitting semiconductor chips, B) providing a target substrate having a mounting plane configured to mount the semiconductor chips thereto, C) forming platforms on the target substrate, and D) transferring at least some of the semiconductor chips with a wafer-to-wafer process from the source substrates onto the target substrate so that the semiconductor chips transferred to the target substrate maintain their relative position with respect to one another, within the types of semiconductor chips, wherein on the target substrate the semiconductor chips of each type of semiconductor chips have a specific height above the mounting plane due to the platforms so that the semiconductor chips of different types of semiconductor chips have different heights.

Abstract: A method for fabricating an interposer substrate is provided, including forming a wiring layer on a carrier, forming an insulating layer on the carrier, forming on the wiring layer a wiring build-up layer structure that is electrically connected to the wiring layer, forming on the wiring build-up layer structure external connection pillars that are electrically connected to the wiring build-up layer structure, and removing the carrier, with the wiring layer is exposed from a surface of the insulating layer. The fabrication process of the via can be bypassed in the fabrication process by forming coreless interposer substrate on the carrier, such that the overall cost of the fabrication process can be decreased, and the fabrication process is simple. This invention further provides the interposer substrate.

Abstract: This work develops a novel microfluidic method to fabricate conductive graphene-based 3D micro-electronic circuits on any solid substrate including, Teflon, Delrin, silicon wafer, glass, metal or biodegradable/non-biodegradable polymer-based, 3D microstructured, flexible films. It was demonstrated that this novel method can be universally applied to many different natural or synthetic polymer-based films or any other solid substrates with proper pattern to create graphene-based conductive electronic circuits. This approach also enables fabrication of 3D circuits of flexible electronic films or solid substrates. It is a green process preventing the need for expensive and harsh postprocessing requirements for other fabrication methods such as ink-jet printing or photolithography. We reported that it is possible to fill the pattern channels with different dimensions as low as 10×10 ?m. The graphene nanoplatelet solution with a concentration of 60 mg/mL in 70% ethanol, pre-annealed at 75° C. for 3 h, provided ˜0.

Abstract: The present disclosure relates to a method of forming an interconnect structure. The method can include providing a semiconductor substrate; depositing a photoresist and a BARC layer on the semiconductor substrate; forming an opening in the photoresist and the BARC layer and a portion of the semiconductor substrate; depositing a conductive material to fill the opening; and planarizing the conductive material and the semiconductor substrate.

Abstract: A metal interconnect structure can be fabricated within an integrated circuit (IC). A recess can be created in an IC dielectric layer and a surface modulation liner can be formed by depositing two different metallic elements onto the surfaces of the recess. One metallic element can have a standard electrode potential greater than a standard electrode potential of an interconnect metal, and the other metallic element can have a standard electrode potential less than the standard electrode potential of the interconnect metal. A metal interconnect structure can be formed by filling the remainder of the recess with interconnect metal, which is physically separated from the dielectric layer by the surface modulation liner. The surface topography of the metal interconnect structure can be modulated with a polishing process, by removing a top portion of the interconnect metal and a top portion of the surface modulation liner.