Patents Examined by Zhuo H. Li
  • Patent number: 11182085
    Abstract: Apparatuses and methods for memory array accessibility can include an apparatus with an array of memory cells. The array can include a first portion accessible by a controller of the array and inaccessible to devices external to the apparatus. The array can include a second portion accessible to the devices external to the apparatus. The array can include a number of registers that store row address that indicate which portion of the array is the first portion. The apparatus can include the controller configured to access the number of registers to allow access to the second portion by the devices external to the apparatus based on the stored row addresses.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: November 23, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Daniel B. Penney, Gary L. Howe
  • Patent number: 11163692
    Abstract: Devices and techniques for memory constrained translation table management are disclosed herein. A level of a translation table is logically segmented into multiple segments. Here, a bottom level of the translation table includes a logical to physical address pairing for a portion of a storage device and other levels of the translation table include references within the translation table. The multiple segments are written to the storage device. A first segment of the multiple segments is loaded to byte-addressable memory. A request for an address translation is received and determined to be for an address referred to by a second segment of the multiple segments. The first segment is then replaced with the second segment in the byte-addressable memory and the request is fulfilled using the second segment to locate a lower level of the translation table that includes the address translation.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: November 2, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Sebastien Andre Jean
  • Patent number: 11132141
    Abstract: A system and a method of synchronizing, by a processor, between content of a first data container and content of at least one second data container may include: receiving one or more first data elements of the first data container and one or more second data elements of the at least one second data container; computing one or more first unique reference values (URVs) for the respective one or more first data elements; computing one or more second URVs for the respective one or more second data elements; storing the first data elements on a first storage element; storing the second data elements at a second storage element; comparing between a first URV and a second URV to identify data elements having diverged content; and synchronizing between content of the first data container and content of the at least one second data container based on the comparison.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: September 28, 2021
    Assignee: IONIR SYSTEMS LTD.
    Inventors: Jacob Cherian, Nir Peleg
  • Patent number: 11126374
    Abstract: Technologies for stochastic associative search operations in memory (e.g., a three-dimensional cross-point memory) include a compute device. The compute device has a memory including a matrix that stores individually addressable bit data and is formed by rows and columns. The compute device receives a request to retrieve a subset of the bit data stored in the matrix. The request includes a search key indicative of the subset of bit data, and the search key is formed on a same axis as the rows. The compute device identifies one or more candidate data sets in the matrix based on a search for matching bit data of the search key with bit data in one or more of the columns. The compute device outputs the identified candidate data sets.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: September 21, 2021
    Assignee: Intel Corporation
    Inventors: Jawad B. Khan, Richard Coulson
  • Patent number: 11126551
    Abstract: Systems and methods are described, and an example system includes logic that implements a user interface and that accepts an indicator of data, and upon identifying the data is restricted access, receives via the interface attributes of tasks, and of the user, and determines a task-user attribute matrix based on the user input. The logic sends a data-coefficient request to access modules, receives a reply message that includes sensitivity metadata coefficient, a privacy metadata coefficient, a combinability metadata coefficient, and a security metadata coefficient. The logic constructs, using a content of the reply message, a metadata coefficient matrix. The logic applies a dynamic access evaluation that is based on the task-user attribute matrix and the metadata coefficient matrix and, upon a positive evaluation, accesses the restricted-access data and provides the accessed data to a data cache. Optionally, the data cache feeds a system of system operational analytics.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: September 21, 2021
    Assignee: The Government of the United States of America, as represented by the Secretary of Homeland Security
    Inventors: John L. Dargan, Damian Garcia, Archie Turner, Carlos M. Lizardi, Lorraine Castillo
  • Patent number: 11119912
    Abstract: A computer-implemented method according to one embodiment includes receiving, by a target system from a source system, a description of a set of data updates that are to be written to the target system. For each given portion of data of the target system that is to be rewritten during performance of the set of data updates, forward lookup is performed on the target system for determining a physical storage address of the given portion of data. The method further includes marking each of the determined physical storage addresses of the portions of data of the target system in a copy of a reverse lookup table of the target system. The marked-up reverse lookup table is used for determining an ordering in which the performance of the set of data updates would result in a least amount of garbage collection being performed while performing the set of data updates.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: September 14, 2021
    Assignee: International Business Machines Corporation
    Inventors: Miles Mulholland, Gordon D. Hutchison, Ben Sasson, Lee J. Sanders
  • Patent number: 11099750
    Abstract: A computing system including: a host interface configured to parse a command packet from a command address medium; and a command block, coupled to the host interface, configured to: assemble a command from the command packet.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: August 24, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chaohong Hu, Liang Yin, Hongzhong Zheng
  • Patent number: 11061817
    Abstract: Data memory node (400) for ESM (Emulated Share Memory) architectures (100, 200), comprising a data memory module (402) containing data memory for storing input data therein and retrieving stored data therefrom responsive to predetermined control signals, a multi-port cache (404) for the data memory, said cache being provided with at least one read port (404A, 404B) and at least one write port (404C, 404D, 404E), said cache (404) being configured to hold recently and/or frequently used data stored in the data memory (402), and an active memory unit (406) at least functionally connected to a plurality of processors via an interconnection network (108), said active memory unit (406) being configured to operate the cache (404) upon receiving a multioperation reference (410) incorporating a memory reference to the data memory of the data memory module from a number of processors of said plurality, wherein responsive to the receipt of the multioperation reference the active memory unit (406) is configured to proces
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: July 13, 2021
    Assignee: Teknologian tutkimuskeskus VTT Oy
    Inventor: Martti Forsell
  • Patent number: 11055005
    Abstract: Techniques are provided for background deduplication using trusted fingerprints. Trusted fingerprints of blocks are inserted into a trusted fingerprint store as the blocks are being allocated by a file system sequentially according to block numbers of the blocks. In this way, the trusted fingerprint store is indexed by block numbers of where the blocks are stored. Blocks that are to be deduplicated are identifying by sorting the blocks based upon weak fingerprints, and moving duplicates to a dup file. The dup file is sorted based upon block numbers. Trusted fingerprints are loaded from the trusted fingerprint store for deduplicating the blocks within the dup file.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: July 6, 2021
    Assignee: NetApp, Inc.
    Inventors: Dnyaneshwar Nagorao Pawar, Kartik Rathnakar
  • Patent number: 11048641
    Abstract: Provided are a computer program product, system, and method for managing cache segments between a global queue and a plurality of local queues using a machine learning module. Cache segment management information related to management of segments in the local queues and accesses to the global queue to transfer cache segments between the local queues and the global queue, are provided to a machine learning module to output an optimum number parameter comprising an optimum number of segments to maintain in a local queue and a transfer number parameter comprising a number of cache segments to transfer between a local queue and the global queue. The optimum number parameter and the transfer number parameter are sent to a processing unit having a local queue to cause the processing unit to transfer the transfer number parameter of cache segments between the local queue to the global queue.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: June 29, 2021
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Kevin J. Ash, Beth A. Peterson, Matthew R. Craig
  • Patent number: 11036430
    Abstract: Computer software that adjusts a performance capability of a storage volume by (i) determining a current storage volume to store data having a workload pattern, wherein a cycle of the workload pattern includes a hot period and a cold period, (ii) determining a time limit window of the current storage volume, wherein the time limit window is a shortest time window within which performance capability of the current storage volume is to be kept without adjustment, (iii) determining a low performance period of the current storage volume corresponding to the cold period, and (iv) in response to the low performance period being greater than or equal to the time limit window, reducing the performance capability of the current storage volume during the low performance period.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: June 15, 2021
    Assignee: International Business Machines Corporation
    Inventors: Long Wen Lan, Yang Liu, Duo Chen
  • Patent number: 11029879
    Abstract: A method of page size aware scheduling and a non-transitory computer-readable storage medium having recorded thereon a computer program for executing the method of page size aware scheduling are provided. The method includes determining a size of a media page; determining if the media page is open or closed; performing, by a memory controller, a speculative read operation if the media page is determined to be open; and performing, by the memory controller, a regular read operation if the media page is determined to be closed.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: June 8, 2021
    Inventors: Dimin Niu, Mu Tien Chang, Hongzhong Zheng, Sun Young Lim, Jae-Gon Lee, Indong Kim
  • Patent number: 11016907
    Abstract: Increasing the scope of local purges of structures associated with address translation. A hardware thread of a physical core of a machine configuration issues a purge request. A determination is made as to whether the purge request is a local request. Based on the purge request being a local request, entries of a structure associated with address translation are purged on at least multiple hardware threads of a set of hardware threads of the machine configuration.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: May 25, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jonathan D. Bradbury, Fadi Y. Busaba, Lisa Cranton Heller
  • Patent number: 11016888
    Abstract: A method for compressing data in a local cache of a web server is described. A local cache compression engine accesses values in the local cache and determines a cardinality of the values of the local cache. The local cache compression engine determines a compression rate of a compression algorithm based on the cardinality of the values of the local cache. The compression algorithm is applied to the cache based on the compression rate to generate a compressed local cache.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: May 25, 2021
    Assignee: eBay Inc.
    Inventor: Amit Desai
  • Patent number: 11010056
    Abstract: A data operating method, device, and system are provided and relate to the computer field, so as to resolve a prior-art problem of low efficiency of performing a data operation on a block device by a CPU. The method includes: receiving an operation instruction sent by a CPU; when the operation instruction is a read instruction, reading a first data block in the block device and returning to-be-read data in the first data block to the CPU; or when the operation instruction is a write instruction, writing, into a cache, to-be-written data indicated by the write instruction, and writing, into the block device, a second data block that includes the to-be-written data. The method is used to operate data in a block device.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: May 18, 2021
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Fei Xia, Mingyu Chen, Dejun Jiang, Jin Xiong
  • Patent number: 10996899
    Abstract: Disclosed herein is a computer storage array providing one or more remote initiators with NVMe over Fabrics (NVMe-oF) access to one or more storage devices connected to the storage array. According to an example embodiment, the computer storage array comprises: a computer processor configured to run an operating system for managing networking protocols; a network switch configured to establish an NVMe-oF connection and route data between the initiators and the storage devices; a baseboard management controller (BMC) configured to configure a network setting or NVMe-oF setting of the storage devices; a PCIe switch connecting the BMC with each of the storage devices via a PCIe bus; and a computer motherboard including the PCIe bus and to which the computer processor, network switch, BMC and PCIe switch are installed.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: May 4, 2021
    Inventors: Sompong Paul Olarig, Son T. Pham, Ramdas Kachare
  • Patent number: 10977179
    Abstract: A method and apparatus for cache management and eviction polices using unsupervised reinforcement learning schemes is disclosed.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: April 13, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Opher Lieber, Ariel Navon, Alexander Bazarsky, Shay Benisty
  • Patent number: 10936211
    Abstract: There is described a method, data processing apparatus and computer program product for initializing storage protection, the storage protection for enforcing access permission for a region of storage configured in a layout of regions according to at least one security constraint, the method comprising: receiving a set of storage requirements; generating a layout whereby the layout comprises a combination of storage regions that accommodate the storage requirements within the at least one security constraint; and configuring the storage protection according to the generated layout, wherein generating a layout comprises: calculating, for each storage requirement, a list of all storage regions that could accommodate the storage requirement within the at least one security constraint; selecting and testing combinations of storage regions until a selected combination accommodates the storage requirements within the at least one security constraint; and providing the accommodated combination of storage regions as a
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: March 2, 2021
    Assignee: ARM IP LTD
    Inventors: Alessandro Angelino, Milosch Meriac, Niklas Lennart Hauser
  • Patent number: 10929298
    Abstract: A processor of an aspect includes a plurality of packed data registers, and a decode unit to decode a no-locality hint vector memory access instruction. The no-locality hint vector memory access instruction to indicate a packed data register of the plurality of packed data registers that is to have a source packed memory indices. The source packed memory indices to have a plurality of memory indices. The no-locality hint vector memory access instruction is to provide a no-locality hint to the processor for data elements that are to be accessed with the memory indices. The processor also includes an execution unit coupled with the decode unit and the plurality of packed data registers. The execution unit, in response to the no-locality hint vector memory access instruction, is to access the data elements at memory locations that are based on the memory indices.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: February 23, 2021
    Assignee: Intel Corporation
    Inventor: Christopher J. Hughes
  • Patent number: 10929043
    Abstract: Techniques are described for reserving space on a destination node or volume for increasing the likelihood of a successful data transfer in a distributed storage environment. A reservation may be retried at one or more destinations if the reservation fails at a first destination. In some embodiments, the data-transfer process can be paused or terminated prior to data being transferred to one or more destinations if a reservation fails. Reserving space on a destination node or volume can increase the likelihood of a successful data transfer, which can increase the likelihood of efficient resources usage in a storage system.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: February 23, 2021
    Assignee: NETAPP, INC.
    Inventors: Tymoteusz Altman, Yi Zhang, Dheeraj Raghavender Sangamkar, Emalayan Vairavanathan