Patents Examined by Zhuo H. Li
  • Patent number: 12008236
    Abstract: A device includes a first memory die and a second memory die directly coupled to the first memory die via a first bus. The device also includes a second bus directly coupled to the first memory die. The first memory die includes a first trim circuit that when in operation adjusts a delay of signal transmission by the first memory die to a first value, while the second memory die comprises a second trim circuit that when in operation adjusts a delay of signal transmission by the second memory die to a second value.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: June 11, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Hari Giduturi, Bret Addison Johnson
  • Patent number: 12008261
    Abstract: A memory access method and device are provided. A memory access method may include: identifying, when an access to a page of a remote memory occurs, a type of the access; allocating a sparse buffer when the access is a sparse write; storing data for the sparse write in the sparse buffer; storing an address for the sparse write as a key and the sparse buffer as a value in a buffer table; and updating an instruction pointer to point to a next instruction.
    Type: Grant
    Filed: May 10, 2022
    Date of Patent: June 11, 2024
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Kwang-Won Koh, Kang Ho Kim, Changdae Kim, Taehoon Kim
  • Patent number: 12007944
    Abstract: With a forever incremental snapshot configuration and a typical caching policy (e.g., least recently used), a storage appliance may evict stable data blocks of an older snapshot, perhaps unchanged data blocks of the snapshot baseline. If stable data blocks have been evicted, restore of a recent snapshot will suffer the time penalty of downloading the stable blocks for restoring the recent snapshot. Creating synthetic baseline snapshots and refreshing eviction data of stable data blocks can avoid eviction of stable data blocks and reduce the risk of violating a recovery time objective.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: June 11, 2024
    Assignee: NetApp, Inc.
    Inventors: Ajay Pratap Singh Kushwah, Ling Zheng, Sharad Jain
  • Patent number: 12001720
    Abstract: A method and apparatus for operating a solid state drive is disclosed comprising receiving at least two commands from a host requiring an action by the solid state drive in a preliminary order, ordering the at least two commands based upon a quality of service classification for the at least two commands to a final order and executing the at least two commands on the solid state drive in the final order, wherein an operational parameter of the solid state drive is modified by at least one of the at least two commands.
    Type: Grant
    Filed: July 8, 2022
    Date of Patent: June 4, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventor: Shay Benisty
  • Patent number: 12001706
    Abstract: Provided is a computing system including a memory system in communication with a host, to store data therein. The memory system includes a memory having a plurality of memory components coupled to the controller via a memory interface; and a memory controller configured to communicate with the memory to control data transmission and performing scrubbing operation of the memory components and detecting a region of the memory to be sanitized and performing a sanitization operation of the detected region to prevent the occurrence of failure.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: June 4, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Marco Sforzin, Angelo Visconti, Giorgio Servalli, Daniele Balluchi, Paolo Amato
  • Patent number: 12001331
    Abstract: A data storage device may include a storage including a plurality of memory blocks composed of system memory blocks for storing system data and user memory blocks for storing user data; and a controller configured to: control exchange of the system and user data with the storage in response to a request of a host device; and determine whether a start condition for performing a garbage collection operation on the storage is satisfied, based on a number of bad memory blocks in the plurality of memory blocks.
    Type: Grant
    Filed: April 26, 2023
    Date of Patent: June 4, 2024
    Assignee: SK hynix Inc.
    Inventor: Gun Wook Lee
  • Patent number: 11983441
    Abstract: An integrated circuit includes a front-end interface, a back-end interface, a controller, and arbiter circuitry. The front-end interface communicates with a remote host over a front-end fabric. The back-end interface communicates with nonvolatile memory (NVM) subsystems over a back-end fabric. The controller is coupled between the front-end interface and the back-end interface. The controller receives commands from the remote host for the NVM subsystems, and stores the commands in queue pairs associated with the NVM subsystems. The arbiter circuitry receives data for the queue pairs, and selects a command from a first queue pair of the queue pairs based on a comparison of the data to one or more thresholds. The selected command is outputted to one or more of the NVM subsystems.
    Type: Grant
    Filed: March 24, 2022
    Date of Patent: May 14, 2024
    Assignee: XILINX, INC.
    Inventors: Ramesh Ramaiya Subramanian, Chaitanya Kallakuri
  • Patent number: 11966361
    Abstract: With a forever incremental snapshot configuration and a typical caching policy (e.g., least recently used), a storage appliance may evict stable data blocks of an older snapshot, perhaps unchanged data blocks of the snapshot baseline. If stable data blocks have been evicted, restore of a recent snapshot will suffer the time penalty of downloading the stable blocks for restoring the recent snapshot. Creating synthetic baseline snapshots and refreshing eviction data of stable data blocks can avoid eviction of stable data blocks and reduce the risk of violating a recovery time objective.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: April 23, 2024
    Assignee: NetApp, Inc.
    Inventors: Ajay Pratap Singh Kushwah, Ling Zheng, Sharad Jain
  • Patent number: 11954047
    Abstract: Systems, methods, and apparatuses to implement spatially unique and location independent persistent memory encryption are described. In one embodiment, a system on a chip (SoC) includes at least one persistent range register to indicate a persistent range of memory, an address modifying circuit to check if an address for a memory store request is within the persistent range indicated by the at least one persistent range register, and append a unique identifier value, for a component corresponding to the memory store request for the address, to the address to generate a modified address and output the modified address as an output address when the address is within the persistent range, and output the address as the output address when the address is not within the persistent range, and an encryption engine circuit to generate a ciphertext based on the output address.
    Type: Grant
    Filed: September 26, 2020
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Mahesh Natu, Anand K. Enamandram, Manjula Peddireddy, Robert A. Branch, Tiffany J. Kasanicky, Siddhartha Chhabra, Hormuzd Khosravi
  • Patent number: 11947821
    Abstract: The present disclosure provides methods, systems, and non-transitory computer readable media for managing a primary storage unit of an accelerator. The methods include assessing activity of the accelerator; assigning, based on the assessed activity of the accelerator, a lease to a group of one or more pages of data on the primary storage unit, wherein the assigned lease indicates a lease duration; and marking, in response to the expiration of the lease duration indicated by the lease, the group of one or more pages of data as an eviction candidate.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: April 2, 2024
    Assignee: Alibaba Group Holding Limited
    Inventors: Yongbin Gu, Pengcheng Li, Tao Zhang, Yuan Xie
  • Patent number: 11941259
    Abstract: A communication method applied to a computer system that includes a first subsystem and a second subsystem. A safety level of the first subsystem is higher than a safety level of the second subsystem. The first subsystem includes a memory access checker. The method includes the memory access checker receives a memory access request from a memory access initiator, determines, based on preconfigured memory safety level division information, whether a safety level of a memory to be accessed by the memory access initiator matches a safety level of the memory access initiator, and allows the memory access initiator to access the memory address when the safety level of the memory matches the safety level of the memory access initiator.
    Type: Grant
    Filed: July 7, 2021
    Date of Patent: March 26, 2024
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Dongjiu Geng, Chuanlong Yang, Yan Sang, Qiangmin Lin
  • Patent number: 11922032
    Abstract: A content addressable memory circuit is provided that includes: multiple integrated circuit memory devices that include memory address locations that share common memory addresses; buffer circuits operatively coupled to the memory devices; a hash table that includes a plurality of hash values that each corresponds to one or more key values; one or more processor circuits configured with instructions to perform operations that include: assigning each hash value to a memory address location based upon a first portion of the hash value; storing each key value at a memory address location assigned to a first portion of a hash value that corresponds to the key value; copying a first key value from a first memory address location within a memory device to a buffer circuit operatively coupled to the memory device; copying the first key value from the buffer circuit operatively coupled to the memory device to a second memory address location of the memory device; and assigning a second portion of a hash value that co
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: March 5, 2024
    Assignee: DreamBig Semiconductor Inc.
    Inventors: Sohail A Syed, Hillel Gazit, Hon Luu, Pranab Ghosh
  • Patent number: 11914905
    Abstract: Examples describe memory refresh operations for memory subsystems. One example is a method for a memory controller, the method including entering a first state upon exiting self-refresh state, wherein the first state comprises activating a first timer. The method includes entering a second state from the first state upon detecting an end of an active period and detecting that the first timer has not expired. The method includes entering a third state from the second state upon detecting expiration of the second state, wherein the third state comprises re-entering the self-refresh state.
    Type: Grant
    Filed: July 15, 2021
    Date of Patent: February 27, 2024
    Assignee: XILINX, INC.
    Inventor: Martin Newman
  • Patent number: 11907555
    Abstract: Described are memory modules that include address-buffer components and data-buffer components that together support wide- and narrow-data modes. The address-buffer component manages communication between a memory controller and two sets of memory components. In the wide-data mode, the address-buffer enables memory components in each set and instructs the data-buffer components to communicate full-width read and write data by combining data from or to from both sets for each memory access. In the narrow-data mode, the address-buffer enables memory components in just one of the two sets and instructs the data-buffer components to half-width read and write data with one set per memory access.
    Type: Grant
    Filed: November 18, 2022
    Date of Patent: February 20, 2024
    Assignee: Rambus Inc.
    Inventors: Suresh Rajan, Abhijit M. Abhyankar, Ravindranath Kollipara, David A. Secker
  • Patent number: 11907121
    Abstract: A method for caching content, a method for reading content, a client, and a storage medium are provided. The method for caching content includes: acquiring JSON data corresponding to content to be delivered, and determining identification information corresponding to the JSON data; grouping the JSON data and storing the grouped JSON data according to the identification information to obtain a memory list corresponding to the identification information, and writing the JSON data to a target disk according to the identification information and the memory list; performing video preloading processing on the content to be delivered according to the JSON data to obtain preloaded video data, and determining address information corresponding to the preloaded video data; and storing the address information in the memory list and the target disk according to the identification information, to complete caching of the JSON data and the preloaded video data.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: February 20, 2024
    Assignee: BEIJING BYTEDANCE NETWORK TECHNOLOGY CO., LTD.
    Inventors: Weiqin Lian, You Tu
  • Patent number: 11899595
    Abstract: Systems and methods for providing object versioning in a storage system may support the logical deletion of stored objects. In response to a delete operation specifying both a user key and a version identifier, the storage system may permanently delete the specified version of an object having the specified key. In response to a delete operation specifying a user key, but not a version identifier, the storage system may create a delete marker object that does not contain object data, and may generate a new version identifier for the delete marker. The delete marker may be stored as the latest object version of the user key, and may be addressable in the storage system using a composite key comprising the user key and the new version identifier. Subsequent attempts to retrieve the user key without specifying a version identifier may return an error, although the object was not actually deleted.
    Type: Grant
    Filed: September 2, 2022
    Date of Patent: February 13, 2024
    Assignee: Amazon Technologies, Inc.
    Inventors: Jason G. McHugh, Praveen Kumar Gattu, Michael A. Ten-Pow, Derek Ernest Denny-Brown, II
  • Patent number: 11899940
    Abstract: When load requests are generated to support data processing operations, the load requests are buffered in pending load buffer circuitry prior to being carried out. Coalescing circuitry determines for a first load request whether a set of one or more subsequent load requests buffered in the pending load buffer circuitry satisfies an address proximity condition. The address proximity condition is satisfied when all data items identified by the set of one or more subsequent load requests are comprised within a series of data items which will be retrieved from the memory system in response to the first load request. When the address proximity condition is satisfied, forwarding of the set of one or more subsequent load requests is suppressed.
    Type: Grant
    Filed: October 7, 2020
    Date of Patent: February 13, 2024
    Assignee: Arm Limited
    Inventors: Mbou Eyole, Stefanos Kaxiras
  • Patent number: 11893242
    Abstract: Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a multi-chip module (MCM) is disclosed. The MCM includes a common substrate and a first integrated circuit (IC) chip disposed on the common substrate. The first IC chip includes a first memory interface. A second IC chip is disposed on the common substrate and includes a second memory interface. A first memory device is disposed on the common substrate and includes memory and a first port coupled to the memory. The first port is configured for communicating with the first memory interface of the first IC chip. A second port is coupled to the memory and communicates with the second memory interface of the second IC chip. In-memory processing circuitry is coupled to the memory and controls transactions between the first memory device and the first and second IC chips.
    Type: Grant
    Filed: November 25, 2022
    Date of Patent: February 6, 2024
    Assignee: Eliyan Corporation
    Inventors: Ramin Farjadrad, Syrus Ziai
  • Patent number: 11892952
    Abstract: A processor of an aspect includes a plurality of packed data registers, and a decode unit to decode a no-locality hint vector memory access instruction. The no-locality hint vector memory access instruction to indicate a packed data register of the plurality of packed data registers that is to have a source packed memory indices. The source packed memory indices to have a plurality of memory indices. The no-locality hint vector memory access instruction is to provide a no-locality hint to the processor for data elements that are to be accessed with the memory indices. The processor also includes an execution unit coupled with the decode unit and the plurality of packed data registers. The execution unit, in response to the no-locality hint vector memory access instruction, is to access the data elements at memory locations that are based on the memory indices.
    Type: Grant
    Filed: July 18, 2022
    Date of Patent: February 6, 2024
    Assignee: Intel Corporation
    Inventor: Christopher J. Hughes
  • Patent number: 11886715
    Abstract: Apparatuses and methods for memory array accessibility can include an apparatus with an array of memory cells. The array can include a first portion accessible by a controller of the array and inaccessible to devices external to the apparatus. The array can include a second portion accessible to the devices external to the apparatus. The array can include a number of registers that store row address that indicate which portion of the array is the first portion. The apparatus can include the controller configured to access the number of registers to allow access to the second portion by the devices external to the apparatus based on the stored row addresses.
    Type: Grant
    Filed: November 19, 2021
    Date of Patent: January 30, 2024
    Inventors: Daniel B. Penney, GAry L. Howe