Abstract: Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a multi-chip module (MCM) is disclosed. The MCM includes a common substrate and a first integrated circuit (IC) chip disposed on the common substrate. The first IC chip includes a first memory interface. A second IC chip is disposed on the common substrate and includes a second memory interface. A first memory device is disposed on the common substrate and includes memory and a first port coupled to the memory. The first port is configured for communicating with the first memory interface of the first IC chip. A second port is coupled to the memory and communicates with the second memory interface of the second IC chip. In-memory processing circuitry is coupled to the memory and controls transactions between the first memory device and the first and second IC chips.

Abstract: Methods, systems, and devices for capability messaging for memory operations across banks with multiple page access are described. Techniques are described for a memory system to use a same bank for first and second access operations of data associated with an access command. The data corresponding to the second access operation may be communicated after the data corresponding to the first access operation on the same data channels. Techniques are further described for including one or more additional access commands with the access command that use other banks. Techniques are further described for interleaving data sets communicated as a result of the access commands and for abutting data sets based on parameters obtained by the memory device. Techniques are further described for the generation and performance of internal access commands in accordance with a data transfer type indicated by a host system.

Abstract: Disclosed Methods, Apparatus, and articles of manufacture to profile page tables for memory management are disclosed. An example apparatus includes a processor to execute computer readable instructions to: profile a first page at a first level of a page table as not part of a target group; and in response to profiling the first page as not part of the target group, label a data page at a second level that corresponds to the first page as not part of the target group, the second level being lower than the first level.

Abstract: A solid state drive management solution is provided, and includes: detecting that a usage status of a first storage space of an SSD meets a preset condition, where the first storage space works in a first mode; and enabling, based on the detection result, the first storage space to work in a second mode to obtain a second storage space, where a quantity of bits that can be stored in a cell in the first storage space is greater than a quantity of bits that can be stored in a cell in the second storage space.

Abstract: Provided is a method for cleaning residual paths on a host end, including: acquiring device information of subordinate devices of a plurality of paths; determining, according to the device information, whether links corresponding to the subordinate devices are all abnormal; acquiring a global identification number and connection information of each subordinate device in a case that the links corresponding to the subordinate devices are all abnormal; when the global identification number is not null and the connection information is successfully acquired, querying a mapping state of a volume corresponding to the global identification number and a mapped host according to the global identification number and the connection information; and when the volume is not in the mapping state or the mapped host is not a target host, deleting the plurality of paths and the subordinate devices.

Abstract: Mechanisms for controlling background wear leveling are provided, including: increasing a first counter; comparing the first counter to a first threshold; and in response to the first counter meeting the first threshold: decreasing the first counter by a value of the first threshold; and triggering background wear leveling. In some embodiments, the first counter is increased in response to receiving a write trigger. In some embodiments, the first threshold is based upon a page size and a number of planes of physical media of an SSD. In some embodiments, the mechanisms further comprise: incrementing a second counter in response to receiving a host write trigger; comparing the second counter to a second threshold; and in response to the second counter meeting the second threshold, decreasing the second counter by the second threshold, wherein the increasing the first counter is performed in response to the second counter meeting the second threshold.

Abstract: Disclosed embodiments relate to atomic memory operations. In one example, an apparatus includes multiple processor cores, a cache hierarchy, a local execution unit, and a remote execution unit, and an adaptive remote atomic operation unit. The cache hierarchy includes a local cache at a first level and a shared cache at a second level. The local execution unit is to perform an atomic operation at the first level if the local cache is a storing a cache line including data for the atomic operation. The remote execution unit is to perform the atomic operation at the second level. The adaptive remote atomic operation unit is to determine whether to perform the first atomic operation at the first level or at the second level and whether to copy the cache line from the shared cache to the local cache.

Abstract: A memory is described. The memory includes row buffer circuitry to store a page. The page is divided into sections, wherein, at least one of the sections of the page is to be sequestered for the storage of meta data, and wherein, a first subset of column address bits is to: 1) define a particular section of the page, other than the at least one sequestered sections of the page, whose data is targeted by a burst access; and, 2) define a field within the at least one of the sequestered sections of the page that stores meta data for the particular section.

Abstract: Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a multi-chip module (MCM) is disclosed. The MCM includes a common substrate and a first integrated circuit (IC) chip disposed on the common substrate. The first IC chip includes a first memory interface. A second IC chip is disposed on the common substrate and includes a second memory interface. A first memory device is disposed on the common substrate and includes memory and a first port coupled to the memory. The first port is configured for communicating with the first memory interface of the first IC chip. A second port is coupled to the memory and communicates with the second memory interface of the second IC chip. In-memory processing circuitry is coupled to the memory and controls transactions between the first memory device and the first and second IC chips.

Abstract: Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a logic base die for inclusion in a chiplet-based multi-chip module (MCM) is disclosed. The logic base die includes a first port interface for coupling to an interface beachfront of a first integrated circuit (IC) chiplet. The first port interface is to receive data of a first bandwidth via the interface beachfront via a first set of traces formed in a micro-bump advanced-package routing layer. A memory port provides a first portion of the first bandwidth to at least a first memory stack configured for positioning on the logic base die. A second port interface couples to the first port interface and utilizes a second portion of the first bandwidth.

Abstract: Embodiments of systems and methods for a Compression Attached Memory Module (CAMM) for Low-Power Double Data Rate (LPDDR) memories are described. In an illustrative, non-limiting embodiment, an Information Handling System (IHS) may include: a compression Dual In-Line Memory Module (cDIMM) connector coupled to a motherboard; and a memory module coupled to the cDIMM connector, where the memory module comprises an LPDDR device coupled to a top surface of the memory module and accessible via surface contact connections disposed on a bottom surface of the memory module.

Abstract: Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a multi-chip module (MCM) is disclosed. The MCM includes a package substrate and an interposer disposed on a portion of the package substrate. A first integrated circuit (IC) chip is disposed on the interposer. A first memory device is disposed on the interposer and includes a first port interface including an interposer-compliant mechanical interface for coupling to the first IC chip via a first set of traces formed in the interposer. A second port interface includes a non-interposer-compliant mechanical interface for coupling to an off-interposer device. Transactions between the first IC chip and the off-interposer device pass through the first port interface and the second port interface of the first memory device.

Abstract: In one implementation a vector processor gather/scatter apparatus comprises a plurality of vector ports, and a random access memory, where the plurality of vector ports are in communication with the random access memory, and where one or more of the plurality of vector ports uses one or more of an address register and one or more of a stride register in communication with the random access memory to allow the gather/scatter of random access memory contents.

Abstract: Disclosed are various approaches for decreasing the latency involved in reading pages from swap devices. These approaches can include setting a first queue in the plurality of queues as a highest priority queue and a second queue in the plurality of queues as a low priority queue. Then, an input/output (I/O) request for an address in memory can be received. The type of the I/O request can be determined, and then the I/O request can be assigned to the first queue or the second queue of the swap device based at least in part on the type of the I/O request.

Abstract: The present disclosure includes apparatuses and methods for performing operations by a memory device in a self-refresh state. An example includes an array of memory cells and a controller coupled to the array of memory cells. The controller is configured to direct performance of compute operations on data stored in the array when the array is in a self-refresh state.

Abstract: In embodiments, a system includes a first and a second processing unit, a memory, and a firewall device. The first processing unit operates in a secure mode and generates memory access requests having a secure level. The second processing unit operates in a non-secure mode and generates memory access requests having a non-secure level. The memory includes a first memory area that can be shared between the first and second processing units. The firewall device includes a first firewall circuit with a first configuration authorizing access to the first memory area in the presence of a secure or non-secure level access request. The firewall circuit includes a second configuration prohibiting access to the first memory area in the presence of a secure level access request and authorizing access to the first memory area only in the presence of a non-secure level access request.

Abstract: An electronic device includes a display; a memory configured to store at least one instruction corresponding to at least one program; and a processor configured to execute the at least one instruction as a process, wherein the processor is configured to: predict, in response to a foreground execution of a first process, an amount of an available memory at a time point after an elapse of a predetermined time from the foreground execution of the first process, based on memory usage information stored in the memory; based on the predicted amount of the available memory exceeding a predetermined threshold value, suspend a memory return operation for the predetermined time; and based on the predicted amount of the available memory being less than the predetermined threshold value, perform the memory return operation without suspending the memory return operation.

Abstract: Examples of the present disclosure relate to an apparatus comprising interface circuitry to receive memory access commands directed to a memory device, each memory access command specifying a memory address to be accessed. The apparatus comprises scheduler circuitry to store a representation of a plurality of states accessible to the memory device and, based on the representation, determine an order for the received memory access commands. The apparatus comprises dispatch circuitry to receive the received memory access commands from the scheduler circuitry and issue the received memory access commands, in the determined order, to be performed by the memory device.

Abstract: The disclosed technology relates to an electronic device. According to the disclosed technology, a memory controller for a storage device for storing data in connection with a host in communication with the storage device includes a recommendation signal manager configured to store a plurality of recommendation signals that recommends activating a memory area of the host that stores mapping information in the memory area of the host, and a host controller configured to provide at least one of the plurality of recommendation signals to the host according to whether a number of recommendation signals provided to the host is less than a threshold value.

Abstract: A processing-in-memory (PIM) system includes a PIM device and a controller. The PIM device includes a data storage region and an arithmetic circuit for performing an arithmetic operation for data outputted from the data storage region. The controller is configured to control the PIM device. The PIM device is configured to transmit arithmetic quantity data of the arithmetic circuit to the controller in response to a request of the controller.