Abstract: Embodiments of systems and methods for a Compression Attached Memory Module (CAMM) for Low-Power Double Data Rate (LPDDR) memories are described. In an illustrative, non-limiting embodiment, an Information Handling System (IHS) may include: a compression Dual In-Line Memory Module (cDIMM) connector coupled to a motherboard; and a memory module coupled to the cDIMM connector, where the memory module comprises an LPDDR device coupled to a top surface of the memory module and accessible via surface contact connections disposed on a bottom surface of the memory module.

Abstract: Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a multi-chip module (MCM) is disclosed. The MCM includes a package substrate and an interposer disposed on a portion of the package substrate. A first integrated circuit (IC) chip is disposed on the interposer. A first memory device is disposed on the interposer and includes a first port interface including an interposer-compliant mechanical interface for coupling to the first IC chip via a first set of traces formed in the interposer. A second port interface includes a non-interposer-compliant mechanical interface for coupling to an off-interposer device. Transactions between the first IC chip and the off-interposer device pass through the first port interface and the second port interface of the first memory device.

Abstract: In one implementation a vector processor gather/scatter apparatus comprises a plurality of vector ports, and a random access memory, where the plurality of vector ports are in communication with the random access memory, and where one or more of the plurality of vector ports uses one or more of an address register and one or more of a stride register in communication with the random access memory to allow the gather/scatter of random access memory contents.

Abstract: Disclosed are various approaches for decreasing the latency involved in reading pages from swap devices. These approaches can include setting a first queue in the plurality of queues as a highest priority queue and a second queue in the plurality of queues as a low priority queue. Then, an input/output (I/O) request for an address in memory can be received. The type of the I/O request can be determined, and then the I/O request can be assigned to the first queue or the second queue of the swap device based at least in part on the type of the I/O request.

Abstract: The present disclosure includes apparatuses and methods for performing operations by a memory device in a self-refresh state. An example includes an array of memory cells and a controller coupled to the array of memory cells. The controller is configured to direct performance of compute operations on data stored in the array when the array is in a self-refresh state.

Abstract: An electronic device includes a display; a memory configured to store at least one instruction corresponding to at least one program; and a processor configured to execute the at least one instruction as a process, wherein the processor is configured to: predict, in response to a foreground execution of a first process, an amount of an available memory at a time point after an elapse of a predetermined time from the foreground execution of the first process, based on memory usage information stored in the memory; based on the predicted amount of the available memory exceeding a predetermined threshold value, suspend a memory return operation for the predetermined time; and based on the predicted amount of the available memory being less than the predetermined threshold value, perform the memory return operation without suspending the memory return operation.

Abstract: In embodiments, a system includes a first and a second processing unit, a memory, and a firewall device. The first processing unit operates in a secure mode and generates memory access requests having a secure level. The second processing unit operates in a non-secure mode and generates memory access requests having a non-secure level. The memory includes a first memory area that can be shared between the first and second processing units. The firewall device includes a first firewall circuit with a first configuration authorizing access to the first memory area in the presence of a secure or non-secure level access request. The firewall circuit includes a second configuration prohibiting access to the first memory area in the presence of a secure level access request and authorizing access to the first memory area only in the presence of a non-secure level access request.

Abstract: Examples of the present disclosure relate to an apparatus comprising interface circuitry to receive memory access commands directed to a memory device, each memory access command specifying a memory address to be accessed. The apparatus comprises scheduler circuitry to store a representation of a plurality of states accessible to the memory device and, based on the representation, determine an order for the received memory access commands. The apparatus comprises dispatch circuitry to receive the received memory access commands from the scheduler circuitry and issue the received memory access commands, in the determined order, to be performed by the memory device.

Abstract: The disclosed technology relates to an electronic device. According to the disclosed technology, a memory controller for a storage device for storing data in connection with a host in communication with the storage device includes a recommendation signal manager configured to store a plurality of recommendation signals that recommends activating a memory area of the host that stores mapping information in the memory area of the host, and a host controller configured to provide at least one of the plurality of recommendation signals to the host according to whether a number of recommendation signals provided to the host is less than a threshold value.

Abstract: A processing-in-memory (PIM) system includes a PIM device and a controller. The PIM device includes a data storage region and an arithmetic circuit for performing an arithmetic operation for data outputted from the data storage region. The controller is configured to control the PIM device. The PIM device is configured to transmit arithmetic quantity data of the arithmetic circuit to the controller in response to a request of the controller.

Abstract: A memory device includes an interface to communicate with a host, an array of memory cells, and a controller. The controller is configured to access the array of memory cells in response to commands from the host. The controller is further configured to enter an idle time in response to no commands from the host with queue empty, receive a first command from the host, and exit the idle time in response receiving a second command from the host. The controller is further configured to for a plurality of idle times, generate a history indicating a length of each idle time. The controller is further configured to predict the length of a subsequent idle time based on the history.

Abstract: An apparatus includes a graphics processing unit (GPU) and a frame buffer. The frame buffer is coupled to the GPU. Based upon initialization of a virtual function, a plurality of pages are mapped into a virtual frame buffer. The plurality of pages are mapped into the virtual frame buffer by using a graphics input/output memory management unit (GIOMMU) and an associated page table.

Abstract: A transform memory controller is described herein wherein the transform memory controller comprises logic elements configured to perform desired transform operations on data that flows to-and-from conventional computer memory elements. The transform operations are configured to perform operations on such data without the need for such data to travel to-and-from the conventional computer memory element via the processor (e.g., Central Processing Unit (CPU)) of the computer system. Several desirable transform operations are herein disclosed.

Abstract: Methods and systems are disclosed for frequency transitioning in a memory interface system. Techniques disclosed include receiving a signal indicative of a change in operating frequency, into a new frequency, in a processing unit interfacing with memory via the memory interface system; switching the system from a normal mode of operation into a transition mode of operation; updating control and state register (CSR) banks of respective transceivers of the system through a mission bus used during the normal mode of operation; and operating the system in the new frequency.

Abstract: A tiered memory fabric workload performance optimization system includes a workload management device coupled to a processing fabric and a memory fabric. The workload management system receives a workload request to perform a workload including sub-workloads, and identifies a respective processing system in the processing fabric for performing each of the sub-workloads. The workload management device then determines, for use by each respective processing system identified for performing the sub-workloads, a respective memory system in the memory fabric to provide memory systems in different memory tiers in the memory fabric that optimize characteristic(s) of a workload performance pipeline provided by the respective processing systems identified for performing the sub-workloads.

Abstract: A leader control plane node of a set of control plane nodes of a node cluster, may receive a request to store data in a distributed storage system including a set of access manager nodes. The leader control plane node may generate cache data identifying an instruction from the leader control plane node to one or more access manager nodes managed by the leader control plane node of the plurality of access manager nodes, the instruction instructing the one or more access manager nodes to store the data indicated in the request. The leader control plane node may then transmit a replication instruction to one or more follower control plane nodes of the plurality of control plane nodes to replicate the cache data in a respective cache of the one or more follower control plane nodes.

Abstract: A method for in-memory computing. In some embodiments, the method includes: executing, by a first function-in-memory circuit, a first instruction, to produce, as a result, a first value, wherein a first computing task includes a second computing task and a third computing task, the second computing task including the first instruction; storing, by the first function-in-memory circuit, the first value in a first buffer; reading, by a second function-in-memory circuit, the first value from the first buffer; and executing, by a second function-in-memory circuit, a second instruction, the second instruction using the first value as an argument, the third computing task including the second instruction, wherein: the storing, by the first function-in-memory circuit, of the first value in the first buffer includes directly storing the first value in the first buffer.

Abstract: A method and apparatus for cache management and eviction polices using unsupervised reinforcement learning schemes is disclosed.

Abstract: A device includes a first memory die and a second memory die directly coupled to the first memory die via a first bus. The device also includes a second bus directly coupled to the first memory die. The first memory die includes a first trim circuit that when in operation adjusts a delay of signal transmission by the first memory die to a first value, while the second memory die comprises a second trim circuit that when in operation adjusts a delay of signal transmission by the second memory die to a second value.

Abstract: A memory access method and device are provided. A memory access method may include: identifying, when an access to a page of a remote memory occurs, a type of the access; allocating a sparse buffer when the access is a sparse write; storing data for the sparse write in the sparse buffer; storing an address for the sparse write as a key and the sparse buffer as a value in a buffer table; and updating an instruction pointer to point to a next instruction.