Abstract: A method is provided for use in a storage system, comprising: identifying a first process that is arranged to execute a first type-1 node and a first type-2 node of the storage system, the first type-1 node being assigned a communication link for transmitting replication data to a target system, the first type-2 node being arranged to execute I/O requests associated with a first set of addresses in an address space; identifying a second process that is arranged to execute a second type-1 node and a second type-2 node of the storage system, the second type-1 node being not being assigned any communication link for transmitting replication data to a target system, the second type-2 node being arranged to execute I/O requests associated with a second set of addresses in the address space; and transferring at least one of the addresses in the first set to the second set.

Abstract: An apparatus including (i) a processor including a plurality of main buffer on board (BOB) memory controllers (MCs) and a secure engine, (ii) a plurality of simple BOB MCs, (iii) a secure delegator, and (iv) a plurality of memory modules. The secure delegator coupled to a first main BOB MC and a first simple BOB MC creates a secure channel. A second main BOB MC coupled to a second simple BOB MC creates a non-secure channel. The plurality of main BOB MCs, the secure engine and the secure delegator are provided within a trusted computing base (TCB) of the apparatus and the plurality of simple BOB MCs and the plurality of memory modules are provided outside the TCB. The secure delegator is configured to: (i) secure communication between the first main BOB MC and the secure delegator, and (ii) perform Path ORAM accesses to the plurality of memory modules.

Abstract: In a method for accessing an extended memory, after receiving a first memory access request from a processor system in a computer, an extended memory controller sends a read request for obtaining to-be-accessed data to the extended memory and return, to the processor system, a first response message indicating the to-be-accessed data has not been obtained. The extended memory controller writes the to-be-accessed data into a data buffer after receiving the to-be-accessed data returned by the extended memory. After receiving, from the processor system, a second memory access request comprising a second access address, the extended memory controller returns, to the processor system, the to-be-accessed data in the data buffer in response to the second memory access request, wherein the second access address is different from the first access address and points to the physical address of the to-be-accessed data.

Abstract: A system and method for an LBA RAID storage device. The LBA RAID storage device includes a plurality of data channels and a plurality of storage components. Each of the storage components is connected to one of the plurality of data channels. A storage controller is configured to receive a data and write the data to a RAID group made up of at least two storage components of the plurality of storage components that are each connected to a separate data channel.

Abstract: Techniques for improved copy on write functionality within an SSD are disclosed. In some embodiments, the techniques may be realized as a method for providing improved copy on write functionality within an SSD including providing, in memory of a device, an indirection data structure. The data structure may include a master entry for cloned data, the master entry having a reference to one or more indexes and a clone entry for the cloned data, the cloned entry having at least one of: a reference to a master index, a reference to a next index, and a value indicating an end of a data structure. The techniques may include traversing, using a computer processor, one or more copies of the cloned data using one or more of the references.

Abstract: A system and method for an LBA RAID storage device. The LBA RAID storage device includes a plurality of data channels and a plurality of storage components. Each of the storage components is connected to one of the plurality of data channels. A storage controller is configured to receive a data and write the data to a RAID group made up of at least two storage components of the plurality of storage components that are each connected to a separate data channel.

Abstract: Various embodiments are provided for providing a dynamic random-access memory (“DRAM”) cache as second type memory in a computing system by a processor. A selected amount of bytes in a memory line may be cleared using one or more spare bits of the DRAM, a data compression operation, or a combination thereof. A cache directory and data may be stored in the memory line. The DRAM cache is configured as a cache of a second type memory.

Abstract: Systems and methods presented herein provide a controller that is operable to monitor a plurality of background commands to a storage device over a pre-determined period of time and to determine how often each of the background commands is issued during the pre-determined period of time. The controller is further operable to establish a time interval for each of the background commands, and to issue each of the background commands at their respective time intervals.

Abstract: A data storage device may include a storage including a plurality of memory blocks composed of system memory blocks for storing system data and user memory blocks for storing user data; and a controller configured to: control exchange of the system and user data with the storage in response to a request of a host device; and determine whether a start condition for performing a garbage collection operation on the storage is satisfied, based on a number of bad memory blocks in the plurality of memory blocks.

Abstract: With a forever incremental snapshot configuration and a typical caching policy (e.g., least recently used), a storage appliance may evict stable data blocks of an older snapshot, perhaps unchanged data blocks of the snapshot baseline. If stable data blocks have been evicted, restore of a recent snapshot will suffer the time penalty of downloading the stable blocks for restoring the recent snapshot. Creating synthetic baseline snapshots and refreshing eviction data of stable data blocks can avoid eviction of stable data blocks and reduce the risk of violating a recovery time objective.

Abstract: A Data Storage Device (DSD) includes a Non-Volatile Memory (NVM) for storing data. A processor of the DSD receives a command from a host to access data in the NVM, and performs the command to access data in the NVM. The DSD further includes a host-trusted module functionally isolated from at least a portion of the DSD. The host-trusted module is configured to receive an instruction from the host, and perform an operation based on the instruction. According to one aspect, the operation includes a predetermined atomic operation to modify data stored in the NVM.

Abstract: Apparatuses and methods for memory array accessibility can include an apparatus with an array of memory cells. The array can include a first portion accessible by a controller of the array and inaccessible to devices external to the apparatus. The array can include a second portion accessible to the devices external to the apparatus. The array can include a number of registers that store row address that indicate which portion of the array is the first portion. The apparatus can include the controller configured to access the number of registers to allow access to the second portion by the devices external to the apparatus based on the stored row addresses.

Abstract: Devices and techniques for memory constrained translation table management are disclosed herein. A level of a translation table is logically segmented into multiple segments. Here, a bottom level of the translation table includes a logical to physical address pairing for a portion of a storage device and other levels of the translation table include references within the translation table. The multiple segments are written to the storage device. A first segment of the multiple segments is loaded to byte-addressable memory. A request for an address translation is received and determined to be for an address referred to by a second segment of the multiple segments. The first segment is then replaced with the second segment in the byte-addressable memory and the request is fulfilled using the second segment to locate a lower level of the translation table that includes the address translation.

Abstract: A system and a method of synchronizing, by a processor, between content of a first data container and content of at least one second data container may include: receiving one or more first data elements of the first data container and one or more second data elements of the at least one second data container; computing one or more first unique reference values (URVs) for the respective one or more first data elements; computing one or more second URVs for the respective one or more second data elements; storing the first data elements on a first storage element; storing the second data elements at a second storage element; comparing between a first URV and a second URV to identify data elements having diverged content; and synchronizing between content of the first data container and content of the at least one second data container based on the comparison.

Abstract: Technologies for stochastic associative search operations in memory (e.g., a three-dimensional cross-point memory) include a compute device. The compute device has a memory including a matrix that stores individually addressable bit data and is formed by rows and columns. The compute device receives a request to retrieve a subset of the bit data stored in the matrix. The request includes a search key indicative of the subset of bit data, and the search key is formed on a same axis as the rows. The compute device identifies one or more candidate data sets in the matrix based on a search for matching bit data of the search key with bit data in one or more of the columns. The compute device outputs the identified candidate data sets.

Abstract: Systems and methods are described, and an example system includes logic that implements a user interface and that accepts an indicator of data, and upon identifying the data is restricted access, receives via the interface attributes of tasks, and of the user, and determines a task-user attribute matrix based on the user input. The logic sends a data-coefficient request to access modules, receives a reply message that includes sensitivity metadata coefficient, a privacy metadata coefficient, a combinability metadata coefficient, and a security metadata coefficient. The logic constructs, using a content of the reply message, a metadata coefficient matrix. The logic applies a dynamic access evaluation that is based on the task-user attribute matrix and the metadata coefficient matrix and, upon a positive evaluation, accesses the restricted-access data and provides the accessed data to a data cache. Optionally, the data cache feeds a system of system operational analytics.

Abstract: A computer-implemented method according to one embodiment includes receiving, by a target system from a source system, a description of a set of data updates that are to be written to the target system. For each given portion of data of the target system that is to be rewritten during performance of the set of data updates, forward lookup is performed on the target system for determining a physical storage address of the given portion of data. The method further includes marking each of the determined physical storage addresses of the portions of data of the target system in a copy of a reverse lookup table of the target system. The marked-up reverse lookup table is used for determining an ordering in which the performance of the set of data updates would result in a least amount of garbage collection being performed while performing the set of data updates.

Abstract: A computing system including: a host interface configured to parse a command packet from a command address medium; and a command block, coupled to the host interface, configured to: assemble a command from the command packet.

Abstract: Data memory node (400) for ESM (Emulated Share Memory) architectures (100, 200), comprising a data memory module (402) containing data memory for storing input data therein and retrieving stored data therefrom responsive to predetermined control signals, a multi-port cache (404) for the data memory, said cache being provided with at least one read port (404A, 404B) and at least one write port (404C, 404D, 404E), said cache (404) being configured to hold recently and/or frequently used data stored in the data memory (402), and an active memory unit (406) at least functionally connected to a plurality of processors via an interconnection network (108), said active memory unit (406) being configured to operate the cache (404) upon receiving a multioperation reference (410) incorporating a memory reference to the data memory of the data memory module from a number of processors of said plurality, wherein responsive to the receipt of the multioperation reference the active memory unit (406) is configured to proces

Abstract: Techniques are provided for background deduplication using trusted fingerprints. Trusted fingerprints of blocks are inserted into a trusted fingerprint store as the blocks are being allocated by a file system sequentially according to block numbers of the blocks. In this way, the trusted fingerprint store is indexed by block numbers of where the blocks are stored. Blocks that are to be deduplicated are identifying by sorting the blocks based upon weak fingerprints, and moving duplicates to a dup file. The dup file is sorted based upon block numbers. Trusted fingerprints are loaded from the trusted fingerprint store for deduplicating the blocks within the dup file.