Abstract: In one embodiment, a memory that is delineated into transparent and non-transparent portions. The transparent portion may be controlled by a control unit coupled to the memory, along with a corresponding tag memory. The non-transparent portion may be software controlled by directly accessing the non-transparent portion via an input address. In an embodiment, the memory may include a decoder configured to decode the address and select a location in either the transparent or non-transparent portion. Each request may include a non-transparent attribute identifying the request as either transparent or non-transparent. In an embodiment, the size of the transparent portion may be programmable. Based on the non-transparent attribute indicating transparent, the decoder may selectively mask bits of the address based on the size to ensure that the decoder only selects a location in the transparent portion.

Abstract: Apparatuses and methods for prefetch generation are disclosed. Prefetching circuitry receives addresses specified by load instructions and can cause retrieval of a data value from an address before that address is received. Stride determination circuitry determines stride values as a difference between a current address and a previously received address. Plural stride values corresponding to a sequence of received addresses are determined. Multiple stride storage circuitry stores the plurality of stride values determined by the stride determination circuitry. New address comparison circuitry determines whether a current address corresponds to a matching stride value based on the plurality of stride values stored in the multiple stride storage circuitry. Prefetch initiation circuitry can causes a data value to be retrieved from a further address, wherein the further address is the current address modified by the matching stride value of the plurality of stride values.

Abstract: Examples disclosed herein relate, in one aspect, to method of searching a content addressable memory (CAM) that stores a plurality of entries. The method may include obtaining a search word corresponding to a matching data word stored in a matching entry of the CAM, where the matching entry may include a plurality of data words. The method may also include determining, based at least on a value of a predetermined bit of the search word, a search mask to mask off any data words within the matching entry other than the matching data word. The method may also determine, based on the search mask and a search key that includes the search word, the address of the matching entry within the CAM.

Abstract: Embodiments of the present disclosure relate to a method and apparatus for managing cache. The method comprises determining a cache flush time period of the cache for a lower-layer storage device associated with the cache. The method further comprises: in response to a length of the cache flush time period being longer than a threshold length of time, in response to receiving a write request, determining whether data associated with the write request has been stored into the cache. The method further comprises: in response to a miss of the data in the cache, storing the write request and the data in the cache without returning a write completion message for the write request.

Abstract: Exemplary methods and apparatus are provided to reduce read retry latency within solid state devices (SSDs) with non-volatile memories (NVMs). The reduction in read retry latency may be accomplished in some examples by prioritizing read recovery of a regular codeword over an irregular codeword for a cross-die logical page, irrespective of the location in the page with read errors. In an illustrative example, a processor (a) performs a read retry for a second codeword by setting a read voltage level to a first level for a first die, then advancing through a read retry table for the second die until the second codeword is read successfully, and (b) then performs a read retry for the first codeword by setting a read voltage level for the second die to a second level, then advancing through a read retry table for the first die until the first codeword is successfully read.

Abstract: A method and apparatus for operating a solid state drive is disclosed comprising receiving at least two commands from a host requiring an action by the solid state drive in a preliminary order, ordering the at least two commands based upon a quality of service classification for the at least two commands to a final order and executing the at least two commands on the solid state drive in the final order, wherein an operational parameter of the solid state drive is modified by at least one of the at least two commands.

Abstract: Storage device programming methods, systems and devices are described. A method may generate a mapping of data based on a set of data, the mapping of data including a first mapped data and a second mapped data. The method may include performing a first programming operation to write, in a first mode, the first mapped data to the memory device. The method may include storing the second mapped data to a cache. The method may include generating a second set of data, based on an inverse mapping of the mapping of data including the second mapped data from the cache and the first mapped data from the memory device, for writing, in a second mode, to the memory device, wherein the second set of data includes the set of data, and the first mode and the second mode correspond to different modes of writing to the memory device.

Abstract: Embodiments of the present disclosure relates to a method and device of data access. The method comprises determining whether target data stored in a non-volatile storage device is cached in a memory. The target data is organized in a first level of a multi-way tree in the storage device. The method further comprises, in response to determining that the target data is missing in the memory, moving the target data from the storage device into the memory. Besides, the method comprises, in response to the target data being accessed from the memory, adding a reference to the target data to a first list, the first list recording a sequence for accessing data in the first level.

Abstract: A shared storage architecture persistently stores database files in non-volatile memories (NVMs) of a plurality of computing nodes of a multi-node DBMS. The computing nodes of the multi-node DBMS store data blocks in NVM and each computing node of the DBMS stores copies of each data block stored on the plurality of computing nodes. A computing node that disconnects and subsequently rejoins the DBMS employs an on-demand approach to resilvering stale data blocks that have been updated in other computing nodes in the DBMS while the computing node was offline. A data block may be resilvered on-demand based on an I/O request for a specific data block from a workload running on the reconnected computing node. Stale data blocks on the reconnected computing node are not resilvered unless they are accessed by the workload.

Abstract: One or more embodiments provide techniques for accessing a memory page of a virtual machine for which loading might have been deferred, according to an embodiment of the invention, includes the steps of examining metadata of the memory page and determining that a flag in the metadata for indicating that the contents of the memory page needs to be updated is set, and updating the contents of the memory page.

Abstract: Data compression schemes may indicate the length of the compressed data block in a header or in the compressed data itself. If the start and end of the data block are known before the decoding process has completed by the decoding stage, a header processing stage can ‘skip ahead’ to the start of the next block to begin processing the header of the next block while the current block is still being decoded. Thus, the header processing stage and the decoding stage are operated concurrently. If the end of the compressed block is indicated in the compressed data itself the end of the data block is not known until the end of the compressed data block is reached. For these types of compressed data blocks, the header processing stage waits until the decoding stage finishes with the preceding block before processing the header of the current block.

Abstract: A system and method for an LBA RAID storage device. The LBA RAID storage device includes a plurality of data channels and a plurality of storage components. Each of the storage components is connected to one of the plurality of data channels. A storage controller is configured to receive a data and write the data to a RAID group made up of at least two storage components of the plurality of storage components that are each connected to a separate data channel.

Abstract: Described are memory modules that include address-buffer components and data-buffer components that together support wide- and narrow-data modes. The address-buffer component manages communication between a memory controller and two sets of memory components. In the wide-data mode, the address-buffer enables memory components in each set and instructs the data-buffer components to communicate full-width read and write data by combining data from or to from both sets for each memory access. In the narrow-data mode, the address-buffer enables memory components in just one of the two sets and instructs the data-buffer components to half-width read and write data with one set per memory access.

Abstract: Described is a system (and technique) to determine an appropriate path to a storage device and scheduling a data transfer by taking into consideration bandwidth, device performance, and the nature of the transfer. The system may use an efficient implementation to reduce overhead when making such a determination by utilizing a reservation table and selecting a dispatch that is efficient for a particular data transfer. For example, the system may determine a first-fit and a future-fit scheduling for an I/O request for each path to a storage device. The system may determine completion times for each of the types of scheduling for each of the paths, and accordingly, select the path and schedule with the earliest completion time.

Abstract: With omission of a duplication process of compressed data, a cache access frequency is reduced to improve throughput. A storage system includes first and second control units and a storage drive. Upon receiving a data write command, the first control unit stores data to be subjected to the write command in a first cache area of the first control unit, and stores the data in a second cache area of the second control unit to perform duplication, and upon completion of the duplication, the first control unit transmits a response indicating an end of write, performs a predetermined process on the data to be subjected to the write command, stores the data in a buffer area, reads the data stored in the buffer area, and transmits the read data to the storage drive.

Abstract: Method and system for performing data movement operations is described herein. One embodiment of a method includes: storing data for a first memory address in a cache line of a memory of a first processing unit, the cache line associated with a coherency state indicating that the memory has sole ownership of the cache line; decoding an instruction for execution by a second processing unit, the instruction comprising a source data operand specifying the first memory address and a destination operand specifying a memory location in the second processing unit; and responsive to executing the decoded instruction, copying data from the cache line of the memory of the first processing unit as identified by the first memory address, to the memory location of the second processing unit, wherein responsive to the copy, the cache line is to remain in the memory and the coherency state is to remain unchanged.

Abstract: Increasing the scope of local purges of structures associated with address translation. A hardware thread of a physical core of a machine configuration issues a purge request. A determination is made as to whether the purge request is a local request. Based on the purge request being a local request, entries of a structure associated with address translation are purged on at least multiple hardware threads of a set of hardware threads of the the machine configuration.

Abstract: Methods and apparatus for memory management are described. In a disclosed embodiment, a system has a first and a second processor, with each processor able to access a memory system. A first work unit is received for execution by the first processor, with the memory system being accessed. A second work unit is generated for execution by a second processor upon execution of a first work unit. Only after the memory system is updated does processing of the second work unit by the second processor occur. This work unit message based ordering provides relay consistency for memory operations of multiple processors.

Abstract: Systems and methods presented herein provide a controller that is operable to monitor a plurality of background commands to a storage device over a pre-determined period of time and to determine how often each of the background commands is issued during the pre-determined period of time. The controller is further operable to establish a time interval for each of the background commands, and to issue each of the background commands at their respective time intervals.

Abstract: A memory system includes: one or more memory modules, each comprising a plurality of memory devices having corresponding write commit policies; and one or more memory controllers coupled to the one or more memory modules, the one or more memory controllers having a configurable write operation protocol to operate with the memory devices according to the corresponding write commit policies.