Patents Examined by Zhuo H. Li
  • Patent number: 11048641
    Abstract: Provided are a computer program product, system, and method for managing cache segments between a global queue and a plurality of local queues using a machine learning module. Cache segment management information related to management of segments in the local queues and accesses to the global queue to transfer cache segments between the local queues and the global queue, are provided to a machine learning module to output an optimum number parameter comprising an optimum number of segments to maintain in a local queue and a transfer number parameter comprising a number of cache segments to transfer between a local queue and the global queue. The optimum number parameter and the transfer number parameter are sent to a processing unit having a local queue to cause the processing unit to transfer the transfer number parameter of cache segments between the local queue to the global queue.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: June 29, 2021
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Kevin J. Ash, Beth A. Peterson, Matthew R. Craig
  • Patent number: 11036430
    Abstract: Computer software that adjusts a performance capability of a storage volume by (i) determining a current storage volume to store data having a workload pattern, wherein a cycle of the workload pattern includes a hot period and a cold period, (ii) determining a time limit window of the current storage volume, wherein the time limit window is a shortest time window within which performance capability of the current storage volume is to be kept without adjustment, (iii) determining a low performance period of the current storage volume corresponding to the cold period, and (iv) in response to the low performance period being greater than or equal to the time limit window, reducing the performance capability of the current storage volume during the low performance period.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: June 15, 2021
    Assignee: International Business Machines Corporation
    Inventors: Long Wen Lan, Yang Liu, Duo Chen
  • Patent number: 11029879
    Abstract: A method of page size aware scheduling and a non-transitory computer-readable storage medium having recorded thereon a computer program for executing the method of page size aware scheduling are provided. The method includes determining a size of a media page; determining if the media page is open or closed; performing, by a memory controller, a speculative read operation if the media page is determined to be open; and performing, by the memory controller, a regular read operation if the media page is determined to be closed.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: June 8, 2021
    Inventors: Dimin Niu, Mu Tien Chang, Hongzhong Zheng, Sun Young Lim, Jae-Gon Lee, Indong Kim
  • Patent number: 11016888
    Abstract: A method for compressing data in a local cache of a web server is described. A local cache compression engine accesses values in the local cache and determines a cardinality of the values of the local cache. The local cache compression engine determines a compression rate of a compression algorithm based on the cardinality of the values of the local cache. The compression algorithm is applied to the cache based on the compression rate to generate a compressed local cache.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: May 25, 2021
    Assignee: eBay Inc.
    Inventor: Amit Desai
  • Patent number: 11016907
    Abstract: Increasing the scope of local purges of structures associated with address translation. A hardware thread of a physical core of a machine configuration issues a purge request. A determination is made as to whether the purge request is a local request. Based on the purge request being a local request, entries of a structure associated with address translation are purged on at least multiple hardware threads of a set of hardware threads of the machine configuration.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: May 25, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jonathan D. Bradbury, Fadi Y. Busaba, Lisa Cranton Heller
  • Patent number: 11010056
    Abstract: A data operating method, device, and system are provided and relate to the computer field, so as to resolve a prior-art problem of low efficiency of performing a data operation on a block device by a CPU. The method includes: receiving an operation instruction sent by a CPU; when the operation instruction is a read instruction, reading a first data block in the block device and returning to-be-read data in the first data block to the CPU; or when the operation instruction is a write instruction, writing, into a cache, to-be-written data indicated by the write instruction, and writing, into the block device, a second data block that includes the to-be-written data. The method is used to operate data in a block device.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: May 18, 2021
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Fei Xia, Mingyu Chen, Dejun Jiang, Jin Xiong
  • Patent number: 10996899
    Abstract: Disclosed herein is a computer storage array providing one or more remote initiators with NVMe over Fabrics (NVMe-oF) access to one or more storage devices connected to the storage array. According to an example embodiment, the computer storage array comprises: a computer processor configured to run an operating system for managing networking protocols; a network switch configured to establish an NVMe-oF connection and route data between the initiators and the storage devices; a baseboard management controller (BMC) configured to configure a network setting or NVMe-oF setting of the storage devices; a PCIe switch connecting the BMC with each of the storage devices via a PCIe bus; and a computer motherboard including the PCIe bus and to which the computer processor, network switch, BMC and PCIe switch are installed.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: May 4, 2021
    Inventors: Sompong Paul Olarig, Son T. Pham, Ramdas Kachare
  • Patent number: 10977179
    Abstract: A method and apparatus for cache management and eviction polices using unsupervised reinforcement learning schemes is disclosed.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: April 13, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Opher Lieber, Ariel Navon, Alexander Bazarsky, Shay Benisty
  • Patent number: 10936211
    Abstract: There is described a method, data processing apparatus and computer program product for initializing storage protection, the storage protection for enforcing access permission for a region of storage configured in a layout of regions according to at least one security constraint, the method comprising: receiving a set of storage requirements; generating a layout whereby the layout comprises a combination of storage regions that accommodate the storage requirements within the at least one security constraint; and configuring the storage protection according to the generated layout, wherein generating a layout comprises: calculating, for each storage requirement, a list of all storage regions that could accommodate the storage requirement within the at least one security constraint; selecting and testing combinations of storage regions until a selected combination accommodates the storage requirements within the at least one security constraint; and providing the accommodated combination of storage regions as a
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: March 2, 2021
    Assignee: ARM IP LTD
    Inventors: Alessandro Angelino, Milosch Meriac, Niklas Lennart Hauser
  • Patent number: 10929043
    Abstract: Techniques are described for reserving space on a destination node or volume for increasing the likelihood of a successful data transfer in a distributed storage environment. A reservation may be retried at one or more destinations if the reservation fails at a first destination. In some embodiments, the data-transfer process can be paused or terminated prior to data being transferred to one or more destinations if a reservation fails. Reserving space on a destination node or volume can increase the likelihood of a successful data transfer, which can increase the likelihood of efficient resources usage in a storage system.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: February 23, 2021
    Assignee: NETAPP, INC.
    Inventors: Tymoteusz Altman, Yi Zhang, Dheeraj Raghavender Sangamkar, Emalayan Vairavanathan
  • Patent number: 10929298
    Abstract: A processor of an aspect includes a plurality of packed data registers, and a decode unit to decode a no-locality hint vector memory access instruction. The no-locality hint vector memory access instruction to indicate a packed data register of the plurality of packed data registers that is to have a source packed memory indices. The source packed memory indices to have a plurality of memory indices. The no-locality hint vector memory access instruction is to provide a no-locality hint to the processor for data elements that are to be accessed with the memory indices. The processor also includes an execution unit coupled with the decode unit and the plurality of packed data registers. The execution unit, in response to the no-locality hint vector memory access instruction, is to access the data elements at memory locations that are based on the memory indices.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: February 23, 2021
    Assignee: Intel Corporation
    Inventor: Christopher J. Hughes
  • Patent number: 10915461
    Abstract: Embodiments of the present invention are directed to a computer-implemented method for cache eviction. The method includes detecting a first data in a shared cache and a first cache in response to a request by a first processor. The first data is determined to have a mid-level cache eviction priority. A request is detected from a second processor for a same first data as requested by the first processor. However, in this instance, the second processor has indicated that the same first data has a low-level cache eviction priority. The first data is duplicated and loaded to a second cache, however, the data has a low-level cache eviction priority at the second cache.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: February 9, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ekaterina M. Ambroladze, Robert J. Sonnelitter, III, Matthias Klein, Craig Walters, Kevin Lopes, Michael A. Blake, Tim Bronson, Kenneth Klapproth, Vesselina Papazova, Hieu T Huynh
  • Patent number: 10884653
    Abstract: A computer-implemented method according to one embodiment includes sending, from a host to a storage drive, a read request for data, receiving, at the host from the storage drive, a portion of the data as fixed-size two-dimensional units, where the fixed-size two-dimensional units are mapped to fixed-size one-dimensional user data blocks located at the host, and performing one or more actions at the host, utilizing the portion of the data.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: January 5, 2021
    Assignee: International Business Machines Corporation
    Inventors: Paul M. Greco, Edwin R. Childers, Simeon Furrer, Roy D. Cideciyan, Mark A. Lantz
  • Patent number: 10878869
    Abstract: A memory device may be configured to receive a differential data strobe signal and an external data signal from outside the memory device, the memory device may include control circuitry configured to, extract a common mode of the differential data strobe signal to generate a common mode signal, generate an internal data signal based on the external data signal and the common mode signal, and generate an internal data strobe signal based on the differential data strobe signal, the internal data strobe signal associated with latching the internal data signal.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: December 29, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ju-ho Jeon, Han-gi Jung, Hun-dae Choi
  • Patent number: 10860227
    Abstract: Provided herein may be a memory controller, a memory system having the same, and a method of operating the same. The memory controller may include an operating environment determiner configured to determine an operating environment of a memory device based on at least one of surrounding environment-sensing data, and a central processing unit (CPU) configured to determine operating characteristics of the memory device required in the determined operating environment, select a policy depending on the determined operating characteristics, and control an operation of the memory device based on the selected policy.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: December 8, 2020
    Assignee: SK hynix Inc.
    Inventors: Yong Jin, Duck Hoi Koo, Jin Pyo Kim
  • Patent number: 10860257
    Abstract: An information processing apparatus includes a RAM; a non-volatile memory storing setting information in which a compression method is set for each of a plurality of RAM disks, the setting information including a plurality of compression methods; and circuitry. The circuitry is configured to create each of the plurality of RAM disks with the compression method mounted, in the RAM, according to the setting information; request writing and reading of data from an application; write the data into a corresponding RAM disk of the plurality of RAM disks corresponding to the application, in response to a writing request of the data from the application; and compress the data in the compression method mounted on the corresponding RAM disk.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: December 8, 2020
    Assignee: Ricoh Company, Ltd.
    Inventors: Daiki Sakurada, Hideaki Yamamoto, Hiroyuki Ishihara, Tomoe Kitaguchi, Ryuta Aoki
  • Patent number: 10831369
    Abstract: A method and system for synchronizing caches after reboot are described. In a cached environment, a host server stores a cache counter associated with the cache, which can be stored in the cache itself or in another permanent storage device. When data blocks are written to the cache, metadata for each data block is also written to the cache. This metadata includes a block counter based on a value of the cache counter. After a number of data operations are performed in the cache, the value of the cache counter is updated. Then, each data block is selectively updated based on a comparison of the value of the cache counter with a value of the block counter in the metadata for the corresponding data block.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: November 10, 2020
    Assignee: NETAPP, INC.
    Inventors: Somasundaram Krishnasamy, Brian McKean, Yanling Qi
  • Patent number: 10824376
    Abstract: A non-volatile memory system comprises a memory structure and a control circuit connected to the memory structure. The control circuit includes a programmable and reprogrammable microcontroller. The microcontroller has a first processor that executes instructions to coordinate sequences of voltages applied to the memory structure by a first circuit in order to perform memory operations. The microcontroller has a second processor that executes second instructions to control a second circuit to test conditions of the non-volatile memory cells in response to the voltages applied to the memory structure. The microcontroller may have a third processor that controls the flow of the memory operation and directs the first and second processors to execute the instructions. The instructions of the various processors may be updated, which provides for flexible flow, core operation control, and condition testing.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: November 3, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Chi-Lin Hsu, Tai-Yuan Tseng, Yan Li, Hiroyuki Mizukoshi
  • Patent number: 10795834
    Abstract: A memory module having reduced access granularity. The memory module includes a substrate having signal lines thereon that form a control path and first and second data paths, and further includes first and second memory devices coupled in common to the control path and coupled respectively to the first and second data paths. The first and second memory devices include control circuitry to receive respective first and second memory access commands via the control path and to effect concurrent data transfer on the first and second data paths in response to the first and second memory access commands.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: October 6, 2020
    Assignee: Rambus Inc.
    Inventors: Craig E. Hampel, Frederick A. Ware
  • Patent number: 10795768
    Abstract: Apparatus and method for managing data in a multi-device storage system, such as a RAID (redundant array of independent discs) system. Distributed data sets are stored across a plurality of storage devices. A selected storage device is replaced with a new storage device responsive to an anomalous event. A rebuild operation is performed to reconstruct data from the selected storage device to the new storage device. The rebuild process includes accessing a list of distributed data sets in a local memory. For each distributed data set in the list identified as constituting valid data, read commands are issued to the remaining storage devices and a write command is issued to the new storage device. For each distributed data set in the list identified as constituting unused data, a data clear command is issued to each of the remaining storage devices and to the new storage device.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: October 6, 2020
    Assignee: Seagate Technology LLC
    Inventors: Kushal R. Hosmani, Thomas George Wicklund, Ian Davies, Ryan Patrick McCallister