Abstract: A method for improving the uniformity of connection performance of an assembly surface based on zoned hardening is provided. Through a finite element contact analysis of the assembly surface, a topology optimization of the hardening layer layout of the assembly surface is carried out with the aim of improving the uniformity of the connection performance of the assembly surface. The design is based on the optimized theoretical data, and uses the laser hardening technology to realize the zoned differential hardening of the assembly surface. By performing the zoned differential hardening on the assembly surface, the uniformity of the connection performance of the assembly surface can be effectively improved, and the purpose of improving the high cycle fatigue and the vibration of the high-end equipment parts such as aero-engines can be further achieved.

Abstract: A system includes a substrate having a first side and a second side opposite the first side, a cell on the substrate having a first pin on either the first side or the second side, and a second pin on the second side, a first signal connected to the first pin, and a second signal connected to the second pin.

Abstract: A tool includes a barrel, a guiding wire, and an electrically conductive member. The barrel is made of electrically conductive material. The guiding wire is disposed in the barrel. The barrel and the guiding wire are directly or indirectly connected to two opposite electrodes of a power source. The electrically conductive member is connected to an outer periphery of the guiding wire and is electrically connected to the guiding wire. The electrically conductive member is disposed between the barrel and the guiding wire and is spaced from the barrel. When the power source is activated, an electric arc is generated between the electrically conductive member and the barrel.

Abstract: A tool includes a barrel, a guiding wire, and an electrically conductive member. The barrel is made of electrically conductive material. The guiding wire is disposed in the barrel. The barrel and the guiding wire are directly or indirectly connected to two opposite electrodes of a power source. The electrically conductive member is connected to an outer periphery of the guiding wire and is electrically connected to the guiding wire. The electrically conductive member is disposed between the barrel and the guiding wire and is spaced from the barrel. When the power source is activated, an electric arc is generated between the electrically conductive member and the barrel.

Abstract: A cable comprising: a core wires; a shielding layer covering the core wires; and an outer insulating layer covering the shielding layer; wherein the shielding layer is aluminum coated PP, or aluminum coated PE, or aluminum coated PTFE, or copper coated PP, or copper coated PE, or copper coated PTFE.

Abstract: A cable includes: a pair of core wires; a shielding layer covering the pair of core wires; and an outer insulating layer covering the shielding layer, wherein each of the core wires includes an inner conductor, an inner insulating layer covering the inner conductor, and a first shielding layer covering the inner insulating layer, and each core wire includes only one inner conductor.

Abstract: A failure-in-time (FIT) evaluation method for an IC is provided. The FIT evaluation method includes accessing data representing a layout of the IC including a metal line and a plurality of vertical interconnect accesses (VIAs); picking a plurality of nodes along the metal line; dividing the metal line into a plurality of metal segments based on the nodes; and determining FIT value for each of the metal segments to verify the layout and fabricate the IC. The number of the nodes is less than the number of the VIAs, and a distance between two adjacent VIAs of the VIAs is less than a width of the metal line.

Abstract: A method (of fabricating a power grid (PG) arrangement in a semiconductor) includes: forming a first conductive layer including segments which are conductive, including forming first segments designated for a first reference voltage and second segments designated for a second reference voltage, and interspersing the first and second segments; relative to a first direction; and forming a second conductive layer over the first conductive layer, the second conductive layer including segments that are conductive, including forming third segments designated for the first reference voltage and fourth segments designated for the second reference voltage, interspersing the third and fourth segments relative to a second direction, the second direction being perpendicular to the first direction, and arranging the segments in the second conductive layer substantially asymmetrically including, relative to the first direction, locating each fourth segment substantially asymmetrically between corresponding adjacent ones of

Abstract: A method of generating a power network layout is provided. A first conductive line, generated by a processor, is in a first conductive layer along a first direction. A plurality of second conductive lines, generated by a processor, is in a second conductive layer along a second direction, substantially vertical to the first direction. The second conductive lines overlap with the first conductive line. A first plurality of interlayer vias, generated by a processor, is interposed between the first conductive layer and the second conductive layer at where the second conductive lines overlapping the first conductive line. Each of the second conductive lines has a width such that a first routing track adjacent to the first conductive line is available for routing or a second routing track adjacent to one of the plurality of second conductive lines is available for routing.

Abstract: A method of forming a semiconductor device includes: providing a first circuit having a plurality of circuit cells; analyzing a loading capacitance on a first pin cell connecting a first circuit cell and a second circuit cell in the plurality of circuit cells to determine if the loading capacitance of the first pin cell is larger than a first predetermined capacitance; replacing the first pin cell by a second pin cell for generating a second circuit when the loading capacitance is larger than the first predetermined capacitance, wherein the second pin cell is different from the first pin cell; and generating the semiconductor device according to the second circuit.

Abstract: A method of forming an IC structure includes forming first and second power rails at a power rail level. First metal segments are formed at a first metal level above the power rail level. Each first metal segment of the plurality of first metal segments overlap one or both of the first power rail or the second power rail. First vias are formed between the power rail level and the first metal level. Second metal segments are formed at a second metal level above the first metal level. At least one second metal segment of the plurality of second metal segments overlaps the first power rail. At least one second metal segment of the plurality of second metal segments overlaps the second power rail. A plurality of second vias are formed between the first metal level and the second metal level.

Abstract: An antenna and an antenna array, the antenna including a dielectric resonator fed by a feeder connected to a ground plane, wherein the dielectric resonator is arranged to emit an electromagnetic radiation along a wave propagation axis upon an electric excitation input to the feeder, and wherein the electromagnetic radiation is equivalent to a combination of a plurality of electromagnetic wave components.

Abstract: A system includes a processor configured to determine a power parameter associated with a cell in an integrated circuit (IC) layout diagram. In response to the determined power parameter exceeding a design criterion, the processor is configured to perform a modification of the IC layout diagram, the modification including at least one of altering a placement of the cell in the IC layout diagram or modifying a power delivery path to the cell. The power parameter includes at least one of a power density of a tile containing the cell, a voltage drop of the tile containing the cell, or a voltage drop of the cell.

Abstract: An integrated circuit (IC) structure includes a power rail oriented in a power rail direction and first metal segments above the power rail, oriented in a first metal level direction perpendicular to the power rail direction. First vias positioned between the power rail and the first metal segments are positioned at locations where first metal segments overlap the power rail. A second metal segment is positioned above the first metal segments, overlaps the power rail, and is oriented in the power rail direction. Second vias are positioned above the first vias between the first metal segments and the second metal segments, and a power strap is positioned above the second metal segment. The power strap is electrically connected to the power rail, each first metal segment of the plurality of first metal segments has a minimum width, and the power strap has a width greater than a minimum width.

Abstract: A method (of generating a revised layout diagram of a conductive line structure for an IC) including: for a first set of pillar patterns that represents portions of an M(i) layer of metallization and where i is a non-negative number, the first set including first and second pillar patterns which extend in a first direction, are non-overlapping of each other with respect to the first direction, are aligned with each other and have a first distance of separation, determining a first distance of separation as between corresponding immediately adjacent members of the first set; recognizing that the first distance is less than a transverse routing (TVR) separation threshold for an M(i+j) layer of metallization, where j is an integer and j?2; and increasing the first distance so as to become a second distance which is greater than the TVR separation threshold of the M(i+j) layer.

Abstract: The invention provides a method for suppressing thermal runaway of lithium batteries, which is included a step of providing a lithium battery capable of performing charging and discharging, which includes an electrochemical reaction system. When the temperature of the lithium battery reaches to a predetermined temperature, a metal ion (A) and an amphoteric metal ion (B) are applied to the positive active material layer and the negative active material layer of the lithium battery to passivate the positive active material layer and the negative active material layer. The metal ion (A) is selected from a non-lithium alkali metal ion, an alkaline earth metal ion or a combination thereof to prevent the thermal runaway from occurring.

Abstract: A method for manufacturing a semiconductor device is provided. The method comprises determining a dimensional quantity of a layout pattern having an angle relative to grid lines of a minimum grid. The minimum grid may be defined by a first quantity associated with a first direction and a second quantity associated with a second direction perpendicular to the first direction. The determination of the dimensional quantity of the layout pattern is based on the first quantity, the second quantity and the angle of the layout pattern relative to the grid lines of the minimum grid.

Abstract: A suppression element includes a passivation composition supplier and a polar solution supplier. The passivation composition supplier is capable of releasing a metal ion (A), selected from a non-lithium alkali metal ion, an alkaline earth metal ion or a combination thereof, and an aluminum etching ion (B). The polar solution of the polar solution supplier carries the metal ion (A) and the aluminum etching ion (B) to an aluminum current collector to etched through thereof, and the metal ion (A) and the aluminum ion, generated during the etching, are seeped into the electrochemical reaction system. Then, the positive active material is transferred to a crystalline state with lower electric potential and lower energy, and the negative active material is transferred y to an inorganic polymer state with higher electric potential and lower energy to prevent the thermal runaway from occurring.

Abstract: The invention provides a thermal runaway suppressant of lithium batteries and the related applications. The thermal runaway suppressant includes a passivation composition supplier, for releasing a metal ion (A), selected from a non-lithium alkali metal ion, an alkaline earth metal ion or a combination thereof, and an amphoteric metal ion (B), a polar solution supplier and an isolating mechanism, which is capable of separating the passivation composition supplier and the polar solution supplier within a predetermined temperature. When the isolating mechanism is failed and the polar solution supplier releases a polar solution to carry the metal ion (A) and the amphoteric metal ion (B) into the lithium battery and react with the positive active material and the negative active material to a state with lower energy. The voltage of the whole battery is decreased and the electrochemical reaction pathway is blocked to prevent the thermal runaway from occurring.

Abstract: In some embodiments, a fishbone structure in a power network includes a first conductive segment in a first conductive layer running in a first direction, a plurality of second conductive segments in a second conductive layer running in a second direction and a plurality of interlayer vias between the first conductive layer and the second conductive layer. The second direction is substantially vertical to the first direction. The plurality of second conductive segments overlap with the first conductive segment. The plurality of interlayer vias are formed at where the plurality of second conductive segments overlap with the first conductive segment. Each of the plurality of second conductive segments has a width such that the first conductive segment has a first unit spacing with a first adjacent conductive line or one of the plurality of second conductive segments has a second unit spacing with a second adjacent conductive line.