Abstract: A method of forming a semiconductor device includes: providing a first circuit having a plurality of circuit cells; analyzing a loading capacitance on a first pin cell connecting a first circuit cell and a second circuit cell in the plurality of circuit cells to determine if the loading capacitance of the first pin cell is larger than a first predetermined capacitance; replacing the first pin cell by a second pin cell for generating a second circuit when the loading capacitance is larger than the first predetermined capacitances, wherein the second pin cell is different from the first pin cell; and generating the semiconductor device according to the second circuit.

Abstract: The present disclosure provides a routing structure. The routing structure includes a substrate having a first circuit region and a boundary surrounding the first circuit region. The routing structure also includes a first conductive trace coupled to a first conductive pad disposed in the first circuit region. The first conductive trace is inclined with respect to the boundary of the substrate. A method of forming a routing structure is also disclosed.

Abstract: The user experience of application downloading and usage between multiple devices in a network is enhanced. One instance of an app on a first device is able to identify and verify installation and/or execution of a companion app on a second device where the two devices may have entirely different platforms (e.g., smartphone operating system and TV platform). The experience for users who have devices on the same network converge in order to improve the user experience with respect to a particular app. In this manner, an enhanced and efficient means of providing an n-screen experience with the app is enabled; ways that provide synergy between devices on the same network.

Abstract: A method of designing an integrated circuit device includes receiving an initial design of an integrated circuit, including a selection and location of a functional group of integrated circuit components, a power grid with multiple layers of conductive lines for supplying power to the components, and vias of one or more initial sizes interconnecting the conductive lines of different layers. The method further includes determining, based on a predetermined criterion such as the existence of unoccupied space for a functional unit, that a via modification can be made. The method further includes substituting the one or more of the via with a modified via of a larger cross-sectional area or a plurality of vias having a larger total cross-sectional area than the initial via. The method further includes confirming that the modified design complies with a predetermined set of design rules.

Abstract: A method includes determining a cell loading of a cell in an integrated circuit (IC) layout diagram. Based on the determined cell loading, a power parameter associated with the cell is determined. In response to the determined power parameter exceeding a design criterion, at least one of altering a placement of the cell in the IC layout diagram or modifying a power delivery path to the cell is performed. At least one of the determining the cell loading, the determining the power parameter, the altering the placement of the cell, or the modifying the power delivery path is executed by a processor.

Abstract: The invention provides a ceramic separator, which mainly includes a plurality of passive ceramic particles and an ion-conductive material located between the passive ceramic particles. The mass content of the passive ceramic particles is greater than 40% of the total mass of the ceramic separator. The ion-conductive material is mainly composed of a polymer base material which is capable of allowing metal ions to move inside the material, and an additive, which is capable of dissociating metal salts and is served as a plasticizer. The ceramic separator of the present invention has high-temperature stability and high-temperature electrical insulation.

Abstract: The present invention relates to a flexible lithium battery comprising a first current collector layer and a second current collector layer, wherein the first current collector layer has a first outer surface and a first inner surface, and the second current collector layer has a second outer surface and a second inner surface; there is a glue frame sandwiched between the first inner surface and the second inner surface to form a sealed and enclosed space, wherein there is an electrochemical system layer disposed in this sealed and enclosed space, with the electrochemical system layer comprising a first active material layer, a second active material layer, and an electrically insulating layer disposed between the first active material layer and the second active material layer; and there is a flexible adhesive layer disposed between the first inner surface and the first active material layer and/or between the second inner surface and the second active material layer, wherein this flexible adhesive layer con

Abstract: A method (of revising an initial layout diagram of a wire routing arrangement, the initial layout diagram and versions thereof being stored on a non-transitory computer-readable medium) includes identifying, in a first conductance layer of the initial layout diagram, a routed pattern and a dummy pattern, each of which extends in a first direction and revising to form a revised layout diagram. The routed patterns are functional in a representation of a circuit and the dummy patterns are non-functional in the representation of the circuit. The revising includes connecting first ends of the corresponding routed and dummy patterns and connecting second ends of the corresponding routed and dummy patterns.

Abstract: Power grid of an integrated circuit (IC) is provided. A plurality of first power lines are formed in a first metal layer. A plurality of second power lines are formed in the first metal layer and parallel to the first power lines, and the first and second power lines are interlaced in the first metal layer. A plurality of third power lines formed in a second metal layer, and the third power lines are perpendicular to the first power lines. A plurality of fourth power lines are formed in the second metal layer and parallel to the third power lines, and the third and fourth power lines are interlaced in the second metal layer. Distances from each of the third power lines to two adjacent fourth power lines are different, and distances from each of the fourth power lines to two adjacent third power lines are the same.

Abstract: One aspect of this description relates to an integrated circuit (IC) structure including a first layer and a second layer. The first layer includes a first metal structure coupled to a first power supply having a first voltage level and a second metal structure coupled to a second power supply having a second voltage level different from the first voltage level. The second layer is formed over the first layer. The second layer includes a first nano-sheet device coupled to the first metal structure and a second nano-sheet device adjacent to the first nano-sheet device. The second nano-sheet device is coupled to the second metal structure. A distance between the first nano-sheet device and the second nano-sheet device is less than a minimum n-well to n-well spacing.

Abstract: A method of a layout diagram (of a conductive line structure for an IC) including: for a first set of pillar patterns included in an initial layout diagram that represents portions of an M(i) layer of metallization and where i is a non-negative number, the first set including first and second pillar patterns which are non-overlapping of each other, which have long axes that are substantially collinear with a reference line, and which have a first distance of separation, determining a first distance of separation as between corresponding immediately adjacent members of the first set; recognizing that the first distance is less than a transverse routing (TVR) separation threshold for an M(i+j) layer of metallization, where j is an integer and j?2; and increasing the first distance so as to become a second distance which is greater than the TVR separation threshold of the M(i+j) layer.

Abstract: The invention provides a composite separating layer, which is composed of a separating body and a structural reinforcing layer disposed on one side of the separating body. The separating body is ion-conductive and without holes, so no soft shorting would be occurred. Also, by the structural reinforcing layer, the mechanical strength of the entire separating layer is enhanced. Therefore, when the separating body is subjected to impact or squeeze to deform, the contact between the positive and negative electrode layers are avoided in the presence of the structural reinforcing layer. The thickness of the overall separating layer can be greatly reduced from this arrangement of the separating body and the structural reinforcing layer.

Abstract: A battery structure is disclosed. The battery structure includes a first current collector layer, a first active material layer, a spacer layer, a first plastic frame, a second active material layer and a second current collector layer. The first active material layer is disposed on the first current collector layer. The spacer layer is disposed on the first active material and completely covers the top surface of the first active material layer. The first plastic frame is disposed on the side wall of the spacer layer and the top of the first plastic frame has a protruding part which extends to the top surface of the spacer. The second active material layer is disposed on the spacer layer and the protruding part. The second active material is isolated from the first active material via the space layer and the protruding part. The second current collector layer is disposed on the second active material layer.

Abstract: A battery having a protective isolation structure is disclosed comprising a first current collecting layer, a first active material layer, a spacer layer, a first glue frame, a second active material and a second current collecting layer. The first active material layer is disposed on the first current collecting layer. The spacer layer is disposed on the first active material layer. The area of the spacer layer is smaller than the area of the first active material layer so that a part of the first active material layer is exposed outside the spacer layer. The first glue frame is covering the top surface of the first active material layer exposed from the spacer layer and has a protrusion disposed on the surface of the spacer layer. The second active material layer is disposed on the surface of the spacer layer and the protrusion. The second current collecting layer is disposed on the second active material layer.

Abstract: A cable includes a pair of core wires, a shielding layer covering the pair of core wires, and an outer insulating layer covering the shielding layer, wherein each of the pair of core wires includes an inner conductor and an insulating layer spirally wound around the inner conductor, the insulating layer includes at least two layers, and winding directions of adjacent insulating layers are different.

Abstract: A cable includes: a pair of core wires; a first shielding layer covering the pair of core wires; a second shielding layer covering the first shielding layer, and an outer insulating layer covering the second shielding layer; wherein the first shielding layer is a pure metal tape, and the cable is not provided with a separate ground wire.

Abstract: A cable includes: a core wire; and an insulating outer layer covering the core wire; where in the core wire including an inner conductor, an inner insulating layer covering the inner conductor, and an outer insulating layer covering the inner insulating layer, the inner insulating layer being made of a material having dielectric constant and loss factor not higher than those of the material of the outer insulating layer, the outer insulating layer being made of a flame-retardant material.

Abstract: An integrated circuit includes a first set of devices, a set of metal layers and a header circuit. The first set of devices are configured to operate on a first supply voltage, and are located on a first layer of the integrated circuit. The set of metal layers are above the first layer, and includes a first metal layer and a second metal layer. The first metal layer extends in at least a first direction and a second direction. The header circuit is above the first set of devices. At least a portion of the header circuit is positioned between the first metal layer and the second metal layer. The header circuit is configured to provide the first supply voltage to the first set of devices, and is configured to be coupled to a first voltage supply having the first supply voltage.

Abstract: In a method, cell placement is performed to place a plurality of cells into a region of an integrated circuit (IC). A thermal analysis is performed to determine whether the region of the IC is thermally stable at an operating condition. In response to a determination that the region of the IC is thermally unstable, at least one of a structure or the operating condition of the region of the IC is changed. After the thermal analysis, routing is performed to route a plurality of nets interconnecting the placed cells. At least one of the cell placement, the thermal analysis, the changing or the routing is executed by a processor.

Abstract: A method (of revising an initial layout diagram of a wire routing arrangement) includes: identifying, in a first conductance layer of the initial layout diagram, a routed pattern and a dummy pattern, each of which extends in a first direction; the routed patterns being functional in a representation of a circuit; the dummy patterns being non-functional in the representation of the circuit; and revising to form a revised layout diagram, the revising including adding first and second jumper patterns, into a second conductance layer, which extend in a second direction substantially perpendicular to the first direction, and adding via patterns, into an interconnection layer between the first and second conductance layers, which represent (A) connections between the first jumper pattern and first ends of the corresponding routed and dummy patterns, and (B) connections between the second jumper pattern and second ends of the corresponding routed and dummy patterns.