Patents by Inventor A-NAN YANG

A-NAN YANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11089693
    Abstract: A flexible printed circuit board includes a substrate that is made of a non-metal; a first modified silicone cured layer that is provided on and in contact with the substrate and that includes a first silicone material that is cured; a metal layer that is made of at least one metal; a second modified silicone cured layer that is provided on and in contact with the metal layer and that includes a second silicone material that is cured; and a silicone adhesive layer disposed between and in contact with the first modified silicone cured layer and the second modified silicone cured layer and that includes an adhesive silicone material that is cured by being thermally polymerized after lamination thereof between the first modified silicone cured layer and the second modified silicone cured layer. Lamination of the cured modified-silicone-coated substrate and the cured modified-silicone-coated metal layer with the silicone adhesive layer improves adhesion and reduces delamination.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: August 10, 2021
    Assignees: PROLOGIUM TECHNOLOGY CO., LTD., PROLOGIUM HOLDING INC.
    Inventor: Szu-Nan Yang
  • Patent number: 11075461
    Abstract: A horn antenna includes a waveguide portion and an antenna portion operably connected with the waveguide portion. The waveguide portion has a feed port. The antenna portion is arranged to receive a linearly polarized signal from the waveguide portion and to convert the received linearly polarized signal to a circularly polarized signal for transmission.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: July 27, 2021
    Assignee: City University of Hong Kong
    Inventors: Kwok Wa Leung, Kai Lu, Nan Yang
  • Publication number: 20210224456
    Abstract: An integrated circuit layout is provided. The integrated circuit layout includes one or more first cell rows partially extending across a space arranged for an integrated circuit layout along a first direction. Each of the one or more first cell rows has a first height along a second direction perpendicular to the first direction. The integrated circuit layout includes one or more third cell rows partially extending across the space along the first direction. Each of the one or more third cell rows has a second height along the second direction, the second height different from the first height.
    Type: Application
    Filed: January 17, 2020
    Publication date: July 22, 2021
    Inventors: Sheng-Hsiung Chen, Chun-Chen Chen, Shao-huan Wang, Kuo-Nan Yang, Chung-Hsing Wang, Anderson Liao, Meng-Xiang Lee
  • Patent number: 11068249
    Abstract: The user experience of application downloading and usage between multiple devices in a network is enhanced. One instance of an app on a first device is able to identify and verify installation and/or execution of a companion app on a second device where the two devices may have entirely different platforms (e.g., smartphone operating system and TV platform). The experience for users who have devices on the same network converge in order to improve the user experience with respect to a particular app. In this manner, an enhanced and efficient means of providing an n-screen experience with the app is enabled; ways that provide synergy between devices on the same network.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: July 20, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Fabio Gava, Fei Xie, Nan Yang, Shiangfeng Lee, Murugan Viswanathan, Andrew Shelansky
  • Patent number: 11068638
    Abstract: A power grid of an integrated circuit (IC) is provided. The power grid includes a plurality of first power lines formed in a first metal layer, a plurality of second power lines formed in the first metal layer, a plurality of third power lines formed in a second metal layer and a plurality of fourth power lines formed in the second metal layer. The second power lines are parallel to the first power lines, and the first and second power lines are interlaced in the first metal layer. The third power lines are perpendicular to the first power lines. The fourth power lines are parallel to the third power lines, and the third and fourth power lines are interlaced in the second metal layer. A first power pitch between two adjacent third power lines is greater than a second power pitch between two adjacent fourth power lines.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: July 20, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Hiranmay Biswas, Kuo-Nan Yang, Chung-Hsing Wang
  • Publication number: 20210217743
    Abstract: A method includes forming a cell layer including first and second cells, each of which is configured to perform a circuit function; forming a first metal layer above the cell layer and including a first conductive feature and a second conductive feature extending along a first direction, in which the first conductive feature extends from the first cell into the second cell, and in which a shortest distance between a center line of the first conductive feature and a center line of the second conductive feature along a second direction is less than a width of the first conductive feature, and the second direction is perpendicular to the first direction; forming a first conductive via interconnecting the cell layer and the conductive feature.
    Type: Application
    Filed: March 26, 2021
    Publication date: July 15, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Fong-Yuan CHANG, Kuo-Nan YANG, Chung-Hsing WANG, Lee-Chung LU, Sheng-Fong CHEN, Po-Hsiang HUANG, Hiranmay BISWAS, Sheng-Hsiung CHEN, Aftab Alam KHAN
  • Patent number: 11064178
    Abstract: A monocular visual odometry system includes a stacked architecture. The stacked architecture receives camera data from a monocular camera and generates a depth map. Additionally, the system includes a deep virtual stereo odometry module that receives the camera data from the monocular camera and the depth map from the stacked architecture. The calculation module initializes a keyframe of the camera data using the depth map and determines a photometric error based on a set of observation points extracted from the keyframe and a set of reference points extracted from the camera data. The calculation module determines a virtual stereo photometric term using the depth map. The calculation module also optimizes a total energy function that includes the photometric error and the virtual stereo photometric term. Using the total energy function, the calculation module generates a positional parameter of the system and provides the positional parameter to an autonomous system.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: July 13, 2021
    Assignee: Artisense Corporation
    Inventors: Nan Yang, Rui Wang
  • Publication number: 20210209283
    Abstract: A method (of fabricating a power grid (PG) arrangement in a semiconductor) includes: forming a first conductive layer including segments which are conductive, including forming first segments designated for a first reference voltage and second segments designated for a second reference voltage, and interspersing the first and second segments; relative to a first direction; and forming a second conductive layer over the first conductive layer, the second conductive layer including segments that are conductive, including forming third segments designated for the first reference voltage and fourth segments designated for the second reference voltage, interspersing the third and fourth segments relative to a second direction, the second direction being perpendicular to the first direction, and arranging the segments in the second conductive layer substantially asymmetrically including, relative to the first direction, locating each fourth segment substantially asymmetrically between corresponding adjacent ones of
    Type: Application
    Filed: March 8, 2021
    Publication date: July 8, 2021
    Inventors: Hiranmay BISWAS, Chung-Hsing WANG, Chin-Shen LIN, Kuo-Nan YANG
  • Patent number: 11056743
    Abstract: A package structure and its related electricity supply system are disclosed. Two substrates of the package structure are directly or indirectly served as current collectors of the electricity supply system. The sealing frame of the package structure is made of several silicone layers having high moisture-resistance and/or high gas-resistance. Hence, the package structure mentioned may not only provide a novel electrical conduction module to lower the intrinsic impedance of the electricity supply system itself but prevent the moisture and the gas outward from the electricity supply unit inside the package structure as well. Consequently, the electrical performance and safety of the electricity supply system are both improved.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: July 6, 2021
    Assignees: PROLOGIUM TECHNOLOGY CO., LTD., PROLOGIUM HOLDING INC.
    Inventor: Szu-Nan Yang
  • Publication number: 20210200930
    Abstract: A failure-in-time (FIT) evaluation method for an IC is provided. The FIT evaluation method includes accessing data representing a layout of the IC including a metal line and a plurality of vertical interconnect accesses (VIAs); picking a plurality of nodes along the metal line; dividing the metal line into a plurality of metal segments based on the nodes; and determining FIT value for each of the metal segments to verify the layout and fabricate the IC. The number of the nodes is less than the number of the VIAs, and a distance between two adjacent VIAs of the VIAs is less than a width of the metal line.
    Type: Application
    Filed: March 17, 2021
    Publication date: July 1, 2021
    Inventors: Chin-Shen LIN, Ming-Hsien LIN, Kuo-Nan YANG, Chung-Hsing WANG
  • Publication number: 20210197526
    Abstract: An air-floating thin film bonding apparatus and its air-floating roller is provided. The apparatus is composed of an air-floating rollers, which can blow out airflow at a specific angle to be applied to the base film with three-dimensional obstacles. The positive pressure provided by the airflow can be utilized to fill the gap space caused by the three-dimensional obstacles. Therefore, the base film can bond to the bonding film tightly to overcome the wrinkles and defects caused by the three-dimensional obstacle and the problem of unflatness of the film-bonding can be solved.
    Type: Application
    Filed: November 19, 2020
    Publication date: July 1, 2021
    Applicants: PROLOGIUM TECHNOLOGY CO., LTD., Prologium Holding Inc.
    Inventors: Szu-Nan YANG, Ching-Ho WANG
  • Patent number: 11046055
    Abstract: An air-floating thin film bonding apparatus and its air-floating roller is provided. The apparatus is composed of an air-floating rollers, which can blow out airflow at a specific angle to be applied to the base film with three-dimensional obstacles. The positive pressure provided by the airflow can be utilized to fill the gap space caused by the three-dimensional obstacles. Therefore, the base film can bond to the bonding film tightly to overcome the wrinkles and defects caused by the three-dimensional obstacle and the problem of unflatness of the film-bonding can be solved.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: June 29, 2021
    Assignees: PROLOGIUM TECHNOLOGY CO., LTD., Prologium Holding Inc.
    Inventors: Szu-Nan Yang, Ching-Ho Wang
  • Publication number: 20210184359
    Abstract: A horn antenna includes a waveguide portion and an antenna portion operably connected with the waveguide portion. The waveguide portion has a feed port. The antenna portion is arranged to receive a linearly polarized signal from the waveguide portion and to convert the received linearly polarized signal to a circularly polarized signal for transmission.
    Type: Application
    Filed: December 16, 2019
    Publication date: June 17, 2021
    Inventors: Kwok Wa Leung, Kai Lu, Nan Yang
  • Patent number: 11017146
    Abstract: An integrated circuit includes a first set of devices, a set of metal layers and a header circuit. The first set of devices are configured to operate on a first supply voltage, and are located on a first layer of the integrated circuit. The set of metal layers are above the first layer, and includes a first metal layer and a second metal layer. The first metal layer extends in at least a first direction and a second direction. The header circuit is above the first set of devices. At least a portion of the header circuit is positioned between the first metal layer and the second metal layer. The header circuit is configured to provide the first supply voltage to the first set of devices, and is configured to be coupled to a second voltage supply having a second supply voltage different from the first supply voltage.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: May 25, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: John Lin, Chung-Hsing Wang, Chin-Shen Lin, Kuo-Nan Yang
  • Publication number: 20210150117
    Abstract: A method of forming a semiconductor device includes: providing a first circuit having a plurality of circuit cells; analyzing a loading capacitance on a first pin cell connecting a first circuit cell and a second circuit cell in the plurality of circuit cells to determine if the loading capacitance of the first pin cell is larger than a first predetermined capacitance; replacing the first pin cell by a second pin cell for generating a second circuit when the loading capacitance is larger than the first predetermined capacitances, wherein the second pin cell is different from the first pin cell; and generating the semiconductor device according to the second circuit.
    Type: Application
    Filed: January 25, 2021
    Publication date: May 20, 2021
    Inventors: KUO-NAN YANG, WAN-YU LO, CHUNG-HSING WANG, HIRANMAY BISWAS
  • Publication number: 20210134947
    Abstract: A semiconductor device, including: a first OD strip, a first doping region, a second OD strip, a second doping region, and a third doping region. The first OD strip extending in a first direction is disposed on the first OD strip, and includes a first-type dopant to define an active region of a first MOS. The second OD strip extending in the first direction and immediately adjacent to the first OD strip in a second direction, wherein the second direction is orthogonal with the first direction. The second doping region is disposed on the second OD strip, and includes a second-type dopant to define an active region of a second MOS. The third doping region is disposed on the second OD strip, and includes the second-type dopant and is configured to be a body terminal of the first MOS.
    Type: Application
    Filed: September 29, 2020
    Publication date: May 6, 2021
    Inventors: JUNG-CHAN YANG, HUI-ZHONG ZHUANG, CHIH-LIANG CHEN, TING-WEI CHIANG, CHENG-I HUANG, KUO-NAN YANG
  • Patent number: 10997347
    Abstract: In a method, based on an operating condition of a region of an integrated circuit (IC), a first relationship between a temperature and heating power of the region is determined. Based on a cooling capacity of the region, a second relationship between the temperature and cooling power of the region is determined. Based on the first relationship and the second relationship, it is determined whether the region is thermally stable. In response to a determination that the region is thermally unstable, at least one of a structure or the operating condition of the region is changed. At least one of the determination of the first relationship, the determination of the second relationship, the determination of thermally stability of the region, or the change of at least one of the structure or the operating condition of the region is executed by a processor.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: May 4, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wan-Yu Lo, Chung-Hsing Wang, Chin-Shen Lin, Kuo-Nan Yang
  • Publication number: 20210126294
    Abstract: The invention discloses a recycling method for oxide-based solid electrolyte with original phase, method of fabricating lithium battery and green battery thereof, which is adapted to recycle the solid-state or quasi-solid lithium batteries after discard. The oxide-based solid electrolyte is only used as an ion transport pathway, and does not participate in the insertion and extraction of lithium ions during charge and discharge cycles. Its crystal structure dose not be destroyed. Therefore, the original phase recycle of the oxide-based solid electrolyte is achieved without damage the structure or materials. The recycled the oxide-based solid electrolyte can be re-used to reduce the manufacturing cost of the related lithium battery.
    Type: Application
    Filed: October 6, 2020
    Publication date: April 29, 2021
    Applicants: PROLOGIUM TECHNOLOGY CO., LTD., Prologium Holding Inc.
    Inventor: Szu-Nan YANG
  • Publication number: 20210119245
    Abstract: The invention provides a contact surface adjusting material for solid electrolytes and composite electrolyte system thereof. The contact surface adjusting material is mainly composed of a polymer base material, which is capable of allowing metal ions to move inside the material, and an additive, which is capable of dissociating metal salts and is served as a plasticizer. The contact surface adjusting material is applied to a surface of the solid electrolytes to construct a face-to-face transmission mode. Therefore, the problems of the high resistances caused by the directly contact of the solid electrolytes are eliminated.
    Type: Application
    Filed: September 29, 2020
    Publication date: April 22, 2021
    Applicants: PROLOGIUM TECHNOLOGY CO., LTD., Prologium Holding Inc.
    Inventors: Szu-Nan YANG, Dmitry BELOV
  • Publication number: 20210119194
    Abstract: The invention provides a ceramic separator, which mainly includes a plurality of passive ceramic particles and an ion-conductive material located between the passive ceramic particles. The mass content of the passive ceramic particles is greater than 40% of the total mass of the ceramic separator. The ion-conductive material is mainly composed of a polymer base material which is capable of allowing metal ions to move inside the material, and an additive, which is capable of dissociating metal salts and is served as a plasticizer. The ceramic separator of the present invention has high-temperature stability and high-temperature electrical insulation.
    Type: Application
    Filed: September 30, 2020
    Publication date: April 22, 2021
    Applicants: PROLOGIUM TECHNOLOGY CO., LTD., Prologium Holding Inc.
    Inventors: Szu-Nan YANG, Dmitry BELOV