Patents by Inventor A-NAN YANG

A-NAN YANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11664598
    Abstract: The present disclosure includes an omnidirectional dielectric resonator antenna (DRA). The omnidirectional DRA comprises a substrate, a dielectric, and a planar antenna positioned between the substrate and the dielectric. The planar antenna comprises a central planar feed positioned on the substrate. The planar antenna also comprises a plurality of feed lines coupled to, and extending outward from, the central planar feed. The planar antenna also comprises a plurality of arms coupled to the plurality of feed lines. Each arm extends from a corresponding feed line.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: May 30, 2023
    Assignee: CITY UNVIERSITY OF HONG KONG
    Inventors: Kwok Wa Leung, Xi-Yao Liu, Nan Yang
  • Publication number: 20230154849
    Abstract: Various layouts for conductive interconnects in the conductor layers in an integrated circuit are disclosed. Some or all of the conductive interconnects are included in a power delivery system. In general, the conductive interconnects in a first conductor layer are arranged according to an orthogonal layout and the conductive interconnects in a second conductor layer are arranged according to a non-orthogonal layout. Conductive stripes in a transition conductor layer positioned between the first and the second conductor layers electrically connect the conductive interconnects in the first conductor layer to the conductive interconnects in the second conductor layer.
    Type: Application
    Filed: January 18, 2023
    Publication date: May 18, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wan-Yu LO, Chung-Hsing WANG, Chin-Shen LIN, Kuo-Nan YANG, Meng-Xiang LEE, Hao-Tien KAN, Jhih-Hong YE
  • Patent number: 11651136
    Abstract: A method of forming a semiconductor device includes: providing a first circuit having a plurality of circuit cells; analyzing a loading capacitance on a first pin cell connecting a first circuit cell and a second circuit cell in the plurality of circuit cells to determine if the loading capacitance of the first pin cell is larger than a first predetermined capacitance; replacing the first pin cell by a second pin cell for generating a second circuit when the loading capacitance is larger than the first predetermined capacitance, wherein the second pin cell is different from the first pin cell; and generating the semiconductor device according to the second circuit.
    Type: Grant
    Filed: January 5, 2022
    Date of Patent: May 16, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Kuo-Nan Yang, Wan-Yu Lo, Chung-Hsing Wang, Hiranmay Biswas
  • Publication number: 20230121445
    Abstract: The present disclosure provides a routing structure. The routing structure includes a substrate having a boundary and a first conductive trace configured to be coupled to a first conductive pad disposed within the boundary of the substrate. The first conductive trace is inclined with respect to the boundary of the substrate.
    Type: Application
    Filed: December 19, 2022
    Publication date: April 20, 2023
    Inventors: CHIN-SHEN LIN, WAN-YU LO, MENG-XIANG LEE, HAO-TIEN KAN, KUO-NAN YANG, CHUNG-HSING WANG
  • Publication number: 20230121153
    Abstract: An integrated circuit includes a cell layer including a first cell and a second cell, a first metal layer over the cell layer and having a first conductive feature, a second metal layer over the first metal layer and having a second conductive feature, and a first via between the first metal layer and the second metal layer and connecting the first conductive feature to the second conductive feature. The first conductive feature spans over a boundary between the first and second cells, and has a lengthwise direction along a first direction. The second conductive feature spans over the boundary between the first and second cells, and has a lengthwise direction along a second direction that is perpendicular to the first direction.
    Type: Application
    Filed: December 21, 2022
    Publication date: April 20, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Fong-Yuan CHANG, Kuo-Nan YANG, Chung-Hsing WANG, Lee-Chung LU, Sheng-Fong CHEN, Po-Hsiang HUANG, Hiranmay BISWAS, Sheng-Hsiung CHEN, Aftab Alam KHAN
  • Publication number: 20230124119
    Abstract: An integrated circuit includes a gated circuit configured to operate on a first or second voltage, a header circuit, a first power rail and a second power rail on a back-side of a wafer, a third power rail on the back-side of the wafer, and a fourth power rail on a front-side of the wafer. The first and second power rail extend in a first direction, and are separated from each other in a second direction. The third power rail is between the first and second power rail in the second direction. The third power rail is configured to supply the second voltage to the gated circuit. The fourth power rail includes a first set of conductors extending in the second direction. Each of the first set of conductors is configured to supply a third voltage to the header circuit, and is separated from each other in the first direction.
    Type: Application
    Filed: December 14, 2022
    Publication date: April 20, 2023
    Inventors: Kuang-Ching CHANG, Jung-Chan YANG, Hui-Zhong ZHUANG, Chih-Liang CHEN, Kuo-Nan YANG
  • Patent number: 11620030
    Abstract: In non-limiting examples of the present disclosure, systems, methods and devices for executing gesture operations are provided. A touchpad gesture manager and a touchscreen gesture manager may be maintained. Both managers may comprise the identities of gesture operations and conditions for executing the gesture operations. The conditions for one or more touchscreen gesture operations may be the same as the conditions for one or more corresponding touchpad gesture operations. The gestures that have same conditions for the touchscreen and the touchpad may comprise application window operations and virtual desktop transition operations. In some examples, one or more display elements, animations, or intermediate operations may be different in executing the touchscreen operations than for executing the touchpad operations.
    Type: Grant
    Filed: May 4, 2021
    Date of Patent: April 4, 2023
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Elizabeth Picchietti Salowitz, Joseph Spencer King, Nan Yang, Albert Peter Yih, Sharath Viswanathan
  • Publication number: 20230073409
    Abstract: The invention discloses a lithium electrode. The electrically conductive structure layer has a recess with one-side opening, and the lithium metal layer is disposed on the bottom of the recess. The solid electrolyte layer and the electrolyte storage layer are disposed thereon sequentially. When the lithium metal is plated, the plated lithium metal is restricted by the solid electrolyte layer to push and compress the electrolyte storage layer. Therefore, the growth of the lithium dendrites is limited efficiently. The penetration through issue of the lithium dendrites will not be occurred so that the safety of the lithium metal battery is improved greatly.
    Type: Application
    Filed: August 3, 2022
    Publication date: March 9, 2023
    Applicants: PROLOGIUM TECHNOLOGY CO., LTD., Prologium Holding Inc.
    Inventor: Szu-Nan YANG
  • Patent number: 11600568
    Abstract: Various layouts for conductive interconnects in the conductor layers in an integrated circuit are disclosed. Some or all of the conductive interconnects are included in a power delivery system. In general, the conductive interconnects in a first conductor layer are arranged according to an orthogonal layout and the conductive interconnects in a second conductor layer are arranged according to a non-orthogonal layout. Conductive stripes in a transition conductor layer positioned between the first and the second conductor layers electrically connect the conductive interconnects in the first conductor layer to the conductive interconnects in the second conductor layer.
    Type: Grant
    Filed: June 18, 2021
    Date of Patent: March 7, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wan-Yu Lo, Chung-Hsing Wang, Chin-Shen Lin, Kuo-Nan Yang, Meng-Xiang Lee, Hao-Tien Kan, Jhih-Hong Ye
  • Publication number: 20230068280
    Abstract: An IC device includes first and second cells adjacent each other and over a substrate. The first cell includes a first IO pattern along a first track among a plurality of tracks in a first metal layer, the plurality of tracks elongated along a first axis and spaced from each other along a second axis. The second cell includes a plurality of conductive patterns along corresponding different tracks among the plurality of tracks in the first metal layer, each of the plurality of conductive patterns being an IO pattern of the second cell or a floating conductive pattern. The first metal layer further includes a first connecting pattern along the first track and connects the first IO pattern and a second IO pattern of the second cell. The second IO pattern is one of the plurality of conductive patterns of the second cell and is along the first track.
    Type: Application
    Filed: August 31, 2021
    Publication date: March 2, 2023
    Inventors: Cheng-Yu LIN, Jung-Chan YANG, Hui-Zhong ZHUANG, Sheng-Hsiung CHEN, Kuo-Nan YANG, Chih-Liang CHEN, Lee-Chung LU
  • Publication number: 20230068367
    Abstract: This invention provides a thermal runaway suppression element for lithium batteries and the related applications. The thermal runaway suppression element includes a composite salt layer provided by a eutectic mixture containing at least two single inorganic salts. The composite salt layer has a melting point between 90 to 150° C. At least one of the single inorganic salts comprises a cation, which is an amphoteric metal ion or an alkali metal ion. The thermal runaway suppression element is disposed inside or outside the lithium battery. When the temperature of the lithium battery reaches to 90 to 150° C., the composite slat layer will be molten and reacts with the electrochemical reaction system to passivate the active materials and decrease ionic and electronic conductivity. Therefore, the thermal runaway event and its derived problem are efficiently solved.
    Type: Application
    Filed: August 1, 2022
    Publication date: March 2, 2023
    Applicants: PROLOGIUM TECHNOLOGY CO., LTD., Prologium Holding Inc.
    Inventor: Szu-Nan YANG
  • Patent number: 11575158
    Abstract: The invention discloses a recycling method for oxide-based solid electrolyte with original phase, method of fabricating lithium battery and green battery thereof, which is adapted to recycle the solid-state or quasi-solid lithium batteries after discard. The oxide-based solid electrolyte is only used as an ion transport pathway, and does not participate in the insertion and extraction of lithium ions during charge and discharge cycles. Its crystal structure dose not be destroyed. Therefore, the original phase recycle of the oxide-based solid electrolyte is achieved without damage the structure or materials. The recycled the oxide-based solid electrolyte can be re-used to reduce the manufacturing cost of the related lithium battery.
    Type: Grant
    Filed: October 6, 2020
    Date of Patent: February 7, 2023
    Assignees: PROLOGIUM TECHNOLOGY CO., LTD., Prologium Holding Inc.
    Inventor: Szu-Nan Yang
  • Patent number: 11557803
    Abstract: The present disclosure relates to a horizontal composite electricity supply structure, which comprises a first insulation layer, a second insulation layer, two electrically conductive layers, and a plurality of electrochemical system element groups. The two electrically conductive layers are disposed on the first and second insulation layers, respectively. The electrochemical system element groups are disposed between the first insulation layer and the second insulation layer, and connected in series and/or in parallel via the electrically conductive layers. The electrochemical system element group is formed by several serially connected electrochemical system elements. Each electrochemical system element includes a package layer on the sidewall, so that their electrolyte systems do not circulate with one another. Thereby, the high voltage produced by connection will not influence any single electrochemical system element nor decompose their respective electrolyte systems.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: January 17, 2023
    Assignees: PROLOGIUM TECHNOLOGY CO., LTD., PROLOGIUM HOLDING INC.
    Inventor: Szu-Nan Yang
  • Patent number: 11552069
    Abstract: An integrated circuit includes a first, second and third power rail, and a header circuit coupled to a gated circuit. The gated circuit is configured to operate on a first or second voltage. The first and second power rail are on a back-side of a wafer, and extend in a first direction. The header circuit is configured to supply the first voltage to the gated circuit by the first power rail. The second power rail is separated from the first power rail in a second direction. The second power rail is configured to supply the second voltage to the gated circuit. The third power rail is on a front-side of the wafer and includes a first set of conductors extending in the second direction, and separated in the first direction. Each of the first set of conductors is configured to supply a third voltage to the header circuit.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: January 10, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuang-Ching Chang, Jung-Chan Yang, Hui-Zhong Zhuang, Chih-Liang Chen, Kuo-Nan Yang
  • Patent number: 11552068
    Abstract: A method includes forming a cell layer including first and second cells, each of which is configured to perform a circuit function; forming a first metal layer above the cell layer and including a first conductive feature and a second conductive feature extending along a first direction, in which the first conductive feature extends from the first cell into the second cell, and in which a shortest distance between a center line of the first conductive feature and a center line of the second conductive feature along a second direction is less than a width of the first conductive feature, and the second direction is perpendicular to the first direction; forming a first conductive via interconnecting the cell layer and the conductive feature.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: January 10, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Fong-Yuan Chang, Kuo-Nan Yang, Chung-Hsing Wang, Lee-Chung Lu, Sheng-Fong Chen, Po-Hsiang Huang, Hiranmay Biswas, Sheng-Hsiung Chen, Aftab Alam Khan
  • Publication number: 20220406716
    Abstract: Various layouts for conductive interconnects in the conductor layers in an integrated circuit are disclosed. Some or all of the conductive interconnects are included in a power delivery system. In general, the conductive interconnects in a first conductor layer are arranged according to an orthogonal layout and the conductive interconnects in a second conductor layer are arranged according to a non-orthogonal layout. Conductive stripes in a transition conductor layer positioned between the first and the second conductor layers electrically connect the conductive interconnects in the first conductor layer to the conductive interconnects in the second conductor layer.
    Type: Application
    Filed: June 18, 2021
    Publication date: December 22, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wan-Yu LO, Chung-Hsing WANG, Chin-Shen LIN, Kuo-Nan YANG, Meng-Xiang LEE, Hao-Tien KAN, Jhih-Hong YE
  • Patent number: 11532562
    Abstract: The present disclosure provides a routing structure. The routing structure includes a substrate having a first circuit region and a boundary surrounding the first circuit region. The routing structure also includes a first conductive trace coupled to a first conductive pad disposed in the first circuit region. The first conductive trace is inclined with respect to the boundary of the substrate. A method of forming a routing structure is also disclosed.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: December 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chin-Shen Lin, Wan-Yu Lo, Meng-Xiang Lee, Hao-Tien Kan, Kuo-Nan Yang, Chung-Hsing Wang
  • Patent number: 11522225
    Abstract: A horizontal composite electricity supply element group comprises a first insulation layer, a second insulation layer, a first patterned conductive layer, a second patterned conductive layer, and a plurality of electricity supply element groups. The first patterned conductive layer is disposed on the first insulation layer. The second patterned conductive layer is disposed on the second insulation layer. The plurality of electricity supply element groups are disposed between the first insulation layer and the second insulation layer, and connected in series and/or in parallel via the first patterned conductive layer and the second patterned conductive layer. The electricity supply element group is formed by several serially connected independent electricity supply elements whose electrolyte systems do not circulate with one another. Thereby, the high voltage produced by connection will not influence any single electricity supply element nor decompose their respective electrolyte systems.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: December 6, 2022
    Assignees: PROLOGIUM TECHNOLOGY CO., LTD., PROLOGIUM HOLDING INC.
    Inventor: Szu-Nan Yang
  • Publication number: 20220384344
    Abstract: An integrated circuit includes a device, a first interconnect structure disposed above the device and a second interconnect structure positioned below the device. The first interconnect structure includes multiple frontside metal layers. The second interconnect structure includes multiple backside metal layers, where each backside metal layer includes metal conductors routed according to diagonal routing. In some embodiments, a backside interconnect structure can include another backside metal layer that includes metal conductors routed according to mixed-Manhattan-diagonal routing. A variety of techniques can be used to route signals between metal conductors in the backside interconnect structure and cells on one or more frontside metal layers.
    Type: Application
    Filed: May 27, 2021
    Publication date: December 1, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Hsiung Chen, Jerry Chang Jui Kao, Kuo-Nan Yang, Jack Liu
  • Publication number: 20220376359
    Abstract: A composite battery cell includes a plurality of electricity supply elements connected to each other in series/parallel to form the electricity supply element groups. The electricity supply element groups are connected to each other in parallel/series and packed to form the battery cell with high capacity and high voltage. Each electricity supply element is an in-dependent module and the electrolyte system does not circulate therebetween. There only have charges transferred rather than electrochemical reactions between the adjacent electricity supply elements. Therefore, the electrolyte decomposition would not occur result from the high voltage caused by connecting in series. Both series and parallel connection are made within the package of the battery cell to achieve high capacity and high voltage.
    Type: Application
    Filed: August 3, 2022
    Publication date: November 24, 2022
    Applicants: PROLOGIUM TECHNOLOGY CO., LTD., Prologium Holding Inc.
    Inventor: Szu-Nan YANG