Abstract: The scaling of features in ICs has been a driving force behind an ever-growing semiconductor industry. As transistors of the ICs become smaller, their gate lengths become smaller, leading to undesirable short-channel effects such as poor leakage, poor subthreshold swing, drain-induced barrier lowering, etc. Embodiments of the present disclosure are based on recognition that extending at least one of two S/D contacts of a transistor into a channel layer while keeping it separated from a corresponding gate stack by a channel material may allow keeping the footprint of the transistor relatively small while effectively increasing transistor's effective gate length and thus reducing the negative impacts of short-channel effects. This architecture may be optimized even further if transistors are to be operated at relatively low temperatures, e.g., below 200 Kelvin degrees or lower. For multiple transistors, some of the S/D contacts may be shared to further increase transistor density.

Abstract: Thin film tunnel field effect transistors having relatively increased width are described. In an example, integrated circuit structure includes an insulator structure above a substrate. The insulator structure has a topography that varies along a plane parallel with a global plane of the substrate. A channel material layer is on the insulator structure. The channel material layer is conformal with the topography of the insulator structure. A gate electrode is over a channel portion of the channel material layer on the insulator structure. A first conductive contact is over a source portion of the channel material layer on the insulator structure, the source portion having a first conductivity type. A second conductive contact is over a drain portion of the channel material layer on the insulator structure, the drain portion having a second conductivity type opposite the first conductivity type.

Abstract: Methods and systems for organizing medical data. For example, a computer-implemented method includes receiving first data of a first data category, the first data having a first data format; extracting a first plurality of attributes from the first data using a first extractor; mapping the first plurality of attributes to an unified data format using a first mapper; receiving second data of a second data category, the second data having a second data format; extracting a second plurality of attributes from the second data using a second extractor; mapping the second plurality of attributes to the unified data format using a second mapper; and building an ontology for a use case by at least linking the first plurality of attributes and the second plurality of attributes.

Abstract: Disclosed herein are transistor gate-channel arrangements with transistor gate stacks that include dipole layers, and related methods and devices. Transistor gate stacks disclosed herein include a multilayer gate oxide having both a high-k dielectric and a dipole layer. In some embodiments, a thin dipole layer may directly border a channel material of choice and may be between the channel material and the high-k dielectric. In other embodiments, a passivation layer may spontaneously form between the dipole layer and the channel material. In still other embodiments, the high-k dielectric may be between the dipole layer and the channel material. Temporary polarization provided by the dipole layer may increase the effective dielectric constant of the high-k dielectric and may allow to use thinner high-k dielectrics and/or high-k dielectrics of suboptimal quality while maintaining transistor performance in terms of, e.g., gate leakage, carrier mobility, and subthreshold swing.

Abstract: An apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The memory array includes an embedded dynamic random access memory (eDRAM) memory array. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes a switched capacitor circuit. The switched capacitor circuit includes a back-end-of-line (BEOL) capacitor coupled to a thin film transistor within the metal/dielectric layers of the semiconductor chip. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip.

Abstract: Described herein are transistor devices formed using perovskite gate dielectrics. In one example, a transistor includes a high-k perovskite dielectric material between a gate electrode and a thin film semiconductor channel. In another example, four-terminal transistor includes a semiconductor channel, a gate stack that includes a perovskite dielectric layer on one side of the channel, and a body electrode on an opposite side of the channel. The body electrode adjusts a threshold voltage of the transistor.

Abstract: Thin film transistors having U-shaped features are described. In an example, integrated circuit structure including a gate electrode above a substrate, the gate electrode having a trench therein. A channel material layer is over the gate electrode and in the trench, the channel material layer conformal with the trench. A first source or drain contact is coupled to the channel material layer at a first end of the channel material layer outside of the trench. A second source or drain contact is coupled to the channel material layer at a second end of the channel material layer outside of the trench.

Abstract: Described herein are apparatuses, systems, and methods associated with metal-assisted transistors. A single crystal semiconductor material may be seeded from a metal. The single crystal semiconductor material may form a channel region, a source, region, and/or a drain region of the transistor. The metal may form the source contact or drain contact, and the source region, channel region, and drain region may be stacked vertically on the source contact or drain contact. Alternatively, a metal-assisted semiconductor growth process may be used to form a single crystal semiconductor material on a dielectric material adjacent to the metal. The portion of the semiconductor material on the dielectric material may be used to form the transistor. Other embodiments may be described and claimed.

Abstract: A correlation engine and policy manager (CPE) system includes: a persistent database, a cache database, an event gate, an event enricher, an event transformer, and an event dispatcher. The event gate obtains event data from at least one event source, and forwards the event data to the event enricher. The event enricher enriches the event data with additional data in the cached business layer data of the cache database, and forwards the enriched event data to the event transformer. The event transformer applies one or more policies in a cached business layer data of the cache database to the enriched event data to obtain transformed event data, and outputs the transformed event data to be stored in the persistent database. The event dispatcher dispatches output data to cause or prompt an action responsive to the transformed event data satisfying the at least one policy.

Abstract: A computer-implemented method for computing or modeling the risk of a cyber security breach to an asset begins by gathering coverage information from network sensors, endpoint agents, and decoys related to the asset, as well as gathering importance information related to the asset, alerts and anomalies from an enterprise and vulnerability information related to the asset. From this, a threat-score is computed for the asset. Connections or coupling information is gathered between users and assets, users and data, and assets and data, which is fused to generate a 3-dimensional vector representation of coverage, importance, and threat-score of the assets, users and data. From this 3-dimensional vector, an asset risk score is computed to provide the asset risk score.

Abstract: A system includes processing circuitry; and a memory connected to the processing circuitry, wherein the memory is configured to store executable instructions that, when executed by the processing circuitry, facilitate performance of operations, including: receive an event message frame from a data source, wherein the event message frame is generated by one or more state changes within a network operatively connected to the system; correlate one or more business policies based the event message frame; apply the one or more operations to the event message frame based on the one or more business policies to create a transformed event message frame; and route the transformed event message frame to a message queue.

Abstract: Disclosed herein are transistors with ferroelectric gates, and related methods and devices. For example, in some embodiments, a transistor may include a channel material, and a gate stack, and the gate stack may include a gate electrode material and a ferroelectric material between the gate electrode material and the channel material.

Abstract: An apparatus is formed. The apparatus includes a stack of semiconductor chips. The stack of semiconductor chips includes a logic chip and a memory stack, wherein, the logic chip includes at least one of a GPU and CPU. The apparatus also includes a semiconductor chip substrate. The stack of semiconductor chips are mounted on the semiconductor chip substrate. At least one other logic chip is mounted on the semiconductor chip substrate. The semiconductor chip substrate includes wiring to interconnect the stack of semiconductor chips to the at least one other logic chip.

Abstract: A semiconductor device comprising stacked complimentary transistors are described. In some embodiments, the semiconductor device comprises a first device comprising an enhancement mode III-N heterostructure field effect transistor (HFET), and a second device over the first device. In an example, the second device comprises a depletion mode thin film transistor. In an example, a connector is to couple a first terminal of the first device to a first terminal of the second device.

Abstract: Application artifact registration is performed by receiving a bundle service specification configured for deployment of a software service in a cloud native environment, transferring a bundle from an original address indicated in the bundle service specification to an object storage at a principal address, attaching, to the bundle service specification, a bundle identifier and the principal address, extracting a plurality of artifacts from the bundle, each of the plurality of artifacts being stored in the object storage at a subordinate address, and creating one or more artifact service specifications, each artifact service specification representing one or more of the plurality of artifacts, each service specification representing the corresponding subordinate address, an artifact identifier, and an artifact type of each represented artifact.

Abstract: A method includes creating a first package of an application, registering the first package with an orchestrator and triggering deployment of the application on a set of target servers. In response to triggering deployment of the application, the orchestrator obtains client identification of security information for the application, deploys the application on the set of target servers, submits the configuration files to a configuration management tool for configuration, applies the configuration files to perform configuration of the application in the set of target servers, and triggers an observability framework (OBF) tool to start application monitoring in response to at least the orchestrator submitting the monitoring configurations to the OBF tool, and monitors the application in the set of target servers. The first package includes deployment files, security information, management configurations of the application, or monitoring configurations for the OBF tool.

Abstract: A method includes causing a graphical user interface to be output by a display. The graphical user interface is a network service generation template having a first user input field configured to receive a first user input identifying a first parameter associated with a network service, a second user input field configured to receive a second user input identifying a second parameter associated with the network service, and a third user input field configured to receive a third user input identifying the second parameter as fixed or dynamic. The method also includes processing the first user input, the second user input and the third user input to generate a network service descriptor including the first parameter, the second parameter and the third parameter. The method further includes causing the network service descriptor to be stored in a database. The method additionally includes processing an instruction to deploy the network service.

Abstract: A method of visual content communication includes: receiving, multimedia data from a multimedia source; identifying, a first set of pixels from among a plurality of pixels of the multimedia data in a YCbCr color space based on information in the plurality of pixels; selecting, a second set of pixels from among the first set of pixels based on a luminance value and an inter-pixel distance of each pixel of the first set of pixels; generating, metadata for the second set of pixels based on an auxiliary content, wherein the auxiliary content is to be added in the multimedia data; modifying, at least one of a Cb component or a Cr component of the second set of pixels using a modification factor based on the metadata; and transmitting, to an electronic device, the multimedia data in an RGB color space with the modified second set of pixels using visible light communication.

Abstract: Relationship-apparent application artifact registration is performed by attaching, to the bundle service specification, a bundle identifier, the principal address, and an artifact relationship specification, the artifact relationship specification representing, for each of the one or more artifact service specifications, the subordinate address, the artifact identifier, and the artifact type of each represented artifact, and attaching, to each of the one or more artifact service specifications, a bundle relationship specification, the bundle relationship specification representing the bundle identifier and the principal address.

Abstract: An apparatus for automated collision avoidance includes a sensor configured to detect an object of interest, predicting a representation of the object of interest at a future point in time, calculating an indication of a possibility of a collision with the object of interest based on the representation of the object of interest at the future point in time, and executing a collision avoidance action based on the indication.