Abstract: A method includes creating a first package of an application, registering the first package with an orchestrator and triggering deployment of the application on a set of target servers. In response to triggering deployment of the application, the orchestrator obtains client identification of security information for the application, deploys the application on the set of target servers, submits the configuration files to a configuration management tool for configuration, applies the configuration files to perform configuration of the application in the set of target servers, and triggers an observability framework (OBF) tool to start application monitoring in response to at least the orchestrator submitting the monitoring configurations to the OBF tool, and monitors the application in the set of target servers. The first package includes deployment files, security information, management configurations of the application, or monitoring configurations for the OBF tool.

Abstract: A method includes causing a graphical user interface to be output by a display. The graphical user interface is a network service generation template having a first user input field configured to receive a first user input identifying a first parameter associated with a network service, a second user input field configured to receive a second user input identifying a second parameter associated with the network service, and a third user input field configured to receive a third user input identifying the second parameter as fixed or dynamic. The method also includes processing the first user input, the second user input and the third user input to generate a network service descriptor including the first parameter, the second parameter and the third parameter. The method further includes causing the network service descriptor to be stored in a database. The method additionally includes processing an instruction to deploy the network service.

Abstract: A method of visual content communication includes: receiving, multimedia data from a multimedia source; identifying, a first set of pixels from among a plurality of pixels of the multimedia data in a YCbCr color space based on information in the plurality of pixels; selecting, a second set of pixels from among the first set of pixels based on a luminance value and an inter-pixel distance of each pixel of the first set of pixels; generating, metadata for the second set of pixels based on an auxiliary content, wherein the auxiliary content is to be added in the multimedia data; modifying, at least one of a Cb component or a Cr component of the second set of pixels using a modification factor based on the metadata; and transmitting, to an electronic device, the multimedia data in an RGB color space with the modified second set of pixels using visible light communication.

Abstract: Relationship-apparent application artifact registration is performed by attaching, to the bundle service specification, a bundle identifier, the principal address, and an artifact relationship specification, the artifact relationship specification representing, for each of the one or more artifact service specifications, the subordinate address, the artifact identifier, and the artifact type of each represented artifact, and attaching, to each of the one or more artifact service specifications, a bundle relationship specification, the bundle relationship specification representing the bundle identifier and the principal address.

Abstract: An apparatus for automated collision avoidance includes a sensor configured to detect an object of interest, predicting a representation of the object of interest at a future point in time, calculating an indication of a possibility of a collision with the object of interest based on the representation of the object of interest at the future point in time, and executing a collision avoidance action based on the indication.

Abstract: Automatically validating the calibration of an visual sensor network includes acquiring image data from visual sensors that have partially overlapping fields of view, extracting a representation of an environment in which the visual sensors are disposed, calculating one or more geometric relationships between the visual sensors, comparing the calculated one or more geometric relationships with previously obtained calibration information of the visual sensors, and verifying a current calibration of the visual sensors based on the comparison.

Abstract: Described herein are IC devices that include TFT based memory arrays on both sides of a layer of logic devices. An example IC device includes a support structure (e.g., a substrate) on which one or more logic devices may be implemented. The IC device further includes a first memory cell on one side of the support structure, and a second memory cell on the other side of the support structure, where each of the first memory cell and the second memory cell includes a TFT as an access transistor. Providing TFT based memory cells on both sides of a layer of logic devices allows significantly increasing density of memory cells in a memory array having a given footprint area, or, conversely, significantly reducing the footprint area of the memory array with a given memory cell density.

Abstract: A method is described. The method includes forming bit line structures above bitline contact structures, forming a first material on top surfaces and sidewall surfaces of the bit line structures to establish step structures for via formation, and forming a second material on the top surface of the first material. Capacitor landing structures are formed by patterning the second material.

Abstract: An example IC device includes a plurality of vertical transistors which may be part of memory cells, thus realizing vertical-transistor based memory. The IC device further includes a wordline, electrically continuous along a first longitudinal axis and electrically coupled to gates of a first subset of the transistors, and a control line that may be either a bitline or a plateline, electrically continuous along a second longitudinal axis and wrapping around at least portions of channel materials of a second subset of the transistors, where the first subset and the second subset have one transistor in common. At least one of the first longitudinal axis and the second longitudinal axis is not parallel to any edges or borders of the support structure, and, as a result, such a memory is referred to as “diagonal memory.” The transistors may be hysteretic transistors and/or may be further coupled to hysteretic capacitors.

Abstract: An example IC device includes a memory cell having a vertical transistor that includes an opening in an insulator material, where sidewall(s) and the bottom of the opening are lined with a channel material and a gate insulator material. The lined opening is at least partially filled with a gate electrode material so that the gate insulator material is between the channel material and the gate electrode material. The IC device further includes a first control line for the memory cell (e.g., a wordline) coupled to the gate electrode material, and a second control line for the memory cell (e.g., a bitline or a plateline) at least partially wrapping around the sidewall of the opening to electrically couple to the channel material at the sidewall. The vertical transistor may be a hysteretic transistor and/or may be further coupled to a hysteretic capacitor.

Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate, a first inter-level dielectric (ILD) layer above the substrate, and a second ILD layer above the first ILD layer. A first capacitor and a second capacitor are formed within the first ILD layer and the second ILD layer. A first top plate of the first capacitor and a second top plate of the second capacitor are formed at a boundary between the first ILD layer and the second ILD layer. The first capacitor and the second capacitor are separated by a dielectric area in the first ILD layer. The dielectric area includes a first dielectric area that is coplanar with the first top plate or the second top plate, and a second dielectric area above the first dielectric area and to separate the first top plate and the second top plate. Other embodiments may be described and/or claimed.

Abstract: A system includes processing circuitry and a memory connected to the processing circuitry. The memory is configured to store executable instructions that, when executed by the processing circuitry, facilitate performance of operations. The operations include filtering, based upon business logic, business data within a cache database. Converting the filtered business data into a data model. Loading the data model to a persistent cache database. Obtaining event messages from a data source, where the event messages are generated by one or more state changes within a network operatively connected to the system. Obtaining, for an event message, event-related data from the data model, where the event-related data is topologically related to the event message. Combining the event message with the event-related data from the data model. Framing the event message with the event-related data; and route the frame according to a user-defined configuration file.

Abstract: Three-dimensional ferroelectric memory cell architectures are discussed related to improved memory cell performance and density. Such three-dimensional ferroelectric memory cell architectures include groups of vertically stacked transistors accessed by vertical bit lines and horizontal word lines. Groups of such stacks of transistors are arrayed laterally. Adjacent transistor stacks are separated by isolation material or memory structures inclusive of capacitor structures or plate line structures.

Abstract: A method includes receiving registration information of an application, extracting resource requirements of the application from the registration information, storing the extracted resource requirements and an identifier of the application in a service catalog, and receiving, from one or more users, a first instruction corresponding to the identifier of the application. In response to the first instruction, application resource requirements are retrieved from the service catalog based on the identifier, the application resource requirements being a portion or all of the extracted resource requirements, a resource manager analyzes a server cluster database based on the application resource requirements and generates a list of server clusters matched to the application resource requirements, and the list of server clusters is output to the one or more users.

Abstract: Embodiments of systems and methods of configuring a cluster of servers is disclosed. In one embodiment of a method, an orchestrator application registers a cluster of servers. The orchestrator application installs a monitoring agent on the cluster of servers with application, wherein the orchestrator application is configured to generate agent configuration data in response to installing the monitoring agent. In response to installing the monitoring agent, the agent configuration data is sent to a cluster monitoring application. The cluster monitoring application configures, the monitoring agent to transmit cluster operation data to the cluster monitoring application based on the sent agent configuration data.

Abstract: An application programming interface (API) server for a correlation engine and policy manager (CPE) system includes a processor, and a memory coupled to the processor. The CPE system includes a plurality of components of various component types, and each component among the plurality of components is configured to perform at least one corresponding processing on event data input to the CPE system. The memory is configured to store executable instructions that, when executed by the processor, cause the processor to perform at least one of registering, removing or updating a configuration of at least one component among the plurality of components of the CPE system, or changing a number of components of a same component type among the various component types, to scale up or down the CPE system.

Abstract: Memory device architectures including integrated high voltage planar transistor support circuitry underlying memory cell arrays are discussed related to improving density and device performance Such memory device architectures include planar transistors having wide band gap channel materials integrated with memory cell arrays using a number of metallization layers. The metallization layers between the planar transistors and the memory cells are predominantly tungsten and the metallization layers in which the memory cells are embedded are predominantly a metal other than tungsten.

Abstract: Memory device architectures including integrated static random access memory based tag circuitry and dynamic random access memory cells are discussed related to improving density and device performance Such memory device architectures include vertically aligned dynamic random access memory cells and memory tag circuitry aligned and implemented within the same monolithic integrated circuit die or on stacked interconnected monolithic integrated circuit dies.

Abstract: A system includes processing circuitry and a memory connected to the processing circuitry. The memory is configured to store executable instructions that, when executed by the processing circuitry, cause the processing circuitry to startup a configuration parser module and an invoke worker module. To obtain a configuration file from a database where the configuration file specifies configuration information for constructing a pluggable event gate that includes a data adaptor for an online source, a data adaptor for an offline source, a data adaptor sink. To construct one or more event gates based on the configuration file. The configuration file further specifies one or more user-defined data sources and one or more user-defined data sinks. To create, responsive to a number of the user-defined data sources and a number of user-defined data sinks, multiprocessing workers located on one or more cores of a network and share data between the multiprocessing workers.

Abstract: Embodiments herein describe techniques for a semiconductor device including a capacitor and a transistor above the capacitor. A contact electrode may be shared between the capacitor and the transistor. The capacitor includes a first plate above a substrate, and the shared contact electrode above the first plate and separated from the first plate by a capacitor dielectric layer, where the shared contact electrode acts as a second plate for the capacitor. The transistor includes a gate electrode above the substrate and above the capacitor; a channel layer separated from the gate electrode by a gate dielectric layer, and in contact with the shared contact electrode; and a source electrode above the channel layer, separated from the gate electrode by the gate dielectric layer, and in contact with the channel layer. The shared contact electrode acts as a drain electrode of the transistor. Other embodiments may be described and/or claimed.