Abstract: A computer includes a processor and a memory storing instructions executable by the processor to identify a virtual boundary between a host roadway lane of a host vehicle and a target roadway lane of a target vehicle, the virtual boundary based on a predicted path of the target vehicle, determine a first constraint value based on a boundary approach velocity of the target vehicle, determine a second constraint value based on (1) a boundary approach velocity of the host vehicle and (2) a boundary approach acceleration of the host vehicle and perform a threat assessment of a collision between the host vehicle and the target vehicle upon determining that the first constraint value violates a first threshold or the second constraint value violates a second threshold.

Abstract: Various arrangements for IC devices implementing memory with one access transistor for multiple hysteretic capacitors are disclosed. An example IC device includes a memory array of M memory units, where each memory unit includes an access transistor and N hysteretic capacitors coupled to the access transistor in a way that allows selecting all of the N hysteretic capacitors for performing READ and/or WRITEs operation when the access transistor is ON. The IC device further includes W wordlines, B bitlines, and P platelines, where N, M, W, B, and P are design variables, each being an integer greater than 1. IC devices implementing memory with one access transistor for multiple hysteretic capacitors as described herein may be used to address the scaling challenges of conventional 1T-1C memory technology and enable high density embedded memory compatible with advanced CMOS processes.

Abstract: Three-dimensional hysteretic memory based on semiconductor nanoribbons is disclosed. An example memory cell may include a nanoribbon-based access transistor and a capacitor coupled to the access transistor, where the capacitor at least partially wraps around the nanoribbon in which the access transistor is formed. One or both of a gate stack of the access transistor and the capacitor insulator may include a hysteretic material/arrangement. Plurality of such memory cells may be provided in a single nanoribbon, and the nanoribbon may be one of a stack of nanoribbons provided above one another over a support structure. Incorporating hysteretic memory cells in different layers above a support structure by using stacks of semiconductor nanoribbons may allow significantly increasing density of hysteretic memory cells in a memory array having a given footprint area, or conversely, significantly reducing the footprint area of the memory array with a given density of hysteretic memory cells.

Abstract: A memory structure includes conductive lines extending horizontally in a spaced apart fashion within a vertical stack above a base or substrate. The vertical stack includes a plurality of conductive lines, the first and second conductive lines being part of the plurality. A gate structure extends vertically through the first and second conductive lines. The gate structure includes a body of semiconductor material and a dielectric, where the dielectric is between the body and the conductive lines. An isolation material is on at least one side of the vertical stack and in contact with the conductive lines. The vertical stack defines a void located vertically between at the first and second conductive lines in the vertical stack and laterally between the gate structure and the isolation material. The void may extend along a substantial length (e.g., 20 nm or more) of the first and second conductive lines.

Abstract: A genus of proteolysis-targeting chimeras (PROTACs)-type compounds/antiestrogens has now been found that act as selective estrogen receptor degraders (SERDs) and estrogen receptor antagonists by degrading and antagonizing ERa in breast cancer cells. The compounds are of the following genus: The compounds described herein exhibit anti-proliferative effects, and are potentially useful, alone or in combination with other therapies, for the treatment of breast cancer. In general, these compounds combine a tight binding ERa targeting ligand tethered to a recognition motif or degron. Once bound, the degron recruits destructive cellular components and the targeted receptor (i.e., ERa) is degraded (i.e., destroyed) or antagonized.

Abstract: Integrated circuits including selectable vias are disclosed. The techniques are particularly well-suited to back end of line (BEOL) processes. In accordance with some embodiments, a selectable via includes a vertically-oriented thin film transistor structure having a wrap around gate, which can be used to effectively select (or deselect) the selectable via ad hoc. When a selectable via is selected, a signal is allowed to pass through the selectable via. Conversely, when the selectable via is not selected, a signal is not allowed to pass through the selectable via. The selectable characteristic of the selectable via allows multiple vias to share a global interconnect. The global interconnect can be connected to any number of selectable vias, as well as standard vias.

Abstract: A method for converting speech in one of a plurality of input languages into text using machine transliteration and transfer learning is disclosed. The method includes a training stage. The training stage includes receiving a training set of a plurality of audio files and an input text corresponding to the audio input in any input language using the speech recognition engine; transliterating the training set to transform the input text into transliterated text that includes characters of a base language and training acoustic model with the plurality of audio files and corresponding transliterated text using transfer learning. The method further includes an inference stage. The inference stage includes performing decoding on output of the trained acoustic model to generate text includes characters of the base language at inference and transliterating the generated text to output text includes characters in input language using reverse transliteration.

Abstract: Described herein are two transistor (2T) memory cells that use TFTs as access and gain transistors. When one or both transistors of a 2T memory cell are implemented as TFTs, these transistors may be provided in different layers above a substrate, enabling a stacked architecture. An example 2T memory cell includes an access TFT provided in a first layer over a substrate, and a gain TFT provided in a second layer over the substrate, the first layer being between the substrate and the second layer (i.e., the gain TFT is stacked in a layer above the access TFT). Stacked TFT based 2T memory cells allow increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.

Abstract: The shape and/or location of an organ may change in accordance with changes in the body shape and/or pose of a patient. Described herein are systems, methods, and instrumentalities for automatically determining, using an artificial neural network (ANN), the shape and/or location of the organ based on human models that reflect the body shape and/or pose the patient. The ANN may be trained to learn the spatial relationship between the organ and the body shape or pose of the patient. Then, at an inference time, the ANN may be used to determine the relationship based on a first patient model and a first representation (e.g., a point cloud) of the organ so that given a second patient model thereafter, the ANN may automatically determine the shape and/or location of the organ corresponding to the body shape or pose of the patient indicated by the second patient model.

Abstract: An embodiment includes an apparatus comprising: a substrate; a thin film transistor (TFT) comprising: source, drain, and gate contacts; a semiconductor material, comprising a channel, between the substrate and the gate contact; a gate dielectric layer between the gate contact and the channel; and an additional layer between the channel and the substrate; wherein (a)(i) the channel includes carriers selected from the group consisting of hole carriers or electron carriers, (a)(ii) the additional layer includes an insulator material that includes charged particles having a polarity equal to a polarity of the carriers. Other embodiments are described herein.

Abstract: A thin film transistor (TFT) apparatus is disclosed, where the apparatus includes a gate comprising metal, a source and a drain, a semiconductor body, and two or more dielectric structures between the gate and the semiconductor body. In an example, the two or more dielectric structures may include at least a first dielectric structure having a first bandgap and a second dielectric structure having a second bandgap. The first bandgap may be different from the second bandgap. The TFT apparatus may be a back-gated TFT apparatus where the source is at least in part coplanar with the drain, and the gate is non-coplanar with the source and the drain.

Abstract: Embodiments herein describe techniques for a semiconductor device including a semiconductor substrate, a first device of a first wafer, and a second device at back end of a second wafer, where the first device is bonded with the second device. A first metal electrode of the first device within a first dielectric layer is coupled to an n-type oxide TFT having a channel layer that includes an oxide semiconductor material. A second metal electrode of the second device within a second dielectric layer is coupled to p-type organic TFT having a channel layer that includes an organic material. The first dielectric layer is bonded to the second dielectric layer, and the first metal electrode is bonded to the second metal electrode. The n-type oxide TFT and the p-type organic TFT form a symmetrical pair of transistors of a CMOS circuit. Other embodiments may be described and/or claimed.

Abstract: A system for detecting a road surface includes a processor and a memory. The memory stores instructions executable by the processor to determine a virtual boundary for a vehicle body based on a shape of the vehicle body, to identify one or more objects based on vehicle sensor data, based on the identified one or more objects, the determined virtual boundary, and an input to at least one of propulsion, steering, or braking, to determine at least one of a braking override or a steering override, and based on the determination, to perform at least one of adjusting a vehicle steering and a vehicle speed.

Abstract: A system for detecting a road surface includes a computer programmed to determine a virtual boundary for a vehicle body based on a shape of the vehicle body, upon identifying an object, to identify a plurality of points on the object based on received sensor data, to determine a barrier function based on each of the identified plurality of points, wherein the barrier function includes a barrier distance from a reference point of the virtual boundary of the vehicle to a respective one of the points on the object, based on (i) the determined barrier functions, (ii) the determined virtual boundary of the vehicle, and (iii) an input to at least one of propulsion, steering, or braking, to determine at least one of a braking override or a steering override, and based on the determination, to adjust at least one of a vehicle steering or a vehicle speed.

Abstract: Automated patient positioning and modelling includes a hardware processor to obtain image data from an imaging sensor, classify the image data, using a first machine learning model, as a patient pose based on one or more pre-defined protocols for patient positioning, provide a confidence score based on the classification of the image data and if the confidence score is less than a pre-determined value, re-classify the image data using a second machine learning model; or if the confidence score is greater than a pre-determined value, identify the image data as corresponding to a patient pose based on one or more pre-defined protocols for patient positioning during a scan procedure.

Abstract: Embodiments include a transistor device that comprises a gate electrode and a gate dielectric surrounding the gate electrode. In an embodiment, a source region may be below the gate electrode and a drain region may be above the gate electrode. In an embodiment, a channel region may be between the source region and the drain region. In an embodiment, the channel region is separated from a sidewall of the gate electrode by the gate dielectric. In an embodiment, a capacitor may be electrically coupled to the drain region.

Abstract: Provided is a method, performed by an information processing device, of processing information by using an Internet of things (IoT) device, the method including: receiving, from a user, a web search query; fetching context information of at least one IoT device related to the web search query; automatically generating a synthetic web search query including the web search query and the context information of the at least one IoT device; and determining a control to be applied to the at least one IoT device by using a search result regarding the synthetic web search query.

Abstract: A stacked-substrate advanced encryption standard (AES) integrated circuit device is described in which at least some circuits associated logic functions (e.g., AES encryption operations, memory cell access and control) are provided on a first substrate. Memory arrays used with the AES integrated circuit device (sometimes referred to as “embedded memory”) are provided on a second substrate stacked on the first substrate, thus forming a AES integrated circuit device on a stacked-substrate assembly. Vias are fabricated to pass through the second substrate, into a dielectric layer between the first substrate and the second substrate, and electrically connect to conductive interconnections of the AES logic circuits.

Abstract: Embodiments herein describe techniques for a semiconductor device having an interconnect structure including an inter-level dielectric (ILD) layer between a first layer and a second layer of the interconnect structure. The interconnect structure further includes a separation layer within the ILD layer. The ILD layer includes a first area with a first height to extend from a first surface of the ILD layer to a second surface of the ILD layer. The ILD layer further includes a second area with a second height to extend from the first surface of the ILD layer to a surface of the separation layer, where the first height is larger than the second height. Other embodiments may be described and/or claimed.

Abstract: A technique implements a dataflow graph, taking a number of streams of data inputs and transforms these inputs into a number of streams of outputs. The dataflow graph can perform pattern matching. The technique implements reactions via the composition of pattern matching across joined streams of input data. A completeness of matching an input sequence to a particular input pattern can be characterized as having at least three different degrees, such as cold (not yet matched), warm (e.g., minimally matched), and hot (e.g., maximally matched). The input pattern to be matched can have a variable length, including zero length or unlimited or arbitrarily large length. Data flows can be on a push basis or pull basis, or a combination, and may change depending on the state.