Patents by Inventor Abhishek Anil Sharma

Abhishek Anil Sharma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240008285
    Abstract: Bits are stored in an array with multiple capacitors sharing a single access transistor and a common plate coupled to the transistor. A single common select transistor accesses information stored in an array of capacitors, above and below the transistor and sharing a common plate. The common plate may be vertical and encircled by each of the other plates. The capacitors may be ferroelectric capacitors. In an integrated circuit system, the array may be coupled to a power supply and a cooling structure.
    Type: Application
    Filed: July 1, 2022
    Publication date: January 4, 2024
    Applicant: Intel Corporation
    Inventors: Abhishek Anil Sharma, Anand Murthy, Wilfred Gomes, Tahir Ghani
  • Publication number: 20240006412
    Abstract: Structures having recessed channel transistors are described. In an example, an integrated circuit structure includes a channel structure having a recess extending partially there through. A gate dielectric layer is on a bottom and along sides of the recess, the gate dielectric layer laterally surrounded by the channel structure. A gate electrode is on and laterally surrounded by the gate dielectric layer. The gate electrode has an uppermost surface below and uppermost surface of the channel structure.
    Type: Application
    Filed: June 30, 2022
    Publication date: January 4, 2024
    Inventors: Abhishek Anil SHARMA, Tahir GHANI, Anand S. MURTHY, Rishabh MEHANDRU, Cory WEBER, Sagar SUTHRAM, Pushkar RANADE, Wilfred GOMES
  • Publication number: 20240006483
    Abstract: Structures having raised epitaxy on channel structure transistors are described. In an example, an integrated circuit structure includes a channel structure having multi-layer epitaxial source or drain structures thereon, the multi-layer epitaxial source or drain structures having a recess extending there through. A gate dielectric layer is on a bottom and along sides of the recess and laterally surrounded by the epitaxial source or drain structures. A gate electrode is on and laterally surrounded by the gate dielectric layer. The gate electrode has an uppermost surface below an uppermost surface of the gate dielectric layer.
    Type: Application
    Filed: June 30, 2022
    Publication date: January 4, 2024
    Inventors: Abhishek Anil SHARMA, Tahir GHANI, Rishabh MEHANDRU, Anand S. MURTHY, Wilfred GOMES, Cory WEBER, Sagar SUTHRAM
  • Publication number: 20240008253
    Abstract: Structures having memory access transistors with backside contacts are described. In an example, an integrated circuit structure includes a front-side structure including a device layer having a fin-based transistor, and a capacitor structure above the fin-based transistor of the device layer. A backside structure is below the front-side structure. The backside structure includes a conductive contact electrically connected to the fin-based transistor of the device layer.
    Type: Application
    Filed: June 30, 2022
    Publication date: January 4, 2024
    Inventors: Abhishek Anil SHARMA, Tahir GHANI, Anand S. MURTHY, Wilfred GOMES, Cory WEBER, Rishabh MEHANDRU, Sagar SUTHRAM, Pushkar RANADE
  • Publication number: 20240008291
    Abstract: Bits are stored in an array with multiple capacitors per access transistor. An array of multiple ferroelectric capacitors shares a nanowire or nanosheet as a common plate and stores information accessed by a single common select transistor, which uses the nanowire or nanosheet for its channel. In an integrated circuit (IC) system, a group of bitlines is connected to a capacitor array by arrays of nanowires or nanosheets and wordline-controlled non-planar transistors. An IC die with a capacitor array accessed by a single select transistor and sharing a nanowire or nanosheet is coupled to a power supply and a cooling structure.
    Type: Application
    Filed: July 1, 2022
    Publication date: January 4, 2024
    Applicant: Intel Corporation
    Inventors: Abhishek Anil Sharma, Tahir Ghani, Anand Murthy, Wilfred Gomes
  • Publication number: 20240008286
    Abstract: Bits are stored in an array with multiple storage elements sharing a single access transistor and a storage line coupled to the transistor. A single common select transistor accesses information stored in an array of storage elements. Other arrays of storage elements on parallel storage lines can be coupled into a crosspoint array by source lines orthogonal to the storage lines. The storage elements may be non-volatile. In an integrated circuit system, the array may be coupled to a power supply and a cooling structure.
    Type: Application
    Filed: July 1, 2022
    Publication date: January 4, 2024
    Applicant: Intel Corporation
    Inventors: Abhishek Anil Sharma, Wilfred Gomes, Anand Murthy, Sagar Suthram, Tahir Ghani
  • Publication number: 20240006305
    Abstract: Structures having airgaps for backside signal routing or power delivery are described. In an example, an integrated circuit structure includes a front-side structure including a device layer having a plurality of nanowire-based transistors, and a plurality of metallization layers above the nanowire-based transistors of the device layer. A backside structure is below the nanowire-based transistors of the device layer. The backside structure includes a first conductive line laterally spaced apart from a second conductive line by an air gap.
    Type: Application
    Filed: June 30, 2022
    Publication date: January 4, 2024
    Inventors: Abhishek Anil SHARMA, Sagar SUTHRAM, Pushkar RANADE, Anand S. MURTHY, Tahir GHANI, Rishabh MEHANDRU, Cory WEBER
  • Publication number: 20240006416
    Abstract: Structures having ultra-high conductivity global routing are described. In an example, an integrated circuit structure includes a device layer having a plurality of transistors. A plurality of metallization layers is above the plurality of transistors of the device layer. One or more of the metal layers includes a material having a critical temperature greater than 10 Kelvin and less than 300 Kelvin.
    Type: Application
    Filed: June 30, 2022
    Publication date: January 4, 2024
    Inventors: Abhishek Anil SHARMA, Tahir GHANI, Anand S. MURTHY, Sagar SUTHRAM, Pushkar RANADE, Wilfred GOMES, Rishabh MEHANDRU, Cory WEBER
  • Publication number: 20240008239
    Abstract: Stacked static random-access memory (SRAM) circuits have doubled word length for a given SRAM cell area. An integrated circuit (IC) die includes stacked SRAM cells in vertically adjacent device layers with access transistors connected to a common wordline. The IC die with stacked SRAM cells having a common word line may be attached to a substrate and coupled to a power supply and, advantageously, to an active-cooling structure. SRAM cells may be formed in vertically adjacent layers of a substrate and electrically connected at their access transistor gate electrodes.
    Type: Application
    Filed: July 1, 2022
    Publication date: January 4, 2024
    Applicant: Intel Corporation
    Inventors: Abhishek Anil Sharma, Wilfred Gomes, Tahir Ghani, Anand Murthy, Rajabali Koduri, Clifford Ong, Sagar Suthram
  • Publication number: 20240008244
    Abstract: Bits are stored in cells having two transistors between two parallel bitlines. In a memory array, first and second transistor channels in a bit cell are parallel and offset and coupled to first and second bitlines, respectively, which are also parallel and offset. Adjacent bit cells share corresponding transistor channel structures. The transistor channels may be orthogonal to the bitlines. The memory array may be on an integrated circuit (IC) die, which may be coupled to a power supply in an IC system. In an IC system, the memory array may be coupled to a power supply and a cooling structure.
    Type: Application
    Filed: July 1, 2022
    Publication date: January 4, 2024
    Applicant: Intel Corporation
    Inventors: Abhishek Anil Sharma, Sagar Suthram, Wilfred Gomes, Anand Murthy, Tahir Ghani
  • Publication number: 20240006317
    Abstract: Structures having vertical keeper or power gate for backside power delivery are described. In an example, an integrated circuit structure includes a front-side structure including a device layer having a plurality of fin-based transistors, and a plurality of metallization layers above the fin-based transistors of the device layer. A backside structure is below the fin-based transistors of the device layer. The backside structure includes a ground metal line. One or more vertical gate all-around transistors is between the fin-based transistors of the device layer and the ground metal line of the backside structure.
    Type: Application
    Filed: June 30, 2022
    Publication date: January 4, 2024
    Inventors: Abhishek Anil SHARMA, Tahir GHANI, Anand S. MURTHY, Cory WEBER, Rishabh MEHANDRU, Wilfred GOMES, Sagar SUTHRAM
  • Publication number: 20240006531
    Abstract: Structures having vertical transistors are described. In an example, an integrated circuit structure includes a channel structure on a drain contact layer, the channel structure having an opening extending there through. A gate dielectric layer is on a bottom and along sides of the opening, the gate dielectric layer laterally surrounded by the channel structure. A gate electrode is on and laterally surrounded by the gate dielectric layer. A source contact layer is on sides of a portion of the gate dielectric layer extending above the channel structure.
    Type: Application
    Filed: June 30, 2022
    Publication date: January 4, 2024
    Inventors: Abhishek Anil SHARMA, Rishabh MEHANDRU, Sagar SUTHRAM, Cory WEBER, Tahir GHANI, Anand S. MURTHY, Pushkar RANADE, Wilfred GOMES
  • Publication number: 20230420533
    Abstract: Structures having AOI gates with routing across nanowires are described. In an example, an integrated circuit structure includes a stack of horizontal nanowires along a vertical direction. A gate stack is over the stack of horizontal nanowires and is surrounding a channel region of each of the horizontal nanowires, the gate stack having one or more cuts in the vertical direction.
    Type: Application
    Filed: June 28, 2022
    Publication date: December 28, 2023
    Inventors: Abhishek Anil SHARMA, Wilfred GOMES, Anand S. MURTHY, Tahir GHANI, Sagar SUTHRAM
  • Publication number: 20230418508
    Abstract: In one embodiment, an apparatus comprises: a plurality of banks to store data; and a plurality of interconnects, each of the plurality of interconnects to couple a pair of the plurality of banks. In response to a data movement command, a first bank of the plurality of banks is to send data directly to a second bank of the plurality of banks via a first interconnect of the plurality of interconnects. Other embodiments are described and claimed.
    Type: Application
    Filed: June 27, 2022
    Publication date: December 28, 2023
    Inventors: Abhishek Anil Sharma, Pushkar Ranade, Sagar Suthram, Wilfred Gomes, Rajabali Koduri
  • Publication number: 20230418604
    Abstract: In one embodiment, a memory includes a die having: one or more memory layers having a plurality of banks to store data; and at least one other layer comprising at least one reconfigurable vector processor, the at least one reconfigurable vector processor to perform a vector computation on input vector data obtained from at least one bank of the plurality of banks and provide processed vector data to the at least one bank. Other embodiments are described and claimed.
    Type: Application
    Filed: June 27, 2022
    Publication date: December 28, 2023
    Inventors: Abhishek Anil Sharma, Pushkar Ranade, Wilfred Gomes, Sagar Suthram
  • Publication number: 20230422485
    Abstract: Structures having memory with backside DRAM and power delivery are described. In an example, an integrated circuit structure includes a front-side structure including a device layer having a plurality of nanowire-based transistors, and a plurality of metallization layers above the nanowire-based transistors of the device layer. A backside structure is below the nanowire-based transistors of the device layer. The backside structure includes a plurality of dynamic random access memory (DRAM) devices.
    Type: Application
    Filed: June 28, 2022
    Publication date: December 28, 2023
    Inventors: Abhishek Anil SHARMA, Sagar SUTHRAM, Wilfred GOMES, Tahir GHANI, Rishabh MEHANDRU, Cory WEBER, Anand S. MURTHY
  • Publication number: 20230420368
    Abstract: Structures having memory with backside power delivery are described. In an example, an integrated circuit structure includes a front-side structure including a device layer having a plurality of nanowire-based transistors, and a plurality of metallization layers above the nanowire-based transistors of the device layer. One of the metal layers includes an array of uninterrupted signal lines. A backside structure is below the nanowire-based transistors of the device layer. The backside structure includes a ground metal line.
    Type: Application
    Filed: June 28, 2022
    Publication date: December 28, 2023
    Inventors: Abhishek Anil SHARMA, Wilfred GOMES
  • Publication number: 20230422462
    Abstract: Structures having inverters with contacts between nanowires are described. In an example, an integrated circuit structure includes a stack of horizontal nanowires along a vertical direction. A conductive contact is laterally adjacent to a source or drain region of the stack of horizontal nanowires, the conductive contact having a cut in the vertical direction. A gate stack is over the stack of horizontal nanowires and surrounding a channel region of each of the horizontal nanowires, the gate stack laterally spaced apart from the conductive contact.
    Type: Application
    Filed: June 28, 2022
    Publication date: December 28, 2023
    Inventors: Abhishek Anil SHARMA, Wilfred GOMES
  • Patent number: 11830788
    Abstract: An example relates to an integrated circuit including a semiconductor substrate, and a wiring layer stack located on the semiconductor substrate. The integrated circuit further includes a transistor embedded in the wiring layer stack. The transistor includes an embedded layer. The embedded layer has a thickness of less than 10 nm. The embedded layer includes at least one two-dimensional crystalline layer including more than 10% metal atoms. Further examples relate to methods for forming integrated circuits.
    Type: Grant
    Filed: May 25, 2021
    Date of Patent: November 28, 2023
    Assignee: Intel Corporation
    Inventors: Carl Naylor, Ashish Agrawal, Urusa Alaan, Christopher Jezewski, Mauro Kobrinsky, Kevin Lin, Abhishek Anil Sharma
  • Publication number: 20230369501
    Abstract: Techniques are provided herein for forming transistor devices with reduced parasitic capacitance, such as transistors used in a memory structure. In an example, a given memory structure includes memory cells, with a given memory cell having an access device and a storage device. The access device may include, for example, a thin film transistor (TFT), and the storage device may include a capacitor. Any of the given TFTs may include a dielectric liner extending along sidewalls of the TFT. The TFT includes a recess (e.g., a dimple) that extends laterally inwards toward a midpoint of a semiconductor region of the TFT. The dielectric liner thus also pinches or otherwise extends inward. This pinched-in dielectric liner may reduce parasitic capacitance between the contacts of the TFT and the gate electrode of the TFT. The pinched-in dielectric liner may also protect the contacts from forming too deep into the semiconductor region.
    Type: Application
    Filed: May 12, 2022
    Publication date: November 16, 2023
    Applicant: Intel Corporation
    Inventors: Cheng Tan, Yu-Wen Huang, Hui-Min Chuang, Xiaojun Weng, Nikhil J. Mehta, Allen B. Gardiner, Shu Zhou, Timothy Jen, Abhishek Anil Sharma, Van H. Le, Travis W. Lajoie, Bernhard Sell