Abstract: Stitched dies having double interconnects are described. For example, an integrated circuit structure includes a first die including a first device layer, a first plurality of metallization layers over the first device layer, and a first conductive interconnection over the first plurality of metallization layers. The integrated circuit structure also includes a second die separated from the first die by a scribe region, the second die including a second device layer, a second plurality of metallization layers over the second device layer, and a second conductive interconnection over the second plurality of metallization layers. The second conductive interconnection extends over the scribe region and is coupled to the first conductive interconnection.

Abstract: Structures having bit-cost scaling with relaxed transistor area are described. In an example, an integrated circuit structure includes a plurality of plate lines along a first direction. A transistor is beneath the plurality of plate lines, with a direction of a first source or drain to a gate to a second source or drain of the transistor being a second direction orthogonal to the first direction. A plurality of capacitor structures is over the plurality of plate lines, individual ones of the plurality of capacitor structures coupled to a corresponding one of the plurality of plate lines. The plurality of capacitor structures has a staggered arrangement from a plan view perspective.

Abstract: In embodiments herein, an integrated circuit device includes a logic die with processor circuitry and a memory die coupled to the logic die. The memory die includes a first memory module comprising a first memory bank and first control circuitry, a second memory module comprising a second memory bank and second control circuitry, and a scribe line on a surface of the memory die between the first memory module and the second memory module. The first memory module is not electrically connected to the second memory module, and each memory module include through silicon vias (TSVs) to electrically connect a top side of the memory module and a bottom side of the memory module (e.g., for three-dimensional stacking in the integrated circuit device).

Abstract: Structures having lookup table decoders for FPGAs with high DRAM transistor density are described. In an example, an integrated circuit structure includes a plurality of fins or nanowire stacks, individual ones of the plurality of fins or nanowire stacks having a longest dimension along a first direction. A plurality of gate structures is over the plurality of fins or nanowire stacks, individual ones of the plurality of gate structures having a longest dimension along a second direction, wherein the first direction is non-orthogonal to the second direction.

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for fabricating semiconductor packages that include DRAM using wide band gap materials, such as SiC or GaN to reduce transistor leakage. In addition, transistors may be fabricated adding one or more extra layers between a source and a drain of a transistor and the contact of the source of the drain to increase the effective electrical gate length of the transistor to further reduce leakage. In addition, for these transistors, a thickness of the body below the gate may be made narrow to improve gate control. Other embodiments may be described and/or claimed.

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for fabricating semiconductor packages that use a SiC layer that is coupled with another layer that includes another material. The SiC layer may be an active layer that includes devices, such as transistors, that are coupled with devices that may be in the other layer. The SiC layer may be coupled with the other layer using fusion bonding, hybrid bonding, layer transfer, and/or bump and island formation techniques. Other embodiments may be described and/or claimed.

Abstract: Structures having layer select transistors for shared peripherals in memory are described. In an example, an integrated circuit structure includes a memory structure layer including a capacitor array coupled to a plurality of plate lines. A memory transistor layer is beneath the memory structure layer, the memory transistor layer including front end transistors coupled to corresponding capacitors of the capacitor array of the memory structure layer. A select transistor layer is over the memory structure layer, the select transistor layer including backend transistors having a channel composition different than the front end transistors. One or more of the backend transistors is coupled to one or more of the plurality of plate lines of the memory structure layer.

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for designing and fabricating semiconductor packages that include transistors that include wide band gap materials, such as silicon carbide or gallium nitride. Other embodiments may be described and/or claimed.

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for semiconductor packages that use devices within an SiC layer coupled with devices within a GaN layer proximate to the SiC to convert a high voltage source to the package, e.g. greater than 1 kV, to 1-1.8 V used by components within the package. The devices may be transistors. The voltage conversion will allow increased power to be supplied to the package. Other embodiments may be described and/or claimed.

Abstract: Structures having vertical shared gate high-drive thin film transistors are described. In an example, an integrated circuit structure includes a stack of alternating dielectric layers and metal layers. A trench is through the stack of alternating dielectric layers and metal layers. A semiconductor channel layer is along sides of the trench. A gate dielectric layer is along sides the semiconductor channel layer in the trench. A gate electrode is within sides of the gate dielectric layer.

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for fabricating semiconductor packages that use high voltage transistors within a SiC layer that are coupled with one or more transistors in one or more other layers in a cascode format in order to switch the high voltage transistors in the SiC layer using low voltages. Other embodiments may be described and/or claimed.

Abstract: Structures having two-transistor gain cell are described. In an example, an integrated circuit structure includes a frontend device layer including a read transistor. A backend device layer is above the frontend device layer, the backend device layer including a write transistor. An intervening interconnect layer is between the backend device layer and the frontend device layer, the intervening interconnect layer coupling the write transistor of the backend device layer to the read transistor of the front-end device layer.

Abstract: Structures having routing across layers of channel structures are described. In an example, an integrated circuit structure includes a first stack of horizontal nanowires along a vertical direction. A second stack of horizontal nanowires is along the vertical direction, the second stack of horizontal nanowires beneath the first stack of horizontal nanowires. A conductive routing layer extends laterally between the first stack of horizontal nanowires and the second stack of horizontal nanowires.

Abstract: Structures having two-level memory are described. In an example, an integrated circuit structure includes an SRAM layer including transistors. A DRAM layer is vertically spaced apart from the transistors of the SRAM layer. A metallization structure is between the transistors of the SRAM layer and the DRAM layer.

Abstract: Structures having backside power delivery and signal routing for front side DRAM are described. In an example, an integrated circuit structure includes a front side structure including a dynamic random access memory (DRAM) layer having one or more capacitors over one or more transistors, and a plurality of metallization layers above the DRAM layer. A backside structure is below and coupled to the transistors of the DRAM layer, the backside structure including metal lines for power delivery and signal routing to the one or more transistors of the DRAM layer.

Abstract: Structures having backside capacitors are described. In an example, an integrated circuit structure includes a front side structure including a device layer having a plurality of select transistors, a plurality of metallization layers above the plurality of select transistors, and a plurality of vias below and coupled to the plurality of select transistors. A backside structure is below the plurality of vias of the device layer. The backside structure includes a memory layer coupled to the plurality of select transistors by the plurality of vias.

Abstract: Embodiments disclosed herein include an integrated circuit structure. In an embodiment, the integrated circuit structure comprises an interlayer dielectric (ILD). and an interconnect over the ILD. In an embodiment, the interconnect comprises a plurality of first layers, where the first layers comprise a metal, and a plurality of second layer in an alternating pattern with the plurality of first layers. In an embodiment, the second layers comprise a two-dimensional (2D) material.

Abstract: Embodiments disclosed herein include an integrated circuit structure. In an embodiment, the integrated circuit structure comprises an interlayer dielectric (ILD), and an opening in the ILD. In an embodiment, a first layer lines the opening, and a second layer lines the first layer. In an embodiment, the second layer comprises a semi-metal or transition metal dichalcogenide (TMD). The integrated circuit structure may further comprise a third layer over the second layer.

Abstract: An embodiment of an integrated circuit (IC) device may include a plurality of layers of wide bandgap (WBG)-based circuitry and a plurality of layers of silicon (Si)-based circuitry monolithically bonded to the plurality of layers of WBG-based circuitry, with one or more electrical connections between respective WBG-based circuits in the plurality of layers of WBG-based circuitry and Si-based circuits in the plurality of layers of Si-based circuitry. In some embodiments, a wafer-scale WBG-based IC is hybrid bonded or layer transfer bonded to a wafer-scale Si-based IC. Other embodiments are disclosed and claimed.

Abstract: An embodiment of a capacitor in the back-side layers of an IC die may comprise any type of solid-state electrolyte material disposed between electrodes of the capacitor. Another embodiment of a capacitor anywhere in an IC die may include one or more materials selected from the group of indium oxide, indium nitride, gallium oxide, gallium nitride, zinc oxide, zinc nitride, tungsten oxide, tungsten nitride, tin oxide, tin nitride, nickel oxide, nickel nitride, niobium oxide, niobium nitride, cobalt oxide, and cobalt nitride between electrodes of the capacitor. Other embodiments are disclosed and claimed.