Abstract: Stacked static random-access memory (SRAM) circuits have doubled word length for a given SRAM cell area. An integrated circuit (IC) die includes stacked SRAM cells in vertically adjacent device layers with access transistors connected to a common wordline. The IC die with stacked SRAM cells having a common word line may be attached to a substrate and coupled to a power supply and, advantageously, to an active-cooling structure. SRAM cells may be formed in vertically adjacent layers of a substrate and electrically connected at their access transistor gate electrodes.

Abstract: Structures having ultra-high conductivity global routing are described. In an example, an integrated circuit structure includes a device layer having a plurality of transistors. A plurality of metallization layers is above the plurality of transistors of the device layer. One or more of the metal layers includes a material having a critical temperature greater than 10 Kelvin and less than 300 Kelvin.

Abstract: Structures having vertical keeper or power gate for backside power delivery are described. In an example, an integrated circuit structure includes a front-side structure including a device layer having a plurality of fin-based transistors, and a plurality of metallization layers above the fin-based transistors of the device layer. A backside structure is below the fin-based transistors of the device layer. The backside structure includes a ground metal line. One or more vertical gate all-around transistors is between the fin-based transistors of the device layer and the ground metal line of the backside structure.

Abstract: Bits are stored in cells having two transistors between two parallel bitlines. In a memory array, first and second transistor channels in a bit cell are parallel and offset and coupled to first and second bitlines, respectively, which are also parallel and offset. Adjacent bit cells share corresponding transistor channel structures. The transistor channels may be orthogonal to the bitlines. The memory array may be on an integrated circuit (IC) die, which may be coupled to a power supply in an IC system. In an IC system, the memory array may be coupled to a power supply and a cooling structure.

Abstract: Structures having vertical transistors are described. In an example, an integrated circuit structure includes a channel structure on a drain contact layer, the channel structure having an opening extending there through. A gate dielectric layer is on a bottom and along sides of the opening, the gate dielectric layer laterally surrounded by the channel structure. A gate electrode is on and laterally surrounded by the gate dielectric layer. A source contact layer is on sides of a portion of the gate dielectric layer extending above the channel structure.

Abstract: Structures having AOI gates with routing across nanowires are described. In an example, an integrated circuit structure includes a stack of horizontal nanowires along a vertical direction. A gate stack is over the stack of horizontal nanowires and is surrounding a channel region of each of the horizontal nanowires, the gate stack having one or more cuts in the vertical direction.

Abstract: In one embodiment, a memory includes a die having: one or more memory layers having a plurality of banks to store data; and at least one other layer comprising at least one reconfigurable vector processor, the at least one reconfigurable vector processor to perform a vector computation on input vector data obtained from at least one bank of the plurality of banks and provide processed vector data to the at least one bank. Other embodiments are described and claimed.

Abstract: In one embodiment, an apparatus comprises: a plurality of banks to store data; and a plurality of interconnects, each of the plurality of interconnects to couple a pair of the plurality of banks. In response to a data movement command, a first bank of the plurality of banks is to send data directly to a second bank of the plurality of banks via a first interconnect of the plurality of interconnects. Other embodiments are described and claimed.

Abstract: Structures having memory with backside power delivery are described. In an example, an integrated circuit structure includes a front-side structure including a device layer having a plurality of nanowire-based transistors, and a plurality of metallization layers above the nanowire-based transistors of the device layer. One of the metal layers includes an array of uninterrupted signal lines. A backside structure is below the nanowire-based transistors of the device layer. The backside structure includes a ground metal line.

Abstract: Structures having memory with backside DRAM and power delivery are described. In an example, an integrated circuit structure includes a front-side structure including a device layer having a plurality of nanowire-based transistors, and a plurality of metallization layers above the nanowire-based transistors of the device layer. A backside structure is below the nanowire-based transistors of the device layer. The backside structure includes a plurality of dynamic random access memory (DRAM) devices.

Abstract: Structures having inverters with contacts between nanowires are described. In an example, an integrated circuit structure includes a stack of horizontal nanowires along a vertical direction. A conductive contact is laterally adjacent to a source or drain region of the stack of horizontal nanowires, the conductive contact having a cut in the vertical direction. A gate stack is over the stack of horizontal nanowires and surrounding a channel region of each of the horizontal nanowires, the gate stack laterally spaced apart from the conductive contact.

Abstract: An example relates to an integrated circuit including a semiconductor substrate, and a wiring layer stack located on the semiconductor substrate. The integrated circuit further includes a transistor embedded in the wiring layer stack. The transistor includes an embedded layer. The embedded layer has a thickness of less than 10 nm. The embedded layer includes at least one two-dimensional crystalline layer including more than 10% metal atoms. Further examples relate to methods for forming integrated circuits.

Abstract: Techniques are provided herein for forming transistor devices with reduced parasitic capacitance, such as transistors used in a memory structure. In an example, a given memory structure includes memory cells, with a given memory cell having an access device and a storage device. The access device may include, for example, a thin film transistor (TFT), and the storage device may include a capacitor. Any of the given TFTs may include a dielectric liner extending along sidewalls of the TFT. The TFT includes a recess (e.g., a dimple) that extends laterally inwards toward a midpoint of a semiconductor region of the TFT. The dielectric liner thus also pinches or otherwise extends inward. This pinched-in dielectric liner may reduce parasitic capacitance between the contacts of the TFT and the gate electrode of the TFT. The pinched-in dielectric liner may also protect the contacts from forming too deep into the semiconductor region.

Abstract: Techniques are provided herein for forming thin film transistor structures having a multilayer and/or concentration gradient gate dielectric. Such a gate dielectric can be used, to tune the performance and/or reliability of the transistor. According to some such embodiments, memory structures having thin film transistor (TFT) structures are arranged in a two-dimensional array within one or more interconnect layers and stacked in a vertical direction such that multiple tiers of memory structure arrays are formed within the interconnect region. Any of the given TFT structures may include a multilayer and/or graded gate dielectric that includes at least two or more different dielectric layers and/or a material concentration gradient through a thickness of the gate dielectric.

Abstract: Techniques are provided herein for forming thin film transistor (TFT) structures having one or more doped contact regions. The addition of certain dopants can be used to increase conductivity and provide higher thermal stability in the contact regions of the TFT. Memory structures having TFT structures are arranged in a two-dimensional array within one or more interconnect layers and stacked in a vertical direction such that multiple tiers of memory structure arrays are formed within the interconnect region. Any of the TFT structures within the memory structures may include one or more contacts that are doped with additional elements. The doping profile of the contacts can be tuned to optimize performance, stability, and reliability of the TFT structure. Furthermore, additional doping may be performed within the area beneath the contacts and extending into the semiconductor region.

Abstract: Techniques are provided herein for forming multi-tier memory structures with graded characteristics across different tiers. A given memory structure includes memory cells, with a given memory cell having an access device and a storage device. The access device may include, for example, a thin film transistor (TFT) structure, and the storage device may include a capacitor. Certain geometric or material parameters of the memory structures can be altered in a graded fashion across any number of tiers to compensate for process effects that occur when fabricating a given tier, which also affect any lower tiers. This may be done to more closely match the performance of the memory arrays across each of the tiers.

Abstract: Techniques for forming thin film transistors (TFTs) having multilayer and/or concentration gradient semiconductor regions. An example integrated circuit includes a gate electrode, a gate dielectric on the gate electrode, and a semiconductor region on the gate dielectric. In some cases, the semiconductor region includes a plurality of compositionally different material layers, at least two layers of the different material layers each being a semiconductor layer. In some other cases, the semiconductor region includes a single layer having a material concentration gradient extending from a bottom surface of the single layer (adjacent to the gate dielectric) to a top surface of the single layer. The integrated circuit further includes first and second conductive contacts that each contact a respective portion of the semiconductor region.

Abstract: Techniques for forming thin film transistors (TFTs) having multilayer contact structures. An example integrated circuit includes a gate electrode, a gate dielectric on the gate electrode, a semiconductor region on the gate dielectric, and a conductive contact that contacts at least a portion of the semiconductor region. In some other cases, the conductive contact comprises a multilayer structure having at least a first material layer on the at least a portion of the semiconductor region, at least a second material layer on the first material layer, and a conductive fill material over the first and second material layers. In some other cases, the conductive contact comprises a multilayer structure having (1) a graded material layer on the at least a portion of the semiconductor region and (2) a conductive fill material over the graded material layer, wherein the graded material layer comprises a concentration gradient of a given element.

Abstract: Techniques are provided herein for forming thin film transistor structures having co-doped semiconductor regions. The addition of insulating dopants can be used to improve the performance, stability, and reliability of the TFT. A given TFT structure within an array of similar TFT structures formed in an interconnect region may include a semiconductor region that is co-doped with one or more additional elements. The doping profile can be tuned to optimize performance, stability, and reliability of the TFT structure. In some embodiments, the doping profile causes an overall reduction in the conductivity of the semiconductor region, leading to a higher threshold voltage. Designing access devices (in, for example, a DRAM architecture) with higher threshold voltages can be beneficial for improving reliability of the memory cell.

Abstract: Techniques are provided for making asymmetric contacts to improve the performance of thin film transistors (TFT) structures. The asymmetry may be with respect to the area of contact interface with the semiconductor region and/or the depth to which the contacts extend into the semiconductor region. According to some embodiments, the TFT structures are used in memory structures arranged in a two-dimensional array within one or more interconnect layers and stacked in a vertical direction such that multiple tiers of memory structure arrays are formed within the interconnect region. Any of the given TFT structures may include asymmetric contacts, such as two contacts that each have a different contact area to a semiconductor region, and/or that extend to different depths within the semiconductor region. The degree of asymmetry may be tuned during fabrication to modulate certain transistor parameters such as, for example, leakage, capacitance, gate control, channel length, or contact resistance.