Abstract: Techniques are provided herein for forming thin film transistor structures having a laterally recessed gate electrode. The gate electrode may be recessed such that it does not extend under one or both conductive contacts of the transistor. Recessing the lateral dimensions of the gate electrode can reduce gate leakage current and parasitic capacitance. According to an example, a given memory structure generally includes memory cells, with each memory cell having an access device and a storage device. According to some such embodiments, the memory cells are arranged in a two-dimensional array within one or more interconnect layers and stacked in a vertical direction such that multiple tiers of memory cell arrays are formed within the interconnect region. Any of the given TFT structures may include a gate electrode that is laterally recessed such that one or more of the contacts are not directly over the gate electrode.

Abstract: Methods and apparatus to implement an integrated circuit to operate based on data access characteristics. In one embodiment, the integrated circuit comprises a first array comprising a first plurality of memory cells, a second array comprising a second plurality of memory cells, both first and second arrays to store data of a processor, the second plurality of memory cells implementing a selector transistor of a memory cell within using a thin-film transistor (TFT), and a memory control circuit to write a first set of bits to the first array and a second set of bits to the second array upon determining the first set of bits is to be accessed more frequently than the second set of bits.

Abstract: An integrated circuit includes a first layer, and a second layer above the first layer. A third layer is between a first section of the first layer and a first section of the second layer. A fourth layer is laterally adjacent to the third layer, the fourth layer between a second section of the first layer and a second section of the second layer. In an example, a first dielectric material of the third layer is different (e.g., one or both of compositionally different and structurally different) from a second dielectric material of the fourth layer. In an example, the third and fourth layers are etch stop layers. In some cases, the third and fourth layers are coplanar with each other with respect to their top surfaces, or their bottom surfaces, or both their top and bottom surfaces.

Abstract: Method and apparatus to implement an integrated circuit (IC) device to perform compression/decompression operations. In one embodiment, the IC device includes a memory array containing a plurality of memory cells to store data and compression/decompression circuitry to perform compression operations on data to be written to the memory array and decompression operations on data read from the memory array. The memory array and the compression/decompression circuitry are integrated in a same die but at different die depth. At least a portion of the memory array overlaps a portion of the compression/decompression circuitry in a same x-y plane.

Abstract: Integrated circuit (IC) including transistors with high-mobility/high-saturation velocity, non-silicon channel materials coupled to a silicon substrate through counter-doped sub-channel materials, which greatly reduce electrical leakage currents through the substrate when the IC is operated at very low temperatures (e.g., below ?25 C). With low temperature operation, high transistor performance associated with the non-silicon channel materials can be integrated into high density IC architectures that avoid the limitations associated with semiconductor material layer transfers.

Abstract: Thermoelectric (TE) devices and their manufacture on integrated circuit (IC) dies to improve thermal performance. An IC die may include a substrate with transistors on one side, a heat spreader on a second side, and a TE device between them. The TE device may have TE elements with similar dimensions as transistor features. An IC die with transistor circuitry blocks in multiple areas of an IC die may include TE devices between each of the transistor circuitry blocks and a heat spreader.

Abstract: Method and apparatus to implement an integrated circuit (IC) device to perform homomorphic computing. In one embodiment, the IC device includes a memory array containing a plurality of memory cells to store data and compute circuitry to perform computations on encrypted data stored in the memory array. The memory array and the compute circuitry are integrated in a same die but at different die depth. At least a portion of the memory array overlaps a portion of the compute circuitry in a same x-y plane.

Abstract: In one embodiment, a memory comprises: a first subarray having a first plurality of memory cells, the first subarray having a first orientation; and a second subarray having a second plurality of memory cells, the second subarray having a second orientation, the second orientation orthogonal to the first orientation. Other embodiments are described and claimed.

Abstract: Integrated circuits including static random-access memory (SRAM) bit-cells that are actively cooled to a low temperature (e.g., in the cryogenic range) where transistor drive currents become significantly increased and transistor leakage currents significantly reduced. With the drive current improvement, bit-cell capacitance may be reduced by defining narrower transistor fin structures and/or four transistor (4T) bit-cells may be implemented, for example with two parallel transistor fins and colinear gate electrodes.

Abstract: In one embodiment, an integrated circuit package includes: a first die having a plurality of cores, each of the plurality of cores having a local memory interface circuit to access a local portion of a dynamic random access memory (DRAM); and a second die comprising the DRAM, where at least some of the plurality of cores are directly coupled to a corresponding local portion of the DRAM by a stacking of the first die and the second die. Other embodiments are described and claimed.

Abstract: Integrated circuit interconnect structures including an interconnect metallization feature comprising a sidewall reacted with a chalcogen into a low resistance liner. A portion of a backbone material or a metal seed layer may be advantageously converted into a metal chalcogenide, which can lower scattering resistance of an interconnect feature relative to alternative diffusion barrier materials, such a tantalum. Scattering resistance of such metal chalcogenide liner materials may be further reduced by actively cooling an IC, for example to cryogenic temperatures.

Abstract: Systems and techniques related to narrow interconnects for integrated circuits. An integrated circuit die includes narrow interconnect lines with a relatively high pitch. A system includes an integrated circuit die with narrow interconnect lines and cooling structure to lower an operating temperature of at least the interconnects to a point where conductance of the narrow interconnect is sufficient.

Abstract: Narrow-channel, non-planar transistors and their manufacture on integrated circuit dies. A method includes forming channel portions of transistors from sidewall spacers by removing backbone features and coupling a gate structure, a source, and a drain to the channel portions. An integrated circuit die includes a gate structure, a source, and a drain coupled to pair-symmetric channel portions with sidewalls of differing heights. A method includes iteratively etching away portions of semiconductor material not covered by a mask or a passivation layer, revealing a channel portion by removing the mask and passivation layer, and coupling a gate structure, a source, and a drain to the channel portion. An integrated circuit die includes a gate structure, a source, and a drain coupled to a channel portion with vertically alternating, greater and lesser widths.

Abstract: In one embodiment, an apparatus includes: at least one core to execute operations on data; a cryptographic circuit to perform cryptographic operations; a static random access memory (SRAM) coupled to the at least one core; and a ferroelectric memory coupled to the at least one core. In response to a read request, the SRAM is to provide an encryption key to the cryptographic circuit and the ferroelectric memory is to provide encrypted data to the cryptographic circuit, the encryption key associated with the encrypted data. Other embodiments are described and claimed.

Abstract: Integrated circuit (IC) including domino logic circuit blocks with nFETs that are implemented in a first device layer and pFET keeper transistors that are implemented in a second device layer. The multiple device layers may be integrated within an IC die through layer transfer. Very low temperature operation (e.g., ?25° C., or less) may greatly reduce electrical leakage current from dynamic nodes of the domino logic circuit blocks so that output capacitance of the keeper transistors is sufficient to maintain dynamic node charge levels for good noise margin.

Abstract: In one embodiment, an apparatus includes a first die adapted on a second die. The first die may have a plurality of cores, each of the plurality of cores associated with a first plurality of through silicon vias (TSVs), and the second die may have dynamic random access memory (DRAM). The DRAM of the second die may have a plurality of local portions, each of the plurality of local portions associated with a second plurality of TSVs, where each of at least some of the plurality of cores are directly coupled to a corresponding local portion of the DRAM by the corresponding first and second plurality of TSVs. Other embodiments are described and claimed.

Abstract: Methods and apparatus to implement an integrated circuit including both dynamic random-access memory (DRAM) and static random-access memory (SRAM). In one embodiment, the integrated circuit comprises a static random-access memory (SRAM) device to store a first portion of data of a processor, a dynamic random-access memory (DRAM) device to store a second portion of the data of the processor, and a memory control circuit to read from both the SRAM and DRAM devices, a first set of bits of a first word to be read from the SRAM device and a second set of bits of the first word to be read from the DRAM device.

Abstract: Techniques are provided herein for forming backend memory structures with airgaps in an interconnect region above semiconductor devices. The airgaps may be provided between conductive features, such as wordlines, to reduce parasitic capacitance. An interconnect region above a plurality of semiconductor devices includes any number of interconnect layers. A first interconnect layer includes first conductive layers (e.g., wordlines) extending in a first direction with airgaps between adjacent first conductive layers. A second interconnect layer over the first interconnect layer includes at least portions of memory cells over corresponding first conductive layers. A third interconnect layer over the second interconnect layer includes a second conductive layer (e.g., bitline) extending in a second direction over one or more of the at least portions of memory cells.

Abstract: An integrated circuit includes a first conductive structure, a second conductive structure, and a first spacer and a second spacer each comprising a first dielectric material. The integrated circuit further includes a layer comprising a second dielectric material that is compositionally different from the first dielectric material. The integrated circuit further includes a first interconnect feature above and at least partially landed on the first conductive structure. In an example, the first interconnect feature is laterally between the first spacer and the second spacer. The integrated circuit further includes a second interconnect feature above and at least partially landed on the second conductive structure. In an example, the second interconnect feature is laterally between the second spacer and the layer comprising the second dielectric material.

Abstract: An integrated circuit (IC) includes a first memory cell and a second memory cell. The first memory cell includes (i) a first transistor and (ii) a first capacitor coupled to the first transistor, where an upper electrode of the first capacitor is coupled to a first conductive structure. The second memory cell is above the first memory cell. The second memory cell includes (i) a second transistor and (ii) a second capacitor coupled to the second transistor. An upper electrode of the second capacitor is coupled to a second conductive structure. In an example, an interconnect feature includes a continuous and monolithic body of conductive material. In an example, the continuous and monolithic body extends through the second conductive structure, and further extends through the first conductive structure. In an example, the first and second memory cells are dynamic random access memory (DRAM) memory cells.