Abstract: A search engine selects initial coefficients for a receive equalizer. The search engine may be incorporated into a communication receiver that includes a decision feedback equalizer and clock and data recovery circuit. Here, the search engine may initialize various adaptation loops that may control the operation of, for example, a decision feedback equalizer, a clock and data recovery circuit and a continuous time filter. The receiver may include an analog-to-digital converter that is used to generate soft decision data for some of the adaptation loops.

Abstract: Equalization is provided in a high speed communication receiver that includes in various aspects an automatic gain control input stage, a decision feedback equalizer, a clock and data recovery circuit and equalization control circuits. The automatic gain control stage may include a continuous time filter with an adjustable bandwidth. A threshold adjust signal may be applied to the output of the automatic gain control stage. The equalization control circuits may be implemented in the digital domain and operate at a lower clock speed than the data path.

Abstract: Low power high-speed output driver. An array of switches (some of which are inverting switches whose connectivity is governed oppositely as the control signal provided to it) is implemented such that an input signal governs the connectivity of those switches. A resistor is coupled between the nodes interposed between the switches of the array, and an output signal is taken from the nodes at ends of the resistor. The high voltage level of such an output driver is truly the level of the power supply energizing the circuit (e.g., VDD) while still consuming relatively low power.

Abstract: High-resolution low-interconnect phase rotator. A signal may be generated having any desired phase (as determined by the step size employed). First and second control signals select a sector (e.g., the range from 0° to 360° is divided into a number of sectors) and a particular phase within that sector. Generally, this range from 0° to 360° is uniformly divided so that each sector is the same. However, if desired, there can alternatively be differences in the sizes of each of the sectors. The use of these two sets of controls signals (one for selecting the sector and one for selecting the particular phase within the sector) allows for very few control signals. N-channel metal oxide semiconductor field-effect transistor (N-MOSFET) based switches and differential pairs of transistors or alternatively p-channel metal oxide semiconductor field-effect transistor (P-MOSFET) based switches and differential pairs of transistors can be employed.

Abstract: Embodiments include a system for performing dispersion compensation on an electromagnetic signal received over a communication channel, the electromagnetic signal bearing information at a symbol rate. An interleaved analog to digital converter (“ADC”) block may be used, wherein the interleaved ADC block may be configured to generate a plurality of digitally sampled signals from the electromagnetic signal. An interleaved equalizer block may be configured to digitally process each of the digitally sampled signals generated by the ADC block to generate a plurality of digitally equalized signals. A multiplexer may be configured to aggregate the digitally equalized signals into a composite output signal.

Abstract: Embodiments include a system for performing dispersion compensation on an electromagnetic signal received over a communication channel, the electromagnetic signal bearing information at a symbol rate. An interleaved analog to digital converter (“ADC”) block may be used, wherein the interleaved ADC block may be configured to generate a plurality of digitally sampled signals from the electromagnetic signal. An interleaved equalizer block may be configured to digitally process each of the digitally sampled signals generated by the ADC block to generate a plurality of digitally equalized signals. A multiplexer may be configured to aggregate the digitally equalized signals into a composite output signal.

Abstract: A communication system having a transmitter transmits an information signal over a communication media and a receiver coupled to the communication media receives the transmitted information signal. The receiver includes a continuous time filter having an adjustable bandwidth for linearly equalizing the transmitted information signal as a function of the adjustable bandwidth. A decision feedback equalizer coupled to the continuous time filter then reduces inter-symbol interference in the filtered information signal.

Abstract: Embodiments of threshold adjustment circuits are disclosed. An example circuit includes a first differential pair of first and second thin oxide transistors. The first and second thin oxide transistors decrease a DC voltage component of a first and/or second component of an input signal of the circuit. The example circuit further includes a second differential pair of third and fourth thin oxide transistors. The second and third thin oxide transistors increase a DC voltage component of the first and/or the second component of the input signal. The example circuit also includes a power supply that provides a supply voltage to the circuit, the power supply having a voltage level above a reliability level of the thin oxide transistors. In the example circuit, each of the differential pair thin oxide transistors is switched by a signal that keeps each of the first, second, third, and fourth thin oxide transistors operating in saturation.

Abstract: A variable gain amplifier including a stage. The stage having a set of switchable differential pairs. The stage providing a gain range to a signal and adjusting a gain of the signal. At least one differential pair in each stage is permanently enabled. The variable gain amplifier may include a plurality of cascaded stages including the stage. In addition, the variable gain amplifier may be adjusted through an interleaved thermometer coding method.

Abstract: A method and apparatus for an automatic gain control (AGC) loop that utilizes multiple comparators to provide constant bandwidth tracking and step response, as well as fine granularity for decision directed convergence. In one embodiment, an odd number of comparators is used with square-law scaling at the output to achieve constant bandwidth step response for a wide range of input amplitude changes.

Abstract: A method for communicating data includes equalizing received data to reduce channel related distortion in the received data. A clock having frequency and/or phase fixed relative to the equalized data is extracted from the equalized data. The extracted clock is used to clock a retimer to generate recovered data.

Abstract: A variable gain amplifier including a stage. The stage having a set of switchable differential pairs. The stage providing a gain range to a signal and adjusting a gain of the signal. At least one differential pair in each stage is permanently enabled. The variable gain amplifier may include a plurality of cascaded stages including the stage. In addition, the variable gain amplifier may be adjusted through an interleaved thermometer coding method.

Abstract: An equalizer is disclosed that compensates for non-linear effects resulting from a transmitter, a receiver, and/or a communication channel in a communication system. A non-linear decision feedback equalizer compensates for the non-linear effects impressed onto a received symbol by selecting between equalization coefficients based upon a previous received symbol. The received symbol may be represented in form of logic signals based on the binary number system. The two symbols most commonly chosen to represent the two logic values taken on by binary symbols are binary zero and binary one. When the previous received symbol is a binary zero, the non-linear decision feedback equalizer selects an equalization coefficient corresponding to binary zero to compensate for the non-linear effects impressed onto the received symbol.

Abstract: Methods, systems, and apparatuses for calibration of analog to digital converters (ADC) are described herein. In an aspect, an ADC includes a plurality of slices. Each slice includes a digital to analog converter (DAC), a comparator, and a digital processing unit (DPU). The digital processing unit is electrically connected to the comparator and the DAC. In another aspect, an analog-to-digital converter includes an input module and an analog to digital converter core configured to receive an analog input from the input module and generate a digital output. The ADC is configured to adjust a precision of the analog to digital converter core based on a quality of the analog input signal.

Abstract: Multiple channel synchronized clock generation scheme. A novel approach is presented herein in which synchronized clock signals are generated that can be used in parallel processing of deserialized signals. When a serial input signal is received, it can be deserialized into a plurality of parallel signals, and each of these parallel signals can be processed at a frequency that is lower than the frequency of the serial signal. Overall, the frequency at which all of the parallel signals are processed can be the same or substantially close to the frequency of the serial signal, so that throughput within a communication system is not compromised or undesirably reduced. This novel approach is operable to perform independent adjustment of the operational parameters within an apparatus that is operable to perform multiple channel synchronized clock generation (e.g., phase rotation and/or division of signals within each of the individual channels can be adjusted independently).

Abstract: A closed-loop circuitry includes, in part, a loop filter and a current source/sink coupled to the loop filter to adjust the phase/frequency of the signal generated by the closed-loop circuitry. Because the voltage generated by the loop filter has a relatively low frequency, the current source/sink is operable at a relatively low frequency. Each current source and current sink may be a current digital-to-analog (DAC). The amount of current sourced into or sunk out of the loop filter by the current DAC is varied by setting the associated bits of a multi-bit signal. If the closed-loop circuitry is differential, a current source is coupled to the loop filter adapted to receive the differentially high signal, and a current source is coupled to the loop filter adapted to receive the differentially low signal.

Abstract: A method and apparatus for an automatic gain control circuit (AGC) that utilizes freezing and unfreezing states. A freezing process moves the AGC into a TRANSITION state from a NORMAL state, based on net change of VGA gain control codes over a monitoring time window. The freezing process then moves the AGC into a FROZEN state from the TRANSITION state, based on net change of VGA gain control codes over the monitoring time window. An unfreezing process moves the AGC into the NORMAL state from the FROZEN state, based on signal amplitude changes at the output of the VGA or other parameters of the VGA.

Abstract: Present herein is a multirate transceiver wherein data can be received at a first data rate and transmitted at a second data rate. The transceiver device comprises a first interface for receiving data at one data rate a mapper that can map data from a first rate to the second rate, and a second interface for transmitting the data at the second data rate.

Abstract: Embodiments include a system for performing dispersion compensation on an electromagnetic signal received over a communication channel, the electromagnetic signal bearing information at a symbol rate. An interleaved analog to digital converter (“ADC”) block may be used, wherein the interleaved ADC block may be configured to generate a plurality of digitally sampled signals from the electromagnetic signal. An interleaved equalizer block may be configured to digitally process each of the digitally sampled signals generated by the ADC block to generate a plurality of digitally equalized signals. A multiplexer may be configured to aggregate the digitally equalized signals into a composite output signal.

Abstract: Embodiments include a system for performing dispersion compensation on an electromagnetic signal received over a communication channel, the electromagnetic signal bearing information at a symbol rate. An interleaved analog to digital converter (“ADC”) block may be used, wherein the interleaved ADC block may be configured to generate a plurality of digitally sampled signals from the electromagnetic signal. An interleaved equalizer block may be configured to digitally process each of the digitally sampled signals generated by the ADC block to generate a plurality of digitally equalized signals. A multiplexer may be configured to aggregate the digitally equalized signals into a composite output signal.