Abstract: A converter circuit is disclosed. The converter circuit includes a controller configured to operate a pull up component and a pull down component so as to deliver power to a load through an inductor. The controller is configured to operate in either of first and second operational modes based on average current delivered to the load. The converter circuit also includes a mode control circuit configured to change operational modes in response to an indication of current flowing from the inductor to the switch node, and in response to an indication that the average current delivered to the load is greater than the current threshold.

Abstract: A DLL circuit that has a programmable output frequency is provided. In various embodiments, the DLL circuit comprises an input configured to receive an input clock defining an input clock period; an output configured to provide a DLL output clock; a delay line configured to receive the input clock, wherein the delay line comprises a plurality of delay stages, each configured to generate one of a plurality of delay line output clocks, each of the delay line output clocks having a phase relative to the input clock based on a delay of the delay line; a clock generation circuit, configured to generate the DLL output clock based on a selected plurality of the delay line output clocks; and a control circuit configured to select which of the delay line output clocks the clock generation circuit uses to generate the DLL output clock.

Abstract: A DLL circuit that has a programmable output frequency is provided. The DLL circuit uses a single delay line to produce the multiple frequencies. In various embodiments, the delay line is configured to receive an input clock defining an input clock period. The delay line comprises delay stages, each configured to generate a corresponding output clock having a phase relative to the input clock based on a delay of the delay line. In those embodiments, a control circuit is configured to change the delay of the delay line so as to cause a phase difference between the input clock and a sensed output clock to be substantially equal to the input clock period. An edge combiner is configured to generate a DLL output clock based on the output clocks of the delay stages and presents an equal schematic load for each of the output clocks of the delay stages.

Abstract: A receiver circuit is disclosed. The receiver circuit includes an amplifier configured to generate an RF signal based on a received signal, where the RF signal includes an information signal and a blocker signal modulating an RF carrier frequency. The receiver circuit also includes an RF filter connected to the amplifier, where the RF filter is configured to selectively attenuate the blocker signal.

Abstract: A receiver circuit is disclosed. The receiver circuit includes an amplifier having an input terminal, where the amplifier is configured to generate an RF signal based on a signal received at the input terminal, where the RF signal includes an information signal and a blocker signal modulating an RF carrier frequency. The receiver circuit also includes a mixer configured to receive the RF signal and to downconvert the RF signal to generate a baseband signal, where the baseband signal includes the information signal and the blocker signal modulating a baseband carrier frequency, where the baseband carrier frequency is less than the RF carrier frequency, and where the mixer is further configured to selectively attenuate the blocker signal.

Abstract: A converter circuit includes a pull up component, a pull down component, and a controller configured to operate the pull up component and the pull down component so as to deliver power to a load. The controller is configured to operate the pull up and pull down components in first and second operational modes, based on an average current delivered to the load. The converter circuit also includes a mode control circuit to generate a mode control signal based in part on a representation of a peak current received at the switch node from the pull up component.

Abstract: An analog to digital converter (ADC) is disclosed. The ADC includes a DAC which generates a first signal based on an analog input and a digital input word, and a comparator which generates a comparator output having a value corresponding with a sign of a difference between first and second signals. During a first time period, the second signal is equal to a reference signal, the first signal is equal to an analog input, and the comparator generates a first comparator output. During a second time period, the second signal is equal to the reference signal, the first signal is equal to a the analog input plus a predetermined signal, and the comparator generates a second comparator output. A SAR logic circuit generates the digital input word for the DAC based on the first and second comparator outputs.

Abstract: A transmitter circuit includes a phase locked loop circuit, having one or more operational characteristics indicative of an operating state of the phase locked loop circuit. The phase locked loop circuit is configured to generate a frequency signal. The transmitter circuit also includes a power amplifier configured to selectively drive an antenna with a drive signal according to the frequency signal, and a programmable delay circuit configured to controllably extend a propagation delay between the frequency signal and the drive signal of the power amplifier. The programmable delay circuit is programmed such that a first value of a particular operational characteristic of the phase locked loop circuit is substantially equal to a second value of the operational characteristic of the phase locked loop circuit. The first value is measured with the power amplifier not driving the antenna. The second value is measured with the power amplifier driving the antenna.

Abstract: A transmitter circuit is disclosed. The transmitter circuit includes a frequency circuit configured to generate a frequency signal, a power amplifier configured to drive an antenna with a drive signal according to the frequency signal, and a programmable delay circuit configured to controllably extend a propagation delay between the frequency signal generated by the frequency circuit and the drive signal of the power amplifier. The programmable delay circuit is programmed with a programming value which causes the transmitter circuit to pass a calibration test.

Abstract: A converter circuit includes a pull up component, a pull down component, and a controller configured to operate the pull up component and the pull down component so as to deliver power to a load. The controller is configured to operate the pull up and pull down components in first and second operational modes, based on an average current delivered to the load. The converter circuit also includes a mode control circuit to generate a mode control signal based in part on a representation of a peak current received at the switch node from the pull up component.

Abstract: A converter circuit is disclosed. The converter circuit includes a controller configured to operate a pull up component and a pull down component so as to deliver power to a load through an inductor. The controller is configured to operate in either of first and second operational modes based on average current delivered to the load.

Abstract: A transceiver includes a receive path including a low noise amplifier and a first switch coupled between the low noise amplifier and ground, a first transmit path including a low power amplifier and a second switch coupled between the low power amplifier and a main signal path, and a second transmit path including a high power amplifier and a third switch coupled between the main signal path and ground. The receive path is active when the first, second, and third switches are in an open position, the first transmit path is active when the first switch is in a closed position, the second switch is in the closed position, and the third switch is in the open position, and the second transmit path is active when the first switch and the third switch are in the closed position, and the second switch is in the open position.

Abstract: A clock generation circuit is disclosed. The clock generation circuit includes a first PLL circuit configured to generate a first output clock based on a first input clock, where the first PLL circuit includes a first feedback divider circuit. The clock generation circuit also includes a second PLL circuit configured to generate a second output clock based on a second input clock, where the second PLL circuit includes a second feedback divider circuit. The first input clock is generated based on the second output clock.

Abstract: Techniques are described for fast wakeup of a crystal oscillator circuit. Embodiments operate in context of a crystal oscillator coupled with a phase-locked loop (PLL). For example, prior to entering sleep mode, embodiments retain a previously obtained coarse code used to coarse-tune a voltage controlled oscillator of the PLL. On wakeup, the PLL is configured in a chirp mode, in which the retained coarse code and a sweep voltage are used to generate a chirp signal at, or close to, a target stimulating frequency for the crystal oscillator. The chirp signal can be used to inject energy into the crystal oscillator, thereby causing the crystal oscillator to move from sleep mode to steady state oscillation relatively quickly.

Abstract: Techniques are described for ripple detection and cancellation in switching voltage regulator circuits. For example, in a switching voltage converter, a voltage is up-converted or down-converted by switching high side and low side switches and passed through a low-pass filter for averaging. While the act of switching can result in conversion of the voltage with good efficiency, it also typically generates ripples on the output voltage, which can be undesirable in some applications. Embodiments use the switching voltage, the output voltage, and a feed-forward loop to generate a current cancellation signal to have particular gain, timing, and polarity that effectively emulates the complement of the inductor ripple current. The cancellation current signal can be injected into the output node, such that the cancellation current signal sums with the inductor ripple current at the output node, thereby at least partially cancelling the effect of the inductor ripple current.

Abstract: A DLL circuit is disclosed. The DLL circuit includes a delay line, configured to receive a delay line input clock, and to generate a plurality of output clocks each having a phase based on a delay of the delay line. The DLL circuit also includes a control circuit, configured to selectively cause the delay line input clock to be equal to one of a DLL input clock and an inverted one of the output clocks of the delay line, and an edge combiner, configured to generate a DLL output clock based on the output clocks of the delay line.

Abstract: A transceiver includes a receive path including a low noise amplifier and a first switch coupled between the low noise amplifier and ground, a first transmit path including a low power amplifier and a second switch coupled between the low power amplifier and a main signal path, and a second transmit path including a high power amplifier and a third switch coupled between the main signal path and ground. The receive path is active when the first, second, and third switches are in an open position, the first transmit path is active when the first switch is in a closed position, the second switch is in the closed position, and the third switch is in the open position, and the second transmit path is active when the first switch and the third switch are in the closed position, and the second switch is in the open position.

Abstract: Techniques are described for power detection of an amplified signal. For example, power detection described herein can receive an amplified signal from a power amplifier, and can generate an output signal that can be fed back to help regulate an output level of the power amplifier. Embodiments receive the amplified signal can be received by a transistor. A first measurement can be obtained at the transistor's emitter corresponding to an average bias level of the amplified signal, and a second measurement can be obtained at the transistor's base. The output signal can be generated as a function of a difference between the two measurements. Some embodiments further compensate for a measured effective diode voltage corresponding to a base-emitter voltage. Such an approach can generate the power detector output signal to be independent of the ? of the transistor, and therefore less affected by variations in process corners and temperature.

Abstract: A semiconductor device includes a current source, an input/output (IO) region having a first IO device and a second IO device, and a core region having a core device. The first and second IO devices form with the current source a current mirror circuit. Each of the first and second IO devices has a first threshold voltage, and the core device has a second threshold voltage that is lower than the first threshold voltage. The first core device is coupled to the first and second IO devices and the current source and provides an offset voltage to the current source.

Abstract: Techniques are described for implementing fractional dividers in modulated phase-lock loop circuits. For example, a fractional divider can receive a base dividing value having integer and fractional components (e.g., corresponding to a carrier frequency produced by multiplying the dividing value by a reference frequency). The fractional divider can also receive a data signal to modulate the dividing value. Embodiments use a shift value (e.g., preset, or received via a shift input signal) to selectively shift and scale the modulated dividing value to generate a shifted fractional component value. The shifted fractional component value can be added to the base integer component, and de-shifted and de-scaled to generate a corrected dividing value. A feedback signal can then be generated by sequentially dividing a frequency of a clock output signal by the corrected dividing value.