Patents by Inventor Ahmed A. Emira

Ahmed A. Emira has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10742228
    Abstract: An analog to digital converter (ADC) is disclosed. The ADC includes a DAC which generates a first signal based on an analog input and a digital input word, and a comparator which generates a comparator output having a value corresponding with a sign of a difference between first and second signals. During a first time period, the second signal is equal to a reference signal, the first signal is equal to an analog input, and the comparator generates a first comparator output. During a second time period, the second signal is equal to the reference signal, the first signal is equal to a the analog input plus a predetermined signal, and the comparator generates a second comparator output. A SAR logic circuit generates the digital input word for the DAC based on the first and second comparator outputs.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: August 11, 2020
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Mohamed Aboudina, Ali Farid, Ahmed Emira, Hassan Elwan
  • Patent number: 10735017
    Abstract: A successive approximation register (SAR) analog to digital converter (ADC) is disclosed. The SAR ADC includes: a DAC, configured to receive an analog input voltage and a digital input word, and to generate a first voltage. The SAR ADC also includes a comparator, configured to generate a second voltage based on the first voltage and a reference voltage. The second voltage has a value corresponding with a sign of the difference between the first voltage and the reference voltage. The SAR ADC also includes an SAR logic circuit configured to receive the second voltage from the comparator, and to generate the digital input word for the DAC. The SAR logic is further configured to generate a digital output word representing the value of the analog input voltage, where the digital output word of the SAR logic has a greater number of bits than the digital input word of the DAC.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: August 4, 2020
    Assignee: GOODIX TECHNOLOGY INC.
    Inventors: Mohamed Aboudina, Ali Farid, Ahmed Emira, Hassan Elwan
  • Patent number: 10727857
    Abstract: An ADC is disclosed. The ADC includes a SAR logic circuit, a DAC, a comparator, and a voltage generator. The voltage generator includes a first switch connected to the comparator configured to selectively connect a second input terminal of the comparator to a reference voltage, a capacitor connected to the second input terminal of the comparator, and a second switch connected to the capacitor and selectively connected to either of a ground voltage and the reference voltage. The second switch is configured to selectively connect the capacitor to either of the ground voltage and the reference voltage, and the SAR logic circuit is further configured to receive the comparator output voltage, and to generate a digital input word for the DAC based on one or more comparator output voltages received from the comparator.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: July 28, 2020
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Ali Farid, Ahmed Emira, Mohamed Aboudina, Hassan Elwan
  • Patent number: 10693462
    Abstract: Techniques are described for ground-intermediating buffering that can effectively use the reference grounds of the circuit domains on either side of a buffer stage to generate one or more intermediated grounds for one or more signal buffers. For example, one of the reference grounds has a first amount of ground noise, the other of the reference grounds has a second amount of ground noise that is greater than or less than the first amount, and the intermediated grounds are generated to have respective amounts of ground noise that are between the first and second amounts. The ground intermediating buffer can perform signal buffering with respect to the intermediated ground(s), thereby reducing ground noise coupling across the circuit domains through both the signal and ground paths of the buffer stage.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: June 23, 2020
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Kaveh Moazzami, Faisal Hussein, Ahmed Emira
  • Publication number: 20200195256
    Abstract: Techniques are described for peak-adaptive sampling demodulation for radiofrequency transceivers. For example, a tag input signal is received via an antenna, from which a clock input signal can be extracted. Multiple clock output signals can be generated responsive to the extracted clock input signal, such that each has a different respective phase. A multiphase selector can identify the one of the clock output signals that has the respective phase that is closest to the phase of the tag input signal and is best suited for sampling the peak of the tag input signal, accordingly. A single-path detector can generate a data output signal by using the identified clock output signal to sample the tag input signal, and the detector can filter and amplify the data output signal using small-signal devices.
    Type: Application
    Filed: December 12, 2018
    Publication date: June 18, 2020
    Inventors: Ahmed EMIRA, Ahmet Tekin, Hassan Osama ELWAN, Janakan SIVASUBRAMANIAM
  • Publication number: 20200186023
    Abstract: Techniques are described for ripple detection and cancellation in switching voltage regulator circuits. For example, in a switching voltage converter, a voltage is up-converted or down-converted by switching high side and low side switches and passed through a low-pass filter for averaging. While the act of switching can result in conversion of the voltage with good efficiency, it also typically generates ripples on the output voltage, which can be undesirable in some applications. Embodiments use the switching voltage, the output voltage, and a feed-forward loop to generate a current cancellation signal to have particular gain, timing, and polarity that effectively emulates the complement of the inductor ripple current. The cancellation current signal can be injected into the output node, such that the cancellation current signal sums with the inductor ripple current at the output node, thereby at least partially cancelling the effect of the inductor ripple current.
    Type: Application
    Filed: February 14, 2020
    Publication date: June 11, 2020
    Inventors: Siavash Yazdi, Ahmed Emira
  • Publication number: 20200169260
    Abstract: Techniques are described for fast wakeup of a crystal oscillator circuit. Embodiments operate in context of a crystal oscillator coupled with a phase-locked loop (PLL). For example, prior to entering sleep mode, embodiments retain a previously obtained coarse code used to coarse-tune a voltage controlled oscillator of the PLL. On wakeup, the PLL is configured in a chirp mode, in which the retained coarse code and a sweep voltage are used to generate a chirp signal at, or close to, a target stimulating frequency for the crystal oscillator. The chirp signal can be used to inject energy into the crystal oscillator, thereby causing the crystal oscillator to move from sleep mode to steady state oscillation relatively quickly.
    Type: Application
    Filed: January 31, 2020
    Publication date: May 28, 2020
    Inventors: Mohamed Aboudina, Ahmed Emira, Faisal Hussien
  • Patent number: 10651793
    Abstract: Techniques are described for reducing frequency pulling in voltage-controlled oscillator (VCO) circuits. Some embodiments operate in context of a transmitter having a VCO and a power amplifier (PA), where resonant components of the VCO are impacted by magnetically coupled feedback from resonant components of the PA. The VCO and PA are coupled via a set of signal path components that cause signal path delay, such that the feedback signal is phase-delayed with respect to the signal generated by the VCO. A coupling delay matching system is used to introduce additional delay, thereby further phase-shifting the feedback signal to an integer multiple of the oscillation period of the VCO signal; thereby reducing frequency pulling of the VCO.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: May 12, 2020
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Ahmed Emira, Faisal Hussein
  • Publication number: 20200136620
    Abstract: Techniques are described for ground-intermediating buffering that can effectively use the reference grounds of the circuit domains on either side of a buffer stage to generate one or more intermediated grounds for one or more signal buffers. For example, one of the reference grounds has a first amount of ground noise, the other of the reference grounds has a second amount of ground noise that is greater than or less than the first amount, and the intermediated grounds are generated to have respective amounts of ground noise that are between the first and second amounts. The ground intermediating buffer can perform signal buffering with respect to the intermediated ground(s), thereby reducing ground noise coupling across the circuit domains through both the signal and ground paths of the buffer stage.
    Type: Application
    Filed: September 18, 2019
    Publication date: April 30, 2020
    Inventors: Kaveh Moazzami, Faisal Hussein, Ahmed Emira
  • Patent number: 10637418
    Abstract: A power amplifier includes an input terminal configured to receive a low voltage input signal, an output terminal configured to output a high voltage output signal, and a plurality of amplifiers stacked in series between a first voltage terminal and a second voltage terminal. Each of the amplifiers includes an input capacitor, an output capacitor, an input coupled to the input terminal through the input capacitor, an output coupled to the output terminal through the output capacitor, and a feedback element coupled between the input and the output of the amplifier.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: April 28, 2020
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Ahmed Emira, Rami Khatib, Faisal Hussien
  • Patent number: 10630305
    Abstract: A self-calibrating analog-to-digital converter includes a reference signal circuit configured to provide a reference signal, an analog-to-digital converter configured to generate a first digital representation of the reference signal, a dual-slope analog-to-digital converter configured to generate a second digital representation of the reference signal, and a digital engine configured to compare the first digital representation with the second digital representation to obtain a difference and output a calibration signal to the analog-to-digital converter in response to the difference. The reference signal circuit, the analog-to-digital converter, the dual-slop analog-to-digital converter, and digital engine are integrated in an integrated circuit.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: April 21, 2020
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Ali Farid, Ahmed Emira, Hassan Elwan
  • Patent number: 10629755
    Abstract: Techniques are described for staggered-bias varactors. For example, a staggered-bias varactor can include a control voltage node, a number of bias voltage nodes, and a number of sub-varactors coupled in parallel. The control voltage node can be configured to receive a single, variable control voltage; and the bias voltage nodes can each be configured to receive a different, fixed bias voltage. Each sub-varactor is configured, so that its equivalent capacitance is a function of a difference between the control voltage and a respective one of the bias voltages; and the equivalent capacitance of the staggered-bias varactor is a function of the capacitances of the component sub-varactors. The number of varactors and the bias voltages can be configured, so that respective non-linear capacitive responses of the component sub-varactors effectively combine to yield a substantially linear capacitive response for the staggered-bias varactor as a whole.
    Type: Grant
    Filed: December 8, 2018
    Date of Patent: April 21, 2020
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Ahmed Emira, Faisal Hussein
  • Patent number: 10608524
    Abstract: Techniques are described for ripple detection and cancellation in switching voltage regulator circuits. For example, in a switching voltage converter, a voltage is up-converted or down-converted by switching high side and low side switches and passed through a low-pass filter for averaging. While the act of switching can result in conversion of the voltage with good efficiency, it also typically generates ripples on the output voltage, which can be undesirable in some applications. Embodiments use the switching voltage, the output voltage, and a feed-forward loop to generate a current cancellation signal to have particular gain, timing, and polarity that effectively emulates the complement of the inductor ripple current. The cancellation current signal can be injected into the output node, such that the cancellation current signal sums with the inductor ripple current at the output node, thereby at least partially cancelling the effect of the inductor ripple current.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: March 31, 2020
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Siavash Yazdi, Ahmed Emira
  • Patent number: 10594325
    Abstract: Techniques are described for fast wakeup of a crystal oscillator circuit. Embodiments operate in context of a crystal oscillator coupled with a phase-locked loop (PLL). For example, prior to entering sleep mode, embodiments retain a previously obtained coarse code used to coarse-tune a voltage controlled oscillator of the PLL. On wakeup, the PLL is configured in a chirp mode, in which the retained coarse code and a sweep voltage are used to generate a chirp signal at, or close to, a target stimulating frequency for the crystal oscillator. The chirp signal can be used to inject energy into the crystal oscillator, thereby causing the crystal oscillator to move from sleep mode to steady state oscillation relatively quickly.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: March 17, 2020
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Mohamed Aboudina, Ahmed Emira, Faisal Hussien
  • Publication number: 20200083798
    Abstract: Techniques are described for ripple detection and cancellation in switching voltage regulator circuits. For example, in a switching voltage converter, a voltage is up-converted or down-converted by switching high side and low side switches and passed through a low-pass filter for averaging. While the act of switching can result in conversion of the voltage with good efficiency, it also typically generates ripples on the output voltage, which can be undesirable in some applications. Embodiments use the switching voltage, the output voltage, and a feed-forward loop to generate a current cancellation signal to have particular gain, timing, and polarity that effectively emulates the complement of the inductor ripple current. The cancellation current signal can be injected into the output node, such that the cancellation current signal sums with the inductor ripple current at the output node, thereby at least partially cancelling the effect of the inductor ripple current.
    Type: Application
    Filed: April 23, 2019
    Publication date: March 12, 2020
    Inventors: Siavash Yazdi, Ahmed Emira
  • Patent number: 10574186
    Abstract: Techniques are described for reducing frequency pulling in voltage-controlled oscillator (VCO) circuits. Some embodiments operate in context of a transmitter having a VCO and a power amplifier (PA), where resonant components of the VCO are impacted by magnetically coupled feedback from resonant components of the PA. The VCO and PA are coupled via a set of signal path components that cause signal path delay, such that the feedback signal is phase-delayed with respect to the signal generated by the VCO. A coupling delay matching system is used to introduce additional delay, thereby further phase-shifting the feedback signal to an integer multiple of half of the oscillation period of the VCO signal; thereby reducing frequency pulling of the VCO.
    Type: Grant
    Filed: December 8, 2018
    Date of Patent: February 25, 2020
    Assignee: SHENZHEN GOODIX TECHNOLOGYCO., LTD.
    Inventors: Ahmed Emira, Faisal Hussein
  • Publication number: 20200014396
    Abstract: An analog to digital converter (ADC) is disclosed. The ADC includes a DAC which generates a first signal based on an analog input and a digital input word, and a comparator which generates a comparator output having a value corresponding with a sign of a difference between first and second signals. During a first time period, the second signal is equal to a reference signal, the first signal is equal to an analog input, and the comparator generates a first comparator output. During a second time period, the second signal is equal to the reference signal, the first signal is equal to a the analog input plus a predetermined signal, and the comparator generates a second comparator output. A SAR logic circuit generates the digital input word for the DAC based on the first and second comparator outputs.
    Type: Application
    Filed: August 5, 2019
    Publication date: January 9, 2020
    Inventors: Mohamed Aboudina, Ali Farid, Ahmed Emira, HASSAN ELWAN
  • Publication number: 20200014390
    Abstract: Techniques are described for fast wakeup of a crystal oscillator circuit. Embodiments operate in context of a crystal oscillator coupled with a phase-locked loop (PLL). For example, prior to entering sleep mode, embodiments retain a previously obtained coarse code used to coarse-tune a voltage controlled oscillator of the PLL. On wakeup, the PLL is configured in a chirp mode, in which the retained coarse code and a sweep voltage are used to generate a chirp signal at, or close to, a target stimulating frequency for the crystal oscillator. The chirp signal can be used to inject energy into the crystal oscillator, thereby causing the crystal oscillator to move from sleep mode to steady state oscillation relatively quickly.
    Type: Application
    Filed: July 6, 2018
    Publication date: January 9, 2020
    Inventors: Mohamed Aboudina, Ahmed Emira, Faisal Hussien
  • Publication number: 20200014351
    Abstract: A power amplifier includes an input terminal configured to receive a low voltage input signal, an output terminal configured to output a high voltage output signal, and a plurality of amplifiers stacked in series between a first voltage terminal and a second voltage terminal. Each of the amplifiers includes an input capacitor, an output capacitor, an input coupled to the input terminal through the input capacitor, an output coupled to the output terminal through the output capacitor, and a feedback element coupled between the input and the output of the amplifier.
    Type: Application
    Filed: July 6, 2018
    Publication date: January 9, 2020
    Inventors: Ahmed Emira, RAMI KHATIB, Faisa Hussien
  • Publication number: 20200007143
    Abstract: An ADC is disclosed. The ADC includes a SAR logic circuit, a DAC, a comparator, and a voltage generator. The voltage generator includes a first switch connected to the comparator configured to selectively connect a second input terminal of the comparator to a reference voltage, a capacitor connected to the second input terminal of the comparator, and a second switch connected to the capacitor and selectively connected to either of a ground voltage and the reference voltage. The second switch is configured to selectively connect the capacitor to either of the ground voltage and the reference voltage, and the SAR logic circuit is further configured to receive the comparator output voltage, and to generate a digital input word for the DAC based on one or more comparator output voltages received from the comparator.
    Type: Application
    Filed: September 4, 2019
    Publication date: January 2, 2020
    Inventors: Ali Farid, Ahmed Emira, Mohamed Aboudina, HASSAN ELWAN