Patents by Inventor Ahmed A. Emira

Ahmed A. Emira has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190384343
    Abstract: A semiconductor device includes a current source, an input/output (IO) region having a first IO device and a second IO device, and a core region having a core device. The first and second IO devices form with the current source a current mirror circuit. Each of the first and second IO devices has a first threshold voltage, and the core device has a second threshold voltage that is lower than the first threshold voltage. The first core device is coupled to the first and second IO devices and the current source and provides an offset voltage to the current source.
    Type: Application
    Filed: August 30, 2019
    Publication date: December 19, 2019
    Inventors: Mohamed Aboudina, Ahmed Emira, Hassan Elwan
  • Publication number: 20190379333
    Abstract: Techniques are described for using valley detection for supply voltage modulation in power amplifier circuits. Embodiments operate in context of a power amplifier circuit configured to be driven by a supply voltage generated by a supply modulator and to receive an amplitude-modulated (AM) signal at its input. The output of the power amplifier circuit can be fed to a valley detector that can detect a valley level corresponding to the bottom of the envelope of the AM signal. The detected valley level can be fed back to the supply modulator and compared to a constant reference. In response to the comparison, the supply modulator can vary the supply voltage to the power amplifier circuit in a manner that effectively tracking the envelope of the power amplifier circuit's output signal, thereby effectively seeking a flat valley for the output signal's envelope.
    Type: Application
    Filed: June 6, 2018
    Publication date: December 12, 2019
    Inventors: Ahmed Emira, Siavash Yazdi, Kaveh Moazzami
  • Publication number: 20190372583
    Abstract: An ADC, including a DAC which receives an analog input voltage and a digital input word from SAR logic, and generates a first voltage based on the analog input voltage and the digital word. The ADC also includes a comparator, which receives the first voltage and a reference voltage, and generates a second voltage based on the first voltage and on the reference voltage. The second voltage has a value corresponding with a sign of the difference between the first voltage and the reference voltage. The ADC also includes the SAR logic circuit which receives the second voltage from the comparator. The SAR logic generates a digital output word based on a second voltages received from the comparator. A difference between the minimum input voltage on the maximum input voltage is substantially equal to two times a difference between reference voltage and the minimum input voltage.
    Type: Application
    Filed: April 29, 2019
    Publication date: December 5, 2019
    Inventors: Ali Farid, Ahmed Emira, Mohamed Aboudina, HASSAN ELWAN
  • Publication number: 20190372584
    Abstract: An array of capacitors includes a first array of k capacitors coupled to a first node and having capacitances which are binary weighted multiples of a unit capacitance value, a second array of m capacitors coupled to a second node and having capacitances which are binary weighted multiples of the unit capacitance value, a coupling capacitor disposed between the first node and the second node, and a trimmable grounded capacitor coupled between the first node and a ground potential.
    Type: Application
    Filed: May 31, 2018
    Publication date: December 5, 2019
    Inventors: Ahmed Emira, Mohamed Aboudina
  • Publication number: 20190372582
    Abstract: A successive approximation register (SAR) analog to digital converter (ADC) is disclosed. The SAR ADC includes: a DAC, configured to receive an analog input voltage and a digital input word, and to generate a first voltage. The SAR ADC also includes a comparator, configured to generate a second voltage based on the first voltage and a reference voltage. The second voltage has a value corresponding with a sign of the difference between the first voltage and the reference voltage. The SAR ADC also includes an SAR logic circuit configured to receive the second voltage from the comparator, and to generate the digital input word for the DAC. The SAR logic is further configured to generate a digital output word representing the value of the analog input voltage, where the digital output word of the SAR logic has a greater number of bits than the digital input word of the DAC.
    Type: Application
    Filed: May 31, 2018
    Publication date: December 5, 2019
    Inventors: Mohamed Aboudina, Ali Farid, Ahmed Emira, Hassan Elwan
  • Patent number: 10491232
    Abstract: An ADC, including a DAC which receives an analog input voltage and a digital input word from SAR logic, and generates a first voltage based on the analog input voltage and the digital word. The ADC also includes a comparator, which receives the first voltage and a reference voltage, and generates a second voltage based on the first voltage and on the reference voltage. The second voltage has a value corresponding with a sign of the difference between the first voltage and the reference voltage. The ADC also includes the SAR logic circuit which receives the second voltage from the comparator. The SAR logic generates a digital output word based on a second voltages received from the comparator. A difference between the minimum input voltage on the maximum input voltage is substantially equal to two times a difference between reference voltage and the minimum input voltage.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: November 26, 2019
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Ali Farid, Ahmed Emira, Mohamed Aboudina, Hassan Elwan
  • Patent number: 10491233
    Abstract: An array of capacitors includes a first array of k capacitors coupled to a first node and having capacitances which are binary weighted multiples of a unit capacitance value, a second array of m capacitors coupled to a second node and having capacitances which are binary weighted multiples of the unit capacitance value, a coupling capacitor disposed between the first node and the second node, and a trimmable grounded capacitor coupled between the first node and a ground potential.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: November 26, 2019
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Ahmed Emira, Mohamed Aboudina
  • Patent number: 10461767
    Abstract: An ADC is disclosed. The ADC includes a SAR logic circuit, a DAC, a comparator, and a voltage generator. The voltage generator includes a first switch connected to the comparator configured to selectively connect a second input terminal of the comparator to a reference voltage, a capacitor connected to the second input terminal of the comparator, and a second switch connected to the capacitor and selectively connected to either of a ground voltage and the reference voltage. The second switch is configured to selectively connect the capacitor to either of the ground voltage and the reference voltage, and the SAR logic circuit is further configured to receive the comparator output voltage, and to generate a digital input word for the DAC based on one or more comparator output voltages received from the comparator.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: October 29, 2019
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Ali Farid, Ahmed Emira, Mohamed Aboudina, Hassan Elwan
  • Patent number: 10461749
    Abstract: Techniques are described for ground-intermediating buffering that can effectively use the reference grounds of the circuit domains on either side of a buffer stage to generate one or more intermediated grounds for one or more signal buffers. For example, one of the reference grounds has a first amount of ground noise, the other of the reference grounds has a second amount of ground noise that is greater than or less than the first amount, and the intermediated grounds are generated to have respective amounts of ground noise that are between the first and second amounts. The ground intermediating buffer can perform signal buffering with respect to the intermediated ground(s), thereby reducing ground noise coupling across the circuit domains through both the signal and ground paths of the buffer stage.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: October 29, 2019
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Kaveh Moazzami, Faisal Hussein, Ahmed Emira
  • Publication number: 20190319664
    Abstract: A transceiver includes a receive path including a low noise amplifier and a first switch coupled between the low noise amplifier and ground, a first transmit path including a low power amplifier and a second switch coupled between the low power amplifier and a main signal path, and a second transmit path including a high power amplifier and a third switch coupled between the main signal path and ground. The receive path is active when the first, second, and third switches are in an open position, the first transmit path is active when the first switch is in a closed position, the second switch is in the closed position, and the third switch is in the open position, and the second transmit path is active when the first switch and the third switch are in the closed position, and the second switch is in the open position.
    Type: Application
    Filed: May 6, 2019
    Publication date: October 17, 2019
    Inventors: Ahmed Emira, Rami Khatib, Janakan Sivasubramaniam, Jared Gagne
  • Patent number: 10429877
    Abstract: A current reference circuit includes a current source, a first p-channel metal oxide semiconductor (PMOS) transistor having a source coupled to a first supply voltage, a gate, and a drain coupled to the current source, and an n-channel MOS (NMOS) transistor having a drain coupled to a second supply voltage, a gate coupled to the drain of the first PMOS transistor. The current reference circuit also includes a first resistive element having a first terminal coupled to a source of the NMOS transistor and a gate of the first PMOS transistor and a second terminal coupled to a ground potential, a second PMOS transistor having a drain coupled to the first supply voltage, and a second resistive element having a first terminal coupled to the first terminal of the first resistive element and a second terminal coupled to the gate of the second PMOS transistor.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: October 1, 2019
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Mohamed Aboudina, Ahmed Emira, Hassan Elwan
  • Patent number: 10432213
    Abstract: An analog to digital converter (ADC) is disclosed. The ADC includes a DAC which generates a first signal based on an analog input and a digital input word, and a comparator which generates a comparator output having a value corresponding with a sign of a difference between first and second signals. During a first time period, the second signal is equal to a reference signal, the first signal is equal to an analog input, and the comparator generates a first comparator output. During a second time period, the second signal is equal to the reference signal, the first signal is equal to a the analog input plus a predetermined signal, and the comparator generates a second comparator output. A SAR logic circuit generates the digital input word for the DAC based on the first and second comparator outputs.
    Type: Grant
    Filed: July 8, 2018
    Date of Patent: October 1, 2019
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Mohamed Aboudina, Ali Farid, Ahmed Emira, Hassan Elwan
  • Publication number: 20190222218
    Abstract: A self-calibrating analog-to-digital converter includes a reference signal circuit configured to provide a reference signal, an analog-to-digital converter configured to generate a first digital representation of the reference signal, a dual-slope analog-to-digital converter configured to generate a second digital representation of the reference signal, and a digital engine configured to compare the first digital representation with the second digital representation to obtain a difference and output a calibration signal to the analog-to-digital converter in response to the difference. The reference signal circuit, the analog-to-digital converter, the dual-slop analog-to-digital converter, and digital engine are integrated in an integrated circuit.
    Type: Application
    Filed: September 25, 2018
    Publication date: July 18, 2019
    Inventors: Ali Farid, Ahmed Emira, HASSAN ELWAN
  • Patent number: 10333579
    Abstract: A wireless transceiver includes a receive path having a first switch and configured to receive an input signal when the first switch is in an open position, a first transmit path having a second switch and configured to provide a first output signal when the second switch is in a closed position and the first switch is in a closed position, and a second transmit path having a third switch and configured to provide a second output signal when the third switch is in a closed position, the first switch is in the closed position, and the second switch is in an open position. The first, second, and third switches are integrated together with the receive path, the first RF transmit path, and the second transmit path within a same integrated circuit.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: June 25, 2019
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Ahmed Emira, Rami Khatib, Janakan Sivasubramaniam, Jared Gagne
  • Patent number: 10298114
    Abstract: Techniques are described for ripple detection and cancellation in switching voltage regulator circuits. For example, in a switching voltage converter, a voltage is up-converted or down-converted by switching high side and low side switches and passed through a low-pass filter for averaging. While the act of switching can result in conversion of the voltage with good efficiency, it also typically generates ripples on the output voltage, which can be undesirable in some applications. Embodiments use the switching voltage, the output voltage, and a feed-forward loop to generate a current cancellation signal to have particular gain, timing, and polarity that effectively emulates the complement of the inductor ripple current. The cancellation current signal can be injected into the output node, such that the cancellation current signal sums with the inductor ripple current at the output node, thereby at least partially cancelling the effect of the inductor ripple current.
    Type: Grant
    Filed: September 8, 2018
    Date of Patent: May 21, 2019
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Siavash Yazdi, Ahmed Emira
  • Patent number: 10291252
    Abstract: An ADC, including a DAC which receives an analog input voltage and a digital input word from SAR logic, and generates a first voltage based on the analog input voltage and the digital word. The ADC also includes a comparator, which receives the first voltage and a reference voltage, and generates a second voltage based on the first voltage and on the reference voltage. The second voltage has a value corresponding with a sign of the difference between the first voltage and the reference voltage. The ADC also includes the SAR logic circuit which receives the second voltage from the comparator. The SAR logic generates a digital output word based on a second voltages received from the comparator. A difference between the minimum input voltage on the maximum input voltage is substantially equal to two times a difference between reference voltage and the minimum input voltage.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: May 14, 2019
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Ali Farid, Ahmed Emira, Mohamed Aboudina, Hassan Elwan
  • Patent number: 10128857
    Abstract: In one embodiment, a radio receiver includes: a programmable frequency synthesizer to generate a first clock signal; a first frequency divider to divide the first clock signal to generate a master clock signal; a second frequency divider to divide the master clock signal to generate a mixing signal; and a mixer to downconvert a radio frequency (RF) signal to a second frequency signal using the mixing signal. A voltage converter to couple to the radio receiver includes a switch controllable to switchably couple a first voltage to a storage device and a pulse generator to generate at least one pulse pair formed of a first pulse and a second pulse substantially identical to the first pulse, when a second voltage is less than a first threshold voltage, the second pulse separated from the first pulse by a pulse separation interval.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: November 13, 2018
    Assignee: Silicon Laboratories Inc.
    Inventors: Mohamed Elkholy, Ahmed Emira
  • Patent number: 10090848
    Abstract: A self-calibrating analog-to-digital converter includes a reference signal circuit configured to provide a reference signal, an analog-to-digital converter configured to generate a first digital representation of the reference signal, a dual-slope analog-to-digital converter configured to generate a second digital representation of the reference signal, and a digital engine configured to compare the first digital representation with the second digital representation to obtain a difference and output a calibration signal to the analog-to-digital converter in response to the difference. The reference signal circuit, the analog-to-digital converter, the dual-slop analog-to-digital converter, and digital engine are integrated in an integrated circuit.
    Type: Grant
    Filed: January 14, 2018
    Date of Patent: October 2, 2018
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Ali Farid, Ahmed Emira, Hassan Elwan, Mohamed Aboudina, Janakan Sivasubramaniam
  • Patent number: 10079793
    Abstract: Wireless Charging Smart-Gem Jewelry System and Associated Cloud Server comprising a wearable electronic gemstone capable of sensing the emotional state and bodily vital signs of the user and being wirelessly charged and a mobile device capable of communicating with the electronic gemstone such that a cloud server manages communications between members of a social network wearing the electronically smart gemstone. The disclosed Jewelry System provides a custom gemstone with symbol-carved light effects, wireless charging of the stone electronics through universal audio jack of any mobile device, and electrical stimulation of the user along with visual triggers as a specific mode of social interaction.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: September 18, 2018
    Assignee: WAVEWORKS INC.
    Inventors: Ahmet Tekin, Ahmed Emira
  • Patent number: 9614024
    Abstract: In accordance with the present disclosure, one embodiment of a fractal variable capacitor comprises a capacitor body in a microelectromechanical system (MEMS) structure, wherein the capacitor body has an upper first metal plate with a fractal shape separated by a vertical distance from a lower first metal plate with a complementary fractal shape; and a substrate above which the capacitor body is suspended.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: April 4, 2017
    Assignee: KING ABDULLAH UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Amro M. Elshurafa, Ahmed Gomaa Ahmed Radwan, Ahmed A. Emira, Khaled Nabil Salama