Patents by Inventor Akihiko Ito
Akihiko Ito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6172662Abstract: The present invention: (1) divides a selection period into a plurality of sub-selection periods (t11, t21, t31, t41), and distributes these sub-selection periods throughout the period in one frame; (2) further divides a sub-selection period into a plurality of divided sub-selection periods ((s1, s2), (s3, s4), (s5, s6), (s7, s8)), and switches electric potentials of the selection signals between divided sub-selection period in order to eliminate the effects of spikes in voltage from the scanning signals to be applied to adjacent scanning electrodes, and applies these features to commonly known multi-line driving method.Type: GrantFiled: April 18, 1996Date of Patent: January 9, 2001Assignee: Seiko Epson CorporationInventors: Akihiko Ito, Takashi Kurumisawa
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Patent number: 6104183Abstract: A semiconductor device testing apparatus having a reduced transverse width and compact in size is provided. Adjacent to a constant temperature chamber 101 containing therein a vertical transport means is located a test chamber 102 which is in turn adjoined by a temperature-stress removing chamber 103 likewise containing therein a vertical transport means, so that the constant temperature chamber 101, the test chamber 102 and the temperature-stress removing chamber 103 are arranged transversely in a line. Further, a loader section 300 is located in front of the constant temperature chamber, and an unloader section 400 is located in front of the test chamber and the temperature-stress removing chamber. With this arrangement, the transverse width of the testing apparatus may be reduced to about three test tray lengths.Type: GrantFiled: May 28, 1997Date of Patent: August 15, 2000Assignee: Advantest CorporationInventors: Yoshihito Kobayashi, Tsuyoshi Yamashita, Hiroto Nakamura, Shin Nemoto, Yoshiyuki Masuo, Akihiko Ito
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Patent number: 6084563Abstract: A multiplex driving method is provided for a liquid crystal cell device having a liquid crystal layer disposed between a pair of substrates, a plurality of row electrodes arranged on one of the substrates and a plurality of column electrodes arranged on the other substrate. The method comprises the steps of sequentially selecting a group of the plurality of row electrodes during a selection period, simultaneously selecting the row electrodes comprising the group, and dividing and separating the selection period into a plurality of intervals within one frame period.Type: GrantFiled: November 4, 1993Date of Patent: July 4, 2000Assignee: Seiko Epson CorporationInventors: Akihiko Ito, Shoichi Iino
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Patent number: 5963189Abstract: A multiplex driving method is provided for a liquid crystal cell device having a liquid crystal layer disposed between a pair of substrates, a plurality of row electrodes arranged on one of the substrates and a plurality of column electrodes arranged on the other substrate. The method comprises the steps of sequentially selecting a group of the plurality of row electrodes during a selection period, simultaneously selecting the row electrodes comprising the group, and dividing and separating the selection period into a plurality of intervals within one frame period.Type: GrantFiled: May 31, 1995Date of Patent: October 5, 1999Assignee: Seiko Epson CorporationInventors: Akihiko Ito, Shoichi Iino
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Patent number: 5959603Abstract: A multiplex driving method and driving apparatus are provided for a liquid crystal display device having a liquid crystal layer disposed between a pair of substrates, a plurality of row electrodes arranged on one of the substrates and a plurality of column electrodes arranged on the other substrate, the plurality of row electrodes being arranged in plural groups. A portion of the row electrodes are simultaneously selected a within a selection period in which the selection period is divided into a plurality of intervals. A weighted voltage is applied in accordance with desired display data in each of the plurality of intervals to achieve a gray scale display.Type: GrantFiled: May 30, 1995Date of Patent: September 28, 1999Assignee: Seiko Epson CorporationInventors: Akihiko Ito, ShoichI Iino
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Patent number: 5940108Abstract: A printer comprises a frame, a platen supported by the frame for undergoing rotation, and a printing head for printing on a recording medium fed between the platen and the printing head. The printing head is supported by the frame for undergoing pivotal movement into and out of pressure contact with the platen. A biasing member is mounted for movement between a first position in which the biasing member is in a neutral, unstretched state, and a second position in which the biasing member is in stretched state. The biasing member has a first end integrally connected to the printing head and a second end opposite the first end. An operation member is integrally connected to the second end of the biasing member and is supported by the frame for undergoing pivotal movement between a first position and a second position. When the operation member is pivoted to the first position, the biasing member is moved to the first position and the printing head is pivoted out of pressure contact with the platen.Type: GrantFiled: July 11, 1997Date of Patent: August 17, 1999Assignee: Seiko Instruments Inc.Inventor: Akihiko Ito
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Patent number: 5900856Abstract: A matrix display apparatus is provided for displaying an image in accordance with display data. The display matrix comprises a plurality of scanning electrodes and a plurality of signal electrodes arranged in a matrix. A first driving circuit applies a plurality of selection voltages to the scanning electrodes. The scanning electrodes are divided into groups of h scanning electrodes. A selection voltage is applied to each of the plurality of scanning electrodes selected from the plurality of selection voltages in accordance with the selection pattern data. The second driving circuit provides a plurality of signal voltages to the plurality of signal electrodes. The second driver circuit comprises a memory for storing the display data for at least one group of h scanning electrodes and a selecting circuit for selecting a signal voltage applied to each of the plurality of signal electrodes.Type: GrantFiled: June 7, 1995Date of Patent: May 4, 1999Assignee: Seiko Epson CorporationInventors: Shoichi Iino, Akihiko Ito, Yoichi Imamura
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Patent number: 5877738Abstract: A multiplex driving method and driving apparatus are provided for a liquid crystal display device having a liquid crystal layer disposed between a pair of substrates, a plurality of row electrodes arranged on one of the substrates and a plurality of column electrodes arranged on the other substrate, the plurality of row electrodes being arranged in plural groups. A portion of the row electrodes are simultaneously selected a within a selection period in which the selection period is divided into a plurality of intervals. A weighted voltage is applied in accordance with desired display data in each of the plurality of intervals to achieve a gray scale display.Type: GrantFiled: January 7, 1994Date of Patent: March 2, 1999Assignee: Seiko Epson CorporationInventors: Akihiko Ito, Shoichi Iino
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Patent number: 5755522Abstract: A winding mechanism for recording paper is driven by a recording paper feeding motor disposed in a printing mechanism. The winding mechanism comprises a printing mechanism side pulley integrally connected at one end of a platen shaft of the printing mechanism for rotation by the recording paper feeding motor, a winding mechanism side pulley having a winding shaft and disposed in a part of a gear train on the winding mechanism, a belt for connecting the printing mechanism side pulley to the winding mechanism side pulley for transmitting a rotation of the printing mechanism side pulley to the winding mechanism side pulley, and a tension spring for imparting a tension to the belt. A clutch mechanism is disposed in the winding mechanism for maintaining the recording paper at a constant tension. A frame having a winding shaft insertion hole supports the winding shaft for rotation.Type: GrantFiled: September 30, 1996Date of Patent: May 26, 1998Assignee: Seiko Instruments Inc.Inventor: Akihiko Ito
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Patent number: 5635832Abstract: An IC carrier for loading thereon and transporting a device under test is used in an IC handler. The IC carrier is capable of easily and reliably loading thereon and positioning in place a device under test even the device under test having a reduced pitch between lead pins thereof. A box-like housing open in the top is formed and the bottom wall thereof has two generally parallel contact holes in the form of elongated slots, these two contact holes being spaced from each other by a spacing corresponding to that between two arrays of lead pins of the device under test. Each of the contact holes has a length corresponding to that of the associated lead pin array and a width sufficient to receive the associated lead pin array. Carrier guides are formed one adjacent each of opposite longitudinal ends of each of the contact holes and extend upwardly to a predetermined height from the bottom floor of the housing.Type: GrantFiled: February 8, 1996Date of Patent: June 3, 1997Assignee: Advantest CorporationInventors: Akihiko Ito, Yoshihito Kobayashi
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Patent number: 5570277Abstract: A switching power supply apparatus rectifies an AC power input in a rectifier circuit, switches a rectified output and rectifies and smoothes the same in a switching circuit, and a desired DC voltage is derived. A current limiting circuit limits a current supplied to a smoothing capacitor of the rectifier circuit. A voltage detecting circuit detects a rectified output of the rectifier circuit. A current limiting control circuit controls the current limiting circuit in response to a detected voltage. The current limiting control circuit activates the current limiting circuit in a first preset period in which the detected voltage is equal to or lower than a preset level. Further, the current limiting control circuit activates the current limiting circuit for a second preset period after the detected voltage is first changed from a level equal to or higher than the preset level to a level lower than the preset level and then returned to the level equal to or higher than the preset level.Type: GrantFiled: June 2, 1994Date of Patent: October 29, 1996Assignee: Fujitsu LimitedInventors: Akihiko Ito, Yukio Gotoh
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Patent number: 5269401Abstract: Both side walls of a channel groove for guiding integrated circuits with J-shaped leads are formed at an angle greater than 90 degrees to the bottom of the channel groove.Type: GrantFiled: August 3, 1992Date of Patent: December 14, 1993Assignee: Advantest CorporationInventors: Akihiko Ito, Hiroto Nakamura
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Patent number: 4850676Abstract: A method and circuits for multiplex driving of a liquid crystal element employing a ferroelectric liquid crystal therein. The method includes the step of applying a voltage pulse having an amplitude and a pulse width which exceeds a saturation voltage during a first half of a selecting term or a non-selecting term just before the selecting term to place the liquid crystal element in an "ON" or "OFF" state. The method also includes the step of applying the voltage pulse having a opposite polarity with respect to said voltage pulse and having an amplitude and a pulse width smaller than the threshhold voltage or exceeding the saturation voltage so that it is selected in order to maintain or to change the "ON" or "OFF" state. Further, it includes the step of rendering the average of a DC component which is applied to the liquid crystal element to zero by the method for applying a voltage pulse.Type: GrantFiled: April 22, 1987Date of Patent: July 25, 1989Assignee: Seiko Epson CorporationInventors: Minoru Yazaki, Yuzuru Sato, Akihiko Ito
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Patent number: 4591895Abstract: A semiconductor device including a plurality of CMOS (Complementary Metal Oxide Semiconductor) elements, each comprised of a conventional source region, a drain region, and a diffusion region located adjacent to source and drain elements, and each driven by a power source. A first conductor and a second conductor, which are newly introduced in the present device, are physically independent from each other. The first conductor is connected between the power source and the source region. The second conductor is connected between the power source and the diffusion region.Type: GrantFiled: October 8, 1985Date of Patent: May 27, 1986Assignee: Fujitsu LimitedInventors: Akihiko Ito, Tadahiro Saito
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Patent number: 4536949Abstract: A programmable integrated circuit has multi-layer wiring with openings over fuses, and a fabrication method forms the openings for each fuse, to avoid damage due to the blowing off of the fuses. The forming of the openings is performed by etching each insulating layer on the fuses after it is formed over the pre-formed wiring-layers. This results in shorter etching time as compared to the prior art etching method where the openings are etched in all the layers for the whole depth in one process step. Because of the shorter time necessary for each etching, overetching and side-etching are reduced, thus providing the openings with more accurately determined dimensions, which provides higher yield for manufacturing the device. The contact holes and the windows for the bonding pads in each insulating layer are etched in the same fabrication step for forming the openings for the fuses in the same insulating layer.Type: GrantFiled: May 11, 1984Date of Patent: August 27, 1985Assignee: Fujitsu LimitedInventors: Yoshihisa Takayama, Kunihiko Gotoh, Akihiko Ito, Takeshi Yamamura, Kazuyoshi Fujita
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Patent number: 4524333Abstract: A phase-locked loop circuit provides a phase comparator which receives input signals through a first input terminal, a loop filter which receives a first output and a second output of the phase comparator, and a voltage-controlled oscillator which produces output signals of an oscillation frequency proportional to the first output and the second output of the loop filter. The signals corresponding to the output signals produced by the voltage-controlled oscillator are supplied to a second input terminal of the phase comparator so that the phase of the signals supplied to the first input terminal of the phase comparator is compared with the phase of the signals supplied to the second input terminal.Type: GrantFiled: August 11, 1982Date of Patent: June 18, 1985Assignees: Nippon Telegraph & Telephone Public Corporation, Fujitsu LimitedInventors: Atsushi Iwata, Takao Kaneko, Akihiko Ito, Tadahiro Saito, Hirokazu Fukui
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Patent number: 4431973Abstract: An operational amplifier comprising a differential circuit, an output amplifier having an input terminal connected to the output terminal of the differential circuit, a phase compensating circuit, including an inverting amplifier having an input terminal connected to the output terminal of the differential circuit, and a phase compensating capacitor connected between the output terminal of the inverting amplifier and the output terminal of the differential circuit. The signal delay time of the inverting amplifier is shorter than that of the output amplifier.Type: GrantFiled: July 1, 1981Date of Patent: February 14, 1984Assignee: Fujitsu LimitedInventors: Kunihiko Goto, Kazuhiro Kobayashi, Akihiko Ito, Hisami Tanaka, Tadahiro Saito
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Patent number: 4429281Abstract: An integrator for use in a switched capacitor-filter, in which switching elements are connected to an input and to an output of an operational amplifier included in the integrator for clamping the input and output to a ground potential during suspension of the integral operation, in order to prevent potentials at the input and output of the operational amplifier from varying and hence ensure rapid stabilization of the integral operation of the integrator.Type: GrantFiled: December 5, 1980Date of Patent: January 31, 1984Assignee: Fujitsu LimitedInventors: Akihiko Ito, Kazuhiro Kobayashi, Hisami Tanaka, Norio Ueno
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Patent number: 4417158Abstract: A clock generator circuit for generating two pairs of clock signals comprises a NAND circuit and a NOR circuit cross-coupled to each other and each having an input for receiving a reference clock signal (.phi..sub.0). A first inverter is provided between the output of the NAND circuit and the other input of the NOR circuit, and a second inverter is provided between the output of the NOR circuit and the other input of the NAND circuit. A pair of clock signals (.phi..sub.2, .phi..sub.2) are generated from the NAND circuit and the first inverter, while another pair of clock signals (.phi..sub.1, .phi..sub.1) are generated from the NOR circuit and the second inverter.Type: GrantFiled: November 18, 1981Date of Patent: November 22, 1983Assignee: Fujitsu LimitedInventors: Akihiko Ito, Hisami Tanaka, Yoshihisa Takayama, Seiji Kato
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Patent number: D431580Type: GrantFiled: March 4, 1999Date of Patent: October 3, 2000Assignee: Advantest CorporationInventors: Akihiko Ito, Yoshihito Kobayashi