Patents by Inventor Akihiro HANADA

Akihiro HANADA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240128273
    Abstract: There is provided a technique that enables a reduction in the display failure of a display device and the improvement of the yields of the display device in a display device that adopts a semiconductor device including a thin film transistor using an oxide semiconductor. A semiconductor device according to an embodiment includes a thin film transistor having an oxide semiconductor. The oxide semiconductor has a drain region, a source region, and a channel region provided between the drain region and the source region. The thin film transistor includes a gate insulating film provided on the channel region, an aluminum oxide film provided on the gate insulating film, an insulating film provided on the aluminum oxide film, and a gate electrode provided on the insulating film.
    Type: Application
    Filed: December 22, 2023
    Publication date: April 18, 2024
    Inventors: Hajime WATAKABE, Toshihide JINNAI, Ryo ONODERA, Akihiro HANADA
  • Publication number: 20240113228
    Abstract: A semiconductor device according to an embodiment includes: an oxide insulating layer; an oxide semiconductor layer; a gate electrode; a gate insulating layer; and a first insulating layer, wherein the semiconductor device is divided into a first to a third regions, a thickness of the gate insulating layer in the first region is 200 nm or more, the gate electrode contacts the first insulating layer in the first region, the oxide semiconductor layer contacts the first insulating layer in the second region, an amount of impurities contained in the oxide semiconductor layer in the second region is greater than an amount of impurities contained in the oxide semiconductor layer in the first region, and an amount of impurities contained in the oxide insulating layer in the third region is greater than an amount of impurities contained in the oxide insulating layer in the second region.
    Type: Application
    Filed: October 3, 2023
    Publication date: April 4, 2024
    Applicant: Japan Display Inc.
    Inventors: Hajime WATAKABE, Masashi TSUBUKU, Toshinari SASAKI, Akihiro HANADA, Takaya TAMARU
  • Publication number: 20240113227
    Abstract: A method for manufacturing semiconductor device according to an embodiment includes: forming an oxide semiconductor layer above a substrate; forming a gate insulating layer above the oxide semiconductor layer; forming a metal oxide layer containing aluminum as a main component above the gate insulating layer; performing a heat treatment in a state where the metal oxide layer is formed above the gate insulating layer; removing the metal oxide layer after the heat treatment; and forming a gate electrode above the gate insulating layer.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 4, 2024
    Applicant: Japan Display Inc.
    Inventors: Hajime WATAKABE, Masashi TSUBUKU, Toshinari SASAKI, Akihiro HANADA, Takaya TAMARU
  • Patent number: 11942484
    Abstract: A semiconductor device includes an insulating substrate, a first semiconductor layer formed of silicon and positioned above the insulating substrate, a second semiconductor layer formed of a metal oxide and positioned above the first semiconductor layer, a first insulating film formed of a silicon nitride and positioned between the first semiconductor layer and the second semiconductor layer, and a block layer positioned between the first semiconductor film and the second semiconductor layer, the block layer hydrogen diffusion of which is lower than that of the first insulating film.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: March 26, 2024
    Assignee: Japan Display Inc.
    Inventors: Akihiro Hanada, Hajime Watakabe, Kazufumi Watabe
  • Publication number: 20240088192
    Abstract: The present invention provides a technology which realizes a reliable semiconductor device including a photosensor device by preventing pent roofs of edges of a P+ layer from being generated and a metal wiring installed over the P+ layer from coming down while securing the electrical conductivity of the P+ layer. The semiconductor device includes a photosensor including a photodiode formed on a substrate. The photodiode includes: a cathode electrode; a laminated structure that is formed on the cathode electrode and in which an N+ layer, an I layer, and a P+ layer are laminated in this order; an anode electrode formed on the P+ layer; a first insulating film formed so as to cover a portion of the anode electrode and edges of the laminated structure; and a metal wiring connected to the anode electrode. The edges of the laminated structure are formed in forward tapered shapes in a cross-sectional view.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 14, 2024
    Applicant: Japan Display Inc.
    Inventors: Hajime WATAKABE, Akihiro HANADA, Marina MOCHIZUKI, Ryo ONODERA, Fumiya KIMURA, Isao SUZUMURA
  • Publication number: 20240088166
    Abstract: According to one embodiment, a semiconductor device includes an insulating substrate, a first semiconductor layer located above the insulating substrate, a second semiconductor layer located above the insulating substrate, an insulating layer which covers the first semiconductor layer and the second semiconductor layer, and includes a first contact hole reaching the first semiconductor layer and a second contact hole reaching the second semiconductor layer, a barrier layer which covers one of the first semiconductor layer inside the first contact hole and the second semiconductor layer inside the second contact hole, and a first conductive layer which is in contact with the barrier layer.
    Type: Application
    Filed: November 15, 2023
    Publication date: March 14, 2024
    Applicant: Japan Display Inc.
    Inventors: Akihiro HANADA, Masayoshi FUCHI
  • Publication number: 20240085750
    Abstract: A display device includes a first substrate, a gate wiring on the first substrate, a first insulating layer on the gate wiring, a source wiring on the first insulating layer and intersecting the gate wiring, a second insulating layer on the source wiring, a pixel electrode on the second insulating layer; and a first buffer layer between the first substrate and the first insulating layer. A refractive index of the first buffer layer is higher than a refractive index of the first substrate, at an interface between the first buffer layer and the first substrate, and the refractive index of the first buffer layer is lower than a refractive index of the first insulating layer, at an interface between the first buffer layer and the first insulating layer.
    Type: Application
    Filed: August 11, 2023
    Publication date: March 14, 2024
    Applicant: Japan Display Inc.
    Inventors: Takuo KAITOH, Akihiro HANADA, Yoshinori TANAKA
  • Publication number: 20240069400
    Abstract: A display device including: a substrate; a first thin film transistor of polysilicon semiconductor, a second thin film transistor of oxide semiconductor; a first light shading film opposing to the polysilicon semiconductor, and a second light shading film opposing to the oxide semiconductor; a first insulating film, a second insulating film which is constituted from plural insulating films, and a third insulating film superposed in this order; a first through hole penetrating the second insulating film and not penetrating the first insulating film and the third insulating film; a second through hole penetrating the first insulating film and the third insulating film; the first light shading film connects with a first conductive component, a part of the first conductive component exists on the third insulating film, through the second through hole.
    Type: Application
    Filed: November 7, 2023
    Publication date: February 29, 2024
    Applicant: Japan Display Inc.
    Inventors: Akihiro HANADA, Toshihide JINNAI, Isao SUZUMURA, Hajime WATAKABE, Ryo ONODERA
  • Publication number: 20240069396
    Abstract: According to one embodiment, a display device includes a transparent semiconductor, a first insulating layer, a gate electrode, a second insulating layer, a source electrode, a third insulating layer, a transparent electrode which is in contact with the semiconductor in a second contact hole penetrating the first insulating layer, the second insulating layer and the third insulating layer, a fourth insulating layer, a color filter, and a pixel electrode electrically connected to the transparent electrode. The first insulating layer and the second insulating layer are silicon oxide layers. At least one of the third insulating layer and the fourth insulating layer is a silicon nitride layer.
    Type: Application
    Filed: August 29, 2023
    Publication date: February 29, 2024
    Applicant: Japan Display Inc.
    Inventors: Akihiro HANADA, Hitoshi TANAKA
  • Patent number: 11894387
    Abstract: There is provided a technique that enables a reduction in the display failure of a display device and the improvement of the yields of the display device in a display device that adopts a semiconductor device including a thin film transistor using an oxide semiconductor. A semiconductor device according to an embodiment includes a thin film transistor having an oxide semiconductor. The oxide semiconductor has a drain region, a source region, and a channel region provided between the drain region and the source region. The thin film transistor includes a gate insulating film provided on the channel region, an aluminum oxide film provided on the gate insulating film, an insulating film provided on the aluminum oxide film, and a gate electrode provided on the insulating film.
    Type: Grant
    Filed: May 18, 2022
    Date of Patent: February 6, 2024
    Assignee: Japan Display Inc.
    Inventors: Hajime Watakabe, Toshihide Jinnai, Ryo Onodera, Akihiro Hanada
  • Publication number: 20240038768
    Abstract: An object of the present invention is to provide a technology using which, in a thin film transistor using oxide semiconductor, the resistance of a channel region of the oxide semiconductor is made high, and at the same time the resistances of a source region and a drain region of the oxide semiconductor are made low. There is provided a semiconductor device including: a thin film transistor including oxide semiconductor, the oxide semiconductor including a channel region, a drain region, and a source region; a gate insulating film formed on the channel region; an aluminum oxide film formed on the gate insulating film; and a gate electrode formed on the aluminum oxide film, wherein the aluminum oxide film has a region that covers neither the drain region nor the source region in a plane view.
    Type: Application
    Filed: October 16, 2023
    Publication date: February 1, 2024
    Applicant: Japan Display Inc.
    Inventors: Akihiro HANADA, Toshihide JINNAI
  • Patent number: 11855103
    Abstract: According to one embodiment, a semiconductor device includes an insulating substrate, a first semiconductor layer located above the insulating substrate, a second semiconductor layer located above the insulating substrate, an insulating layer which covers the first semiconductor layer and the second semiconductor layer, and includes a first contact hole reaching the first semiconductor layer and a second contact hole reaching the second semiconductor layer, a barrier layer which covers one of the first semiconductor layer inside the first contact hole and the second semiconductor layer inside the second contact hole, and a first conductive layer which is in contact with the barrier layer.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: December 26, 2023
    Assignee: Japan Display Inc.
    Inventors: Akihiro Hanada, Masayoshi Fuchi
  • Patent number: 11855117
    Abstract: The present invention provides a technology which realizes a reliable semiconductor device including a photosensor device by preventing pent roofs of edges of a P+ layer from being generated and a metal wiring installed over the P+ layer from coming down while securing the electrical conductivity of the P+ layer. The semiconductor device includes a photosensor including a photodiode formed on a substrate. The photodiode includes: a cathode electrode; a laminated structure that is formed on the cathode electrode and in which an N+ layer, an I layer, and a P+ layer are laminated in this order; an anode electrode formed on the P+ layer; a first insulating film formed so as to cover a portion of the anode electrode and edges of the laminated structure; and a metal wiring connected to the anode electrode. The edges of the laminated structure are formed in forward tapered shapes in a cross-sectional view.
    Type: Grant
    Filed: February 4, 2021
    Date of Patent: December 26, 2023
    Assignee: JAPAN DISPLAY INC.
    Inventors: Hajime Watakabe, Akihiro Hanada, Marina Mochizuki, Ryo Onodera, Fumiya Kimura, Isao Suzumura
  • Patent number: 11846860
    Abstract: A display device including: a substrate; a first thin film transistor of polysilicon semiconductor, a second thin film transistor of oxide semiconductor; a first light shading film opposing to the polysilicon semiconductor, and a second light shading film opposing to the oxide semiconductor; a first insulating film, a second insulating film which is constituted from plural insulating films, and a third insulating film superposed in this order; a first through hole penetrating the second insulating film and not penetrating the first insulating film and the third insulating film; a second through hole penetrating the first insulating film and the third insulating film; the first light shading film connects with a first conductive component, a part of the first conductive component exists on the third insulating film, through the second through hole.
    Type: Grant
    Filed: February 6, 2023
    Date of Patent: December 19, 2023
    Assignee: Japan Display Inc.
    Inventors: Akihiro Hanada, Toshihide Jinnai, Isao Suzumura, Hajime Watakabe, Ryo Onodera
  • Publication number: 20230395724
    Abstract: A transistor includes a gate line, a first gate insulating film, a semiconductor film, a pair of terminals, a second gate insulating film, and a second gate electrode. A part of the gate line functions as a first gate electrode. The first gate insulating film is located over the first gate electrode. The semiconductor film is located over the first gate insulating film and overlaps the first gate electrode. The terminals are located over and electrically connected to the at least one semiconductor film. The second gate insulating film is located over the terminals. The second gate electrode has a light-transmitting property, is located over the second gate insulating film, overlaps the first gate electrode and the at least one semiconductor film, and is electrically connected to the first gate electrode through a first pair of openings formed in the first gate insulating film and the second gate insulating film.
    Type: Application
    Filed: May 17, 2023
    Publication date: December 7, 2023
    Applicant: Japan Display Inc.
    Inventor: Akihiro HANADA
  • Publication number: 20230387146
    Abstract: A display device including a substrate having thin film transistors (TFT) comprising: the TFT including an oxide semiconductor film, a gate electrode and an insulating film formed between the oxide semiconductor film and the gate electrode, wherein a first aluminum oxide film and a second aluminum oxide film, which is formed on the first aluminum oxide film, are formed between the insulating film and the gate electrode, an oxygen concentration in the first aluminum oxide film is bigger than an oxygen concentration in the second aluminum oxide film.
    Type: Application
    Filed: August 8, 2023
    Publication date: November 30, 2023
    Inventors: Hajime WATAKABE, Isao SUZUMURA, Akihiro HANADA, Yohei YAMAGUCHI
  • Publication number: 20230387320
    Abstract: A semiconductor device includes a first conductive layer, a first insulating layer on the first conductive layer, an oxide semiconductor layer on the first insulating layer, and second and third conductive layers on the oxide semiconductive layer. The oxide semiconductor layer includes a first region, a second region in contact with the second conductive layer, a third region in contact with the third conductive layer, a first impurity region between the first region and the second region, and a second impurity region between the first region and the third region. The first impurity region is in contact with the second conductive layer. The second impurity region is in contact with the third conductive layer. An electrical conductivity of each of the first impurity region and the second impurity region is greater than an electrical conductivity of each of the second region and the third region.
    Type: Application
    Filed: August 10, 2023
    Publication date: November 30, 2023
    Applicant: Japan Display Inc.
    Inventors: Akihiro HANADA, Hajime WATAKABE, Ryo ONODERA
  • Patent number: 11824063
    Abstract: An object of the present invention is to provide a technology using which, in a thin film transistor using oxide semiconductor, the resistance of a channel region of the oxide semiconductor is made high, and at the same time the resistances of a source region and a drain region of the oxide semiconductor are made low. There is provided a semiconductor device including: a thin film transistor including oxide semiconductor, the oxide semiconductor including a channel region, a drain region, and a source region; a gate insulating film formed on the channel region; an aluminum oxide film formed on the gate insulating film; and a gate electrode formed on the aluminum oxide film, wherein the aluminum oxide film has a region that covers neither the drain region nor the source region in a plane view.
    Type: Grant
    Filed: January 14, 2021
    Date of Patent: November 21, 2023
    Assignee: Japan Display Inc.
    Inventors: Akihiro Hanada, Toshihide Jinnai
  • Publication number: 20230350257
    Abstract: According to one embodiment, a display device includes a first substrate including a first transparent substrate, a switching element including an oxide semiconductor, an organic insulating film covering the switching element, a transparent electrode including a first aperture penetrating to an upper surface of the organic insulating film, an inorganic insulating film including a second aperture penetrating to the upper surface in the first aperture, and a pixel electrode electrically connected to the switching element, and a second substrate including a second transparent substrate and opposed to the first substrate.
    Type: Application
    Filed: July 10, 2023
    Publication date: November 2, 2023
    Inventors: Tatsunori MURAMOTO, Kentaro KAWAI, Yoshihide OHUE, Akihiro HANADA
  • Publication number: 20230317853
    Abstract: A semiconductor device includes thin film transistors each having an oxide semiconductor. The oxide semiconductor has a channel region, a drain region, a source region, and low concentration regions which are lower in impurity concentration than the drain region and the source region. The low concentration regions are located between the channel region and the drain region, and between the channel region and the source region. Each of the thin film transistors has a gate insulating film on the channel region and the low concentration regions, an aluminum oxide film on a first part of the gate insulating film, the first part being located on the channel region, and a gate electrode on the aluminum oxide film and a second part of the gate insulating film, the second part being located on the low concentration regions.
    Type: Application
    Filed: June 5, 2023
    Publication date: October 5, 2023
    Applicant: Japan Display Inc.
    Inventors: Hajime WATAKABE, Tomoyuki ITO, Toshihide JINNAI, lsao SUZUMURA, Akihiro HANADA, Ryo ONODERA