Patents by Inventor Akihiro HANADA

Akihiro HANADA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11764233
    Abstract: A display device including a substrate having thin film transistors (TFT) comprising: the TFT including an oxide semiconductor film, a gate electrode and an insulating film formed between the oxide semiconductor film and the gate electrode, wherein a first aluminum oxide film and a second aluminum oxide film, which is formed on the first aluminum oxide film, are formed between the insulating film and the gate electrode, an oxygen concentration in the first aluminum oxide film is bigger than an oxygen concentration in the second aluminum oxide film.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: September 19, 2023
    Assignee: Japan Display Inc.
    Inventors: Hajime Watakabe, Isao Suzumura, Akihiro Hanada, Yohei Yamaguchi
  • Publication number: 20230253506
    Abstract: According to one embodiment, a semiconductor device includes a first gate electrode formed to be integrated with a scanning line, an oxide semiconductor layer, a first signal line and a second signal line in contact with the oxide semiconductor layer, and a second gate electrode disposed opposing the first gate electrode with the oxide semiconductor layer interposed therebetween, and connected to the first gate electrode, wherein the second gate electrode does not overlap the first signal line, but overlaps the second signal line.
    Type: Application
    Filed: February 2, 2023
    Publication date: August 10, 2023
    Applicant: Japan Display Inc.
    Inventors: Ryo ONODERA, Akihiro HANADA, Takuo KAITOH, Tomoyuki ITO
  • Patent number: 11721765
    Abstract: A semiconductor device includes thin film transistors each having an oxide semiconductor. The oxide semiconductor has a channel region, a drain region, a source region, and low concentration regions which are lower in impurity concentration than the drain region and the source region. The low concentration regions are located between the channel region and the drain region, and between the channel region and the source region. Each of the thin film transistors has a gate insulating film on the channel region and the low concentration regions, an aluminum oxide film on a first part of the gate insulating film, the first part being located on the channel region, and a gate electrode on the aluminum oxide film and a second part of the gate insulating film, the second part being located on the low concentration regions.
    Type: Grant
    Filed: October 13, 2021
    Date of Patent: August 8, 2023
    Assignee: JAPAN DISPLAY INC.
    Inventors: Hajime Watakabe, Tomoyuki Ito, Toshihide Jinnai, Isao Suzumura, Akihiro Hanada, Ryo Onodera
  • Publication number: 20230231056
    Abstract: According to one embodiment, a semiconductor device includes a first gate electrode formed integrally with a scanning line, an oxide semiconductor layer, first and second signal lines which are in contact with the oxide semiconductor layer, and a second gate electrode provided so as to face the first gate electrode across the oxide semiconductor layer therebetween and connected to the first gate electrode. The second gate electrode is provided between the first signal line and the second signal line and does not overlap the first signal line or the second signal line.
    Type: Application
    Filed: January 17, 2023
    Publication date: July 20, 2023
    Applicant: Japan Display Inc.
    Inventor: Akihiro HANADA
  • Publication number: 20230185144
    Abstract: A display device including: a substrate; a first thin film transistor of polysilicon semiconductor, a second thin film transistor of oxide semiconductor; a first light shading film opposing to the polysilicon semiconductor, and a second light shading film opposing to the oxide semiconductor; a first insulating film, a second insulating film which is constituted from plural insulating films, and a third insulating film superposed in this order; a first through hole penetrating the second insulating film and not penetrating the first insulating film and the third insulating film; a second through hole penetrating the first insulating film and the third insulating film; the first light shading film connects with a first conductive component, a part of the first conductive component exists on the third insulating film, through the second through hole.
    Type: Application
    Filed: February 6, 2023
    Publication date: June 15, 2023
    Applicant: Japan Display Inc.
    Inventors: Akihiro HANADA, Toshihide JINNAI, Isao SUZUMURA, Hajime WATAKABE, Ryo ONODERA
  • Patent number: 11640088
    Abstract: A high definition display device is provided. The display device includes an array substrate, and an opposing substrate. The array substrate has a substrate, and on the substrate, a first pixel having a first color filter and a second pixel having a second color filter disposed adjacent to the first pixel. Each of the first color filter and the second color filter has a first dielectric layer, a transmissive layer disposed on the first dielectric layer, and a second dielectric layer disposed on the transmissive layer. The transmissive layer of the first color filter has a first film thickness, and the transmissive layer of the second color filter has a second film thickness larger than the first film thickness. On the transmissive layer of the second color filter, a first layer different from the transmissive layer is disposed on a side of the transmissive layer of the first color filter. A height of a bottom face of the first layer is equal to the first film thickness.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: May 2, 2023
    Assignee: JAPAN DISPLAY INC.
    Inventors: Ryo Onodera, Hajime Watakabe, Akihiro Hanada
  • Patent number: 11630361
    Abstract: A display device including: a substrate; a first thin film transistor of polysilicon semiconductor, a second thin film transistor of oxide semiconductor; a first light shading film opposing to the polysilicon semiconductor, and a second light shading film opposing to the oxide semiconductor; a first insulating film, a second insulating film which is constituted from plural insulating films, and a third insulating film superposed in this order; a first through hole penetrating the second insulating film and not penetrating the first insulating film and the third insulating film; a second through hole penetrating the first insulating film and the third insulating film; the first light shading film connects with a first conductive component, a part of the first conductive component exists on the third insulating film, through the second through hole.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: April 18, 2023
    Assignee: Japan Display Inc.
    Inventors: Akihiro Hanada, Toshihide Jinnai, Isao Suzumura, Hajime Watakabe, Ryo Onodera
  • Publication number: 20230108412
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer including a source area, a drain area and a channel area, a first insulating layer, an etching stopper layer located immediately above the channel area and being thinner than the first insulating layer, a second insulating layer provided on the etching stopper layer and being thicker than the first insulating layer, a gate electrode, a third insulating layer which covers the etching stopper layer, the second insulating layer and the gate electrode and covers the first insulating layer immediately above the source area and immediately above the drain area, a source electrode in contact with the source area, and a drain electrode in contact with the drain area.
    Type: Application
    Filed: October 3, 2022
    Publication date: April 6, 2023
    Applicant: Japan Display Inc.
    Inventors: Hajime WATAKABE, Masashi TSUBUKU, Kentaro MIURA, Akihiro HANADA, Takaya TAMARU
  • Patent number: 11609463
    Abstract: According to one embodiment, a display device includes a first substrate including a scanning line, a first inorganic insulating film, an oxide semiconductor, and a first light-shielding wall. The first inorganic insulating film, in planer view, includes a first groove formed between the oxide semiconductor and a light-emitting module. The first light-shielding wall is disposed on the first groove.
    Type: Grant
    Filed: April 19, 2022
    Date of Patent: March 21, 2023
    Assignee: JAPAN DISPLAY INC.
    Inventor: Akihiro Hanada
  • Publication number: 20230074655
    Abstract: A display device including a substrate having a first TFT of an oxide semiconductor and a second TFT of a polysilicon semiconductor comprising: the oxide semiconductor 109 is covered by a first insulating film, a first drain electrode 110 is connected to the oxide semiconductor 109 via a first through hole 132 formed in the first insulating film, a first source electrode 111 is connected to the oxide semiconductor 109 via second through hole 133 formed in the first insulating film in the first TFT, a second insulating film is formed covering the first drain electrode 110 and the first source electrode 111, a drain wiring connects 12 to the first drain electrode 110 via a third through hole 130 formed in the second insulating film, a source wiring 122 is connected to the first source electrode 111 via a fourth through hole 131 formed in the second insulating film.
    Type: Application
    Filed: November 16, 2022
    Publication date: March 9, 2023
    Applicant: Japan Display Inc.
    Inventors: Toshihide JINNAI, Hajime WATAKABE, Akihiro HANADA, Ryo ONODERA, lsao SUZUMURA
  • Publication number: 20230059822
    Abstract: According to one embodiment, a transistor includes a first gate electrode, a second gate electrode, an oxide semiconductor layer disposed between the first gate electrode and the second gate electrode, and a source electrode and a drain electrode each connected to the oxide semiconductor layer, wherein the oxide semiconductor layer includes a channel forming region, a source region, and a drain region, a light irradiation region which is made low-resistance by irradiating light thereto is each formed between the channel forming region and the source region and between the channel forming region and the drain region, and the first date electrode and the second gate electrode have different lengths.
    Type: Application
    Filed: August 17, 2022
    Publication date: February 23, 2023
    Applicant: Japan Display Inc.
    Inventors: Akihiro HANADA, Hajime WATAKABE
  • Publication number: 20230058988
    Abstract: According to one embodiment, a transistor includes a gate electrode, an oxide semiconductor layer which overlaps the gate electrode and including a central portion and an end portion, and a source electrode and a drain electrode each connected to the oxide semiconductor layer, wherein an oxidation degree of the end portion is lower than an oxidation degree of the central portion, and a length of the gate electrode overlapping the central portion is greater than a length of the gate electrode overlapping the end portion.
    Type: Application
    Filed: August 19, 2022
    Publication date: February 23, 2023
    Applicant: Japan Display Inc.
    Inventors: Akihiro HANADA, Hajime WATAKABE, Takeshi SAKAI
  • Publication number: 20230017598
    Abstract: According to one embodiment, a semiconductor device includes a gate electrode, a first insulating layer covering the gate electrode, an oxide semiconductor provided on the first insulating layer immediately above the gate electrode, a source electrode in contact with the oxide semiconductor, and a drain electrode in contact with the oxide semiconductor. Each of the source electrode and the drain electrode includes an oxide conductive layer in contact with the oxide semiconductor, a first metal layer stacked on the oxide conductive layer, a second metal layer formed of a different material from the first metal layer and stacked on the first metal layer, and a third metal layer formed of a same material as the first metal layer and stacked on the second metal layer.
    Type: Application
    Filed: July 12, 2022
    Publication date: January 19, 2023
    Applicant: Japan Display Inc.
    Inventors: Toshiki KANEKO, Akihiro HANADA
  • Publication number: 20230007861
    Abstract: According to one embodiment, a semiconductor device includes a first transistor which includes a an oxide semiconductor layer, and a second transistor connected to first and a second gate electrodes of the first transistor, wherein the oxide semiconductor layer is provided between the first and second gate electrodes in a cross-sectional view, the oxide semiconductor layer includes a first channel formation region overlapping the second gate electrode and a second channel formation region not overlapping the second gate electrode in a plan view, and a resistance value between the second gate electrode and the second transistor is higher than a resistance value between the first gate electrode and the second transistor.
    Type: Application
    Filed: July 7, 2022
    Publication date: January 12, 2023
    Applicant: Japan Display Inc.
    Inventors: Takeshi SAKAI, Hajime WATAKABE, Akihiro HANADA
  • Patent number: 11550195
    Abstract: A display device including a substrate having a first TFT of an oxide semiconductor and a second TFT of a polysilicon semiconductor comprising: the oxide semiconductor 109 is covered by a first insulating film, a first drain electrode 110 is connected to the oxide semiconductor 109 via a first through hole 132 formed in the first insulating film, a first source electrode 111 is connected to the oxide semiconductor 109 via second through hole 133 formed in the first insulating film in the first TFT, a second insulating film is formed covering the first drain electrode 110 and the first source electrode 111, a drain wiring connects 12 to the first drain electrode 110 via a third through hole 130 formed in the second insulating film, a source wiring 122 is connected to the first source electrode 111 via a fourth through hole 131 formed in the second insulating film.
    Type: Grant
    Filed: October 21, 2021
    Date of Patent: January 10, 2023
    Assignee: JAPAN DISPLAY INC.
    Inventors: Toshihide Jinnai, Hajime Watakabe, Akihiro Hanada, Ryo Onodera, Isao Suzumura
  • Publication number: 20220367691
    Abstract: According to one embodiment, a method of manufacturing a semiconductor device, includes forming a first insulating layer, an oxide semiconductor layer, a second insulating layer, a buffer layer and a metal layer sequentially on a base, forming a patterned resist on the metal layer, etching the buffer layer and the metal layer using the resist as a mask to expose an upper surface of the second insulating layer, reducing a volume of the resist to expose an upper surface along a side surface of the metal layer, etching the metal layer using the resist as a mask, to form a gate electrode and to expose an upper surface of the buffer layer, and carrying out ion implantation on the oxide semiconductor layer using the gate electrode as a mask.
    Type: Application
    Filed: April 26, 2022
    Publication date: November 17, 2022
    Applicant: Japan Display Inc.
    Inventors: Hajime WATAKABE, Masashi TSUBUKU, Kentaro MIURA, Akihiro HANADA, Takaya TAMARU
  • Publication number: 20220367528
    Abstract: A semiconductor device includes an insulating substrate, a first semiconductor layer formed of silicon and positioned above the insulating substrate, a second semiconductor layer formed of a metal oxide and positioned above the first semiconductor layer, a first insulating film formed of a silicon nitride and positioned between the first semiconductor layer and the second semiconductor layer, and a block layer positioned between the first semiconductor film and the second semiconductor layer, the block layer hydrogen diffusion of which is lower than that of the first insulating film.
    Type: Application
    Filed: July 28, 2022
    Publication date: November 17, 2022
    Applicant: Japan Display Inc.
    Inventors: Akihiro HANADA, Hajime WATAKABE, Kazufumi WATABE
  • Publication number: 20220342264
    Abstract: According to one embodiment, a display device includes a first substrate including a scanning line, a first inorganic insulating film, an oxide semiconductor, and a first light-shielding wall. The first inorganic insulating film, in planer view, includes a first groove formed between the oxide semiconductor and a light-emitting module. The first light-shielding wall is disposed on the first groove.
    Type: Application
    Filed: April 19, 2022
    Publication date: October 27, 2022
    Applicant: Japan Display Inc.
    Inventor: Akihiro HANADA
  • Patent number: 11442515
    Abstract: According to one embodiment, a semiconductor device includes an insulating substrate, a first semiconductor layer formed of silicon and positioned above the insulating substrate, a second semiconductor layer formed of a metal oxide and positioned above the first semiconductor layer, a first insulating film formed of a silicon nitride and positioned between the first semiconductor layer and the second semiconductor layer, and a block layer positioned between the first semiconductor film and the second semiconductor layer, the block layer hydrogen diffusion of which is lower than that of the first insulating film.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: September 13, 2022
    Assignee: JAPAN DISPLAY INC.
    Inventors: Akihiro Hanada, Hajime Watakabe, Kazufumi Watabe
  • Publication number: 20220278137
    Abstract: There is provided a technique that enables a reduction in the display failure of a display device and the improvement of the yields of the display device in a display device that adopts a semiconductor device including a thin film transistor using an oxide semiconductor. A semiconductor device according to an embodiment includes a thin film transistor having an oxide semiconductor. The oxide semiconductor has a drain region, a source region, and a channel region provided between the drain region and the source region. The thin film transistor includes a gate insulating film provided on the channel region, an aluminum oxide film provided on the gate insulating film, an insulating film provided on the aluminum oxide film, and a gate electrode provided on the insulating film.
    Type: Application
    Filed: May 18, 2022
    Publication date: September 1, 2022
    Inventors: Hajime WATAKABE, Toshihide JINNAI, Ryo ONODERA, Akihiro HANADA