Patents by Inventor Akinobu Teramoto

Akinobu Teramoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8906796
    Abstract: A method of producing a semiconductor transistor involving formation of an ohmic electrode on an active layer composed of a GaN-based semiconductor includes a process of forming a first layer 11 composed of tantalum nitride on an active layer 3 and a second layer 12 composed of Al layered on the first layer 11 and a process of forming ohmic electrodes 9s and 9d in ohmic contact with the active layer 3 by heat treating the first layer 11 and the second layer 12 at a temperature of from 520° C. to 600° C.
    Type: Grant
    Filed: March 2, 2011
    Date of Patent: December 9, 2014
    Assignee: Tohoku University
    Inventors: Hiroshi Kambayashi, Akinobu Teramoto, Tadahiro Ohmi
  • Patent number: 8895410
    Abstract: A cause of deteriorating the hydrogen termination on the surface of a wafer is found to be water adsorbed on the surface. By exposing the wafer to an inert gas atmosphere containing an H2 gas so as to suppress the oxidation reaction due to the water, it is possible to improve the hydrogen termination on the wafer surface.
    Type: Grant
    Filed: September 13, 2005
    Date of Patent: November 25, 2014
    Inventors: Tadahiro Ohmi, Akinobu Teramoto, Hiroshi Akahori
  • Publication number: 20140312399
    Abstract: A gate insulating film of a conventional semiconductor device is subjected to dielectric breakdown at a low electric field strength and thus its service life is short. This is because since the size of the asperity of at least one of a semiconductor layer-side interface and an electrode-side interface is large and, an electric field applied to the gate insulating film is locally concentrated and has a variation in its strength. This problem is solved by specifying the sizes of the asperities of both interfaces of the gate insulating film.
    Type: Application
    Filed: November 16, 2012
    Publication date: October 23, 2014
    Applicant: TOHOKU UNIVERSITY
    Inventors: Rihito Kuroda, Akinobu Teramoto, Shigetoshi Sugawa
  • Publication number: 20140306344
    Abstract: There is provided with a wiring structure. The wiring stracture has a damascene wiring structure including a metal wiring. The metal wiring is provided in direct contact with an upper surface of a barrier film (SiC(O, N) film) containing silicon (Si), carbon (C), and at least one of oxygen (O) and nitrogen (N) as constituent components.
    Type: Application
    Filed: June 24, 2014
    Publication date: October 16, 2014
    Applicant: Tohoku University
    Inventors: Shigetoshi Sugawa, Akinobu Teramoto, Rihito Kuroda, Gu Xun
  • Patent number: 8841545
    Abstract: Disclosed is a solar cell comprising a solar cell semiconductor thin film formed on a base, a transparent conductive film formed on the semiconductor thin film, and a nitride-containing moisture diffusion-preventing film which covers the upper surface of the transparent conductive film. The moisture diffusion-preventing film is preferably composed of at least a silicon nitride film or a silicon carbide nitride (SiCN) film.
    Type: Grant
    Filed: February 10, 2009
    Date of Patent: September 23, 2014
    Assignees: Tohoku University, Tokyo Electron Limited
    Inventors: Yoshihide Wakayama, Kazuki Moyama, Tadahiro Ohmi, Akinobu Teramoto
  • Publication number: 20140225263
    Abstract: During the production of a semiconductor device having a Cu wiring line of a damascene structure, diffusion of fluorine from a CF film that serves as an interlayer insulating film is prevented in cases where a heat treatment is carried out, thereby suppressing increase in the leakage current. A semiconductor device of the present invention having a damascene wiring structure is provided with: an interlayer insulating film (2) that is formed of, for example, a fluorine-added carbon film; and a copper wiring line (4) that is embedded in the interlayer insulating film. A barrier metal layer (6) close to the copper wiring line and a fluorine barrier film (5) close to the interlayer insulating film are formed between the interlayer insulating film and the copper wiring line.
    Type: Application
    Filed: September 6, 2012
    Publication date: August 14, 2014
    Applicants: TOHOKU UNIVERSITY, TOKYO ELECTRON LIMITED
    Inventors: Takenao Nemoto, Akinobu Teramoto, Xun Gu
  • Patent number: 8716114
    Abstract: A semiconductor device manufacturing method includes exciting plasma, applying RF power onto a target substrate to generate substrate bias and performing an ion implantation plural times by applying the RF power in the form of pulses.
    Type: Grant
    Filed: February 14, 2013
    Date of Patent: May 6, 2014
    Assignees: National University Corporation Tohoku University, Tokyo Electron Limited
    Inventors: Tadahiro Ohmi, Tetsuya Goto, Akinobu Teramoto, Takaaki Matsuoka
  • Patent number: 8664909
    Abstract: A miniaturizable, low-cost highly reliable inverter unit. A control circuit section for controlling operating timing of high breakdown voltage semiconductor elements included in an inverter circuit section and first and second drive and abnormality detection circuit sections for outputting drive signals for driving the high breakdown voltage semiconductor elements according to the operating timing and for feeding back an abnormality of the inverter circuit section to the control circuit section are formed on an SOI substrate as one integrated circuit chip. On the integrated circuit chip, circuit formation areas which differ in reference potential are separated from one another by dielectrics. A plurality of level shifters for transmitting signals exchanged between circuit formation areas separated by the dielectrics are formed.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: March 4, 2014
    Assignees: Fuji Electric Co., Ltd., Honda Motor Co., Ltd., Sharp Kabushiki-Kaisha
    Inventors: Hitoshi Sumida, Akinobu Teramoto, Ken-ichi Nonaka, Toshio Naka
  • Patent number: 8648393
    Abstract: An accumulation mode transistor has an impurity concentration of a semiconductor layer in a channel region at a value higher than 2×1017 cm?3 to achieve a large gate voltage swing.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: February 11, 2014
    Assignees: National University Corporation Tohoku University, Foundation for Advancement of International Science
    Inventors: Tadahiro Ohmi, Akinobu Teramoto, Rihito Kuroda
  • Patent number: 8643106
    Abstract: A transistor capable of adjusting a threshold value is obtained by adjusting an impurity concentration of a silicon substrate supporting an SOI layer and by controlling a thickness of a buried insulating layer formed on a surface of the silicon substrate in contact with the SOI layer.
    Type: Grant
    Filed: June 21, 2007
    Date of Patent: February 4, 2014
    Assignees: National University Corporation Tohoku University, Foundation for Advancement of International Science
    Inventors: Tadahiro Ohmi, Akinobu Teramoto, Cheng Weitao
  • Patent number: 8633395
    Abstract: A multilayer wiring board 100 comprises a first wiring region 101 where wirings 103a and insulating layers 104a and 104b are alternately laminated, and a second wiring region 102 where a thickness H2 of an insulating layer 104 is twice or more a thickness H1 of the insulating layer in the first wiring region 101 and a width W2 of a wiring 103b is twice or more a width W1 of the wiring in the first wiring region 101. The first wiring region 101 and the second wiring region 102 are integrally formed on the same board.
    Type: Grant
    Filed: May 22, 2009
    Date of Patent: January 21, 2014
    Assignees: National University Corporation Tohoku University, Foundation For Advancement of International Science
    Inventors: Tadahiro Ohmi, Shigetoshi Sugawa, Hiroshi Imai, Akinobu Teramoto
  • Publication number: 20130309828
    Abstract: Provided is a semiconductor device manufacturing method, comprising forming a first sacrificial layer that contacts at least a portion of a first semiconductor layer and has a higher solid solubility for impurities included in the first semiconductor layer than the first semiconductor layer; annealing the first sacrificial layer and the first semiconductor layer; removing the first sacrificial layer through a wet process; after removing the first sacrificial layer, performing at least one of forming an insulating layer that covers at least a portion of the first semiconductor layer and etching a portion of the first semiconductor layer; and forming an electrode layer that is electrically connected to the first semiconductor layer.
    Type: Application
    Filed: July 24, 2013
    Publication date: November 21, 2013
    Applicants: Tohoku University, Advanced Power Device Research Association
    Inventors: Hiroshi KAMBAYASHI, Akinobu TERAMOTO, Tadahiro OHMI
  • Publication number: 20130307063
    Abstract: Provided is a method of manufacturing a gallium-nitride-based semiconductor device, comprising forming a first semiconductor layer of a gallium-nitride-based semiconductor; and forming a recessed portion by dry etching a portion of the first semiconductor layer via a microwave plasma process using a bromine-based gas.
    Type: Application
    Filed: July 24, 2013
    Publication date: November 21, 2013
    Applicants: TOHOKU UNIVERSITY, ADVANCED POWER DEVICE RESEARCH ASSOCIATION
    Inventors: Hiroshi KAMBAYASHI, Akinobu TERAMOTO, Tadahiro OHMI
  • Publication number: 20130295709
    Abstract: “The invention provides a photoelectric conversion element manufacturing apparatus that forms a semiconductor stack film on a substrate by using microwave plasma CVD. The apparatus includes a chamber which is a enclosed space containing a base, on which the a subject substrate for thin-film formation is mounted, a first gas supply unit which supplies plasma excitation gas to a plasma excitation region in the chamber, a pressure regulation unit which regulates pressure in the chamber, a second gas supply unit which supplies raw gas to a plasma diffusion region in the chamber, a microwave application unit which applies microwaves into the chamber, and a bias voltage application unit which selects and applies a substrate bias voltage to the substrate according to the type of gas.
    Type: Application
    Filed: May 23, 2013
    Publication date: November 7, 2013
    Inventors: Tadahiro OHMI, Akinobu TERAMOTO, Tetsuya GOTO, Kouji TANAKA
  • Publication number: 20130292700
    Abstract: A method for fabricating a semiconductor device including GaN (gallium nitride) that composes a semiconductor layer and includes forming a gate insulating film, in which at least one film selected from the group of a SiO2 film and an Al2O3 film is formed on a nitride layer containing GaN by using microwave plasma and the formed film is used as at least a part of the gate insulating film.
    Type: Application
    Filed: January 23, 2012
    Publication date: November 7, 2013
    Applicants: TOHOKU UNIVERSITY, TOKYO ELECTRON LIMTED, Advanced Power Device Research Association
    Inventors: Akinobu Teramoto, Hiroshi Kambayashi, Hirokazu Ueda, Yuichiro Morozumi, Katsushige Harada, Kazuhide Hasebe, Tadahiro Ohmi
  • Patent number: 8575023
    Abstract: A semiconductor device manufacturing method which achieves a contact of a low resistivity is provided. In a state where a first metal layer in contact with a semiconductor is covered with a second metal layer for preventing oxidation, only the first metal layer is silicided to form a silicide layer with no oxygen mixed therein. As a material of the first metal layer, a metal having a work function difference of a predetermined value from the semiconductor is used. As a material of the second metal layer, a metal which does not react with the first metal layer at an annealing temperature is used.
    Type: Grant
    Filed: October 23, 2009
    Date of Patent: November 5, 2013
    Assignees: National University Corporation Tohoku University, Foundation for Advancement of International Science
    Inventors: Tadahiro Ohmi, Akinobu Teramoto, Tatsunori Isogai, Hiroaki Tanaka
  • Patent number: 8497214
    Abstract: A semiconductor device manufacturing method, the method including: forming a semiconductor element on a semiconductor substrate; and by using microwaves as a plasma source, forming an insulation film on the semiconductor element by performing a CVD process using microwave plasma having an electron temperature of plasma lower than 1.5 eV and an electron density of plasma higher than 1×1011 cm?3 near a surface of the semiconductor substrate.
    Type: Grant
    Filed: August 7, 2008
    Date of Patent: July 30, 2013
    Assignees: Tokyo Electron Limited, National University Corporation Tohoku University
    Inventors: Hirokazu Ueda, Toshihisa Nozawa, Takaaki Matsuoka, Akinobu Teramoto, Tadahiro Ohmi
  • Patent number: 8492879
    Abstract: On a surface of a semiconductor substrate, a plurality of terraces formed stepwise by an atomic step are formed in the substantially same direction. Using the semiconductor substrate, a MOS transistor is formed so that no step exists in a carrier traveling direction (source-drain direction).
    Type: Grant
    Filed: October 6, 2008
    Date of Patent: July 23, 2013
    Assignees: National University Corporation Tohoku University, Shin-Etsu Handotai Co., Ltd.
    Inventors: Tadahiro Ohmi, Akinobu Teramoto, Tomoyuki Suwa, Rihito Kuroda, Hideo Kudo, Yoshinori Hayamizu
  • Patent number: 8465719
    Abstract: A silicon carbide substrate has a high-frequency loss equal to or less than 2.0 dB/mm at 20 GHz is effective to mount and operate electronic components. The silicon carbide substrate is heated at 2000° C. or more to be reduced to the high-frequency loss equal to 2.0 dB/mm or less at 20 GHz. Moreover, manufacturing the silicon carbide substrate by CVD without flowing nitrogen into a heater enables the high-frequency loss to be reduced to 2.0 dB/mm or less.
    Type: Grant
    Filed: April 16, 2009
    Date of Patent: June 18, 2013
    Assignees: National University Corporation Tohoku University, Mitsui Engineering & Shipbuilding Co., Ltd.
    Inventors: Tadahiro Ohmi, Akinobu Teramoto, Sumio Sano, Fusao Fujita
  • Patent number: 8405343
    Abstract: A miniaturizable, low-cost highly reliable inverter unit. A control circuit section for controlling operating timing of high breakdown voltage semiconductor elements included in an inverter circuit section and first and second drive and abnormality detection circuit sections for outputting drive signals for driving the high breakdown voltage semiconductor elements according to the operating timing and for feeding back an abnormality of the inverter circuit section to the control circuit section are formed on an SOI substrate as one integrated circuit chip. On the integrated circuit chip, circuit formation areas which differ in reference potential are separated from one another by dielectrics. A plurality of level shifters for transmitting signals exchanged between circuit formation areas separated by the dielectrics are formed.
    Type: Grant
    Filed: May 19, 2011
    Date of Patent: March 26, 2013
    Assignees: Fuji Electric Systems Co., Ltd., Honda Motor Co., Ltd., Sharp Kabushiki-Kaisha
    Inventors: Hitoshi Sumida, Akinobu Teramoto, Ken-ichi Nonaka, Toshio Naka