Abstract: Disclosed is a method for cleaning a semiconductor substrate that can solve a problem of a conventional cleaning method which should include at least five steps for cleaning a substrate such as a semiconductor substrate. The method for cleaning a semiconductor substrate comprises a first step of cleaning a substrate with ultrapure water containing ozone, a second step of cleaning the substrate with ultrapure water containing a surfactant, and a third step of removing an organic compound derived from the surfactant, with a cleaning liquid containing ultrapure water and 2-propanol. After the third step, plasma of noble gas such as krypton is applied to the substrate to further remove the organic compound derived from the surfactant.

Abstract: This invention provides a composite material useful for size reduction of electronic components and circuit boards mounted on electronic equipment and exhibiting a low magnetic loss (tan ?), and a manufacturing method thereof. The composite material contains an insulating material and particulates dispersed in this insulating material, the particulates being previously coated with an insulating material having substantially the same composition as that of the coating insulating material. The particulates consist of an organic or inorganic substance and preferably have a flat shape. The insulating material may be an insulating material commonly used in the field of electronic components. The composite material of the invention is preferably manufactured by a manufacturing method in which the particulates are previously coated with an insulating material and dispersed in an insulating material having substantially the same composition as that of the coating insulating material.

Abstract: There is provided a wafer on which a plurality of electronic devices and circuits under test are to be formed, where each circuit under test includes a plurality of transistors under measurement provided in electrically parallel, a selecting section which sequentially selects the respective transistors under measurement, and an output section which sequentially outputs the source voltages of the transistors under measurement sequentially selected by the selecting section.

Abstract: For equalizing the rising and falling operating speeds in a CMOS circuit, it is necessary to make the areas of a p-type MOS transistor and an n-type MOS transistor different from each other due to a difference in carrier mobility therebetween. This area unbalance prevents an improvement in integration degree of semiconductor devices. The NMOS transistor and the PMOS transistor each have a three-dimensional structure with a channel region on both the (100) plane and the (110) plane so that the areas of the channel regions and gate insulating films of both transistors are equal to each other. Accordingly, it is possible to make the areas of the gate insulating films and so on equal to each other and also to make the gate capacitances equal to each other. Further, the integration degree on a substrate can be improved twice as much as that in the conventional technique.

Abstract: There is provided a wafer on which a plurality of electronic devices and circuits under test are to be formed, where each circuit under test includes a plurality of transistors under measurement provided in electrically parallel, a selecting section which sequentially selects the respective transistors under measurement, and an output section which sequentially outputs the source voltages of the transistors under measurement sequentially selected by the selecting section.

Abstract: Disclosed is a solar cell comprising a solar cell semiconductor thin film formed on a base, a transparent conductive film formed on the semiconductor thin film, and a nitride-containing moisture diffusion-preventing film which covers the upper surface of the transparent conductive film. The moisture diffusion-preventing film is preferably composed of at least a silicon nitride film or a silicon carbide nitride (SiCN) film.

Abstract: An electronic device that includes an actual operation circuit that operates during an actual operation of the electronic device, a second test circuit and a third test circuit that operate during a test of the electronic device, and a power supply section. The power supply section, during the actual operation of the electronic device, does not apply a power supply voltage to the second test circuit and applies power supply voltages to the actual operation circuit and the third test circuit. The power supply section, to obtain identification of the electronic device, applies a power supply voltage to the second test circuit.

Abstract: Provided is a method for managing manufacturing apparatuses used in a managed production line including a plurality of manufacturing processes for manufacturing an electronic device, each of the apparatuses being used in one or more of the processes. The method includes acquiring a property of a reference device manufactured in a predetermined reference production line including the manufacturing processes to be performed, performing at least one of the manufacturing processes in the managed production line, performing the other manufacturing processes in the reference production line, and manufacturing a comparison device. The method further includes measuring a property of the comparison device, comparing the measured properties of the reference and the comparison devices, and judging whether a manufacturing apparatus used in the at least one manufacturing process in the managed production line is defective or not, based on a property difference between the reference and the comparison devices.

Abstract: A bonding apparatus including a chamber for maintaining an inert gas atmosphere; a first plasma torch for performing a surface treatment on pads and electrodes, the first plasma torch being attached in the chamber, to apply gas plasma to a substrate and a semiconductor chip that is placed inside the chamber; a second plasma torch for performing a surface treatment on an initial ball and/or wire at a tip end of a capillary that is positioned inside the chamber, the second plasma torch being attached in the chamber, to apply gas plasma to the initial ball and/or wire; and a bonding unit for bonding the surface-treated initial ball and/or wire to the surface-treated pads and electrodes in the chamber, thereby cleaning of the surface of the electrodes and pads as well as the wire can be effectively performed.

Abstract: An apparatus and method for manufacturing photoelectric conversion elements, and a photoelectric conversion element, the apparatus and method being capable of highly efficiently forming a film at a high speed with microwave plasma, preventing oxygen from mixing, and reducing the number of defects. The invention provides a photoelectric conversion element manufacturing apparatus 100 that forms a semiconductor stack film on a substrate by using microwave plasma CVD.

Abstract: A film with small hysteresis and high voltage resistance is obtained by reducing the carbon content in a gate insulating film on a SiC substrate. Specifically, the carbon content in the gate insulating film is set to 1×1020 atoms/cm3 or less. For this, using a plasma processing apparatus, a silicon oxide film is formed on the SiC substrate and then the formed silicon oxide film is reformed by exposure to radicals containing nitrogen atoms. Thus, the gate insulating film excellent in electrical properties is obtained.

Abstract: There is provided a device identifying method for identifying an electronic device including therein an actual operation circuit and a test circuit having a plurality of test elements provided therein, where the actual operation circuit operates during an actual operation of the electronic device and the test circuit operates during a test of the electronic device.

Abstract: [Problem] To improve polishing efficiency while lowering shear force added to semiconductor wafers while increasing polishing speed, without damaging the wafer's processing surface or the membrane under it. [Solution Method] Pressing the revolving head or carrier 34 that holds fixed the semiconductor wafer 10 to the polishing pad or polishing cloth 30 attached to rotating polishing table 32 in this CMP device and while rotating carrier 34 and polishing table 32 respectively, and supplying liquid slurry to polishing pad 30 from nozzle 36, planarization by chemical processes and mechanical processes is carried out by removing membranes of the lower face of semiconductor wafer 10 (the processing surface). The chemical mechanical polishing process of the present invention in regard to the size of the relationship between the rotation rate of semiconductor wafer 10 fW and the number of rotations of polishing pad 30 fP has 3 fp<fW as its lower limit and 4 fp<fW<8 fp is ideal conditions.

Abstract: In order to obtain substantially the same operating speed of a p-type MOS transistor and an n-type MOS transistor forming a CMOS circuit, the n-type MOS transistor has a three-dimensional structure having a channel region on both the (100) plane and the (110) plane and the p-type MOS transistor has a planar structure having a channel region only on the (110) plane. Further, both the transistors are substantially equal to each other in the areas of the channel regions and gate insulating films. Accordingly, it is possible to make the areas of the gate insulating films and so on equal to each other and also to make the gate capacitances equal to each other.

Abstract: A semiconductor device manufacturing method, the method including: forming a semiconductor element on a semiconductor substrate; and by using microwaves as a plasma source, forming an insulation film on the semiconductor element by performing a CVD process using microwave plasma having an electron temperature of plasma lower than 1.5 eV and an electron density of plasma higher than 1×1011 cm?3 near a surface of the semiconductor substrate.

Abstract: On a surface of a semiconductor substrate, a plurality of terraces formed stepwise by an atomic step are formed in the substantially same direction. Using the semiconductor substrate, a MOS transistor is formed so that no step exists in a carrier traveling direction (source-drain direction).

Abstract: There is provided a manufacturing system for manufacturing an electronic device through a plurality of manufacturing stages. The manufacturing system includes a plurality of manufacturing apparatuses performing processes corresponding to the plurality of manufacturing stages.

Abstract: A base is formed of a material, such as SiC, having mechanical characteristics higher than those of silicon for forming a semiconductor layer, and the base and the semiconductor layer are bonded through an insulating layer. After bonding, an SOI substrate is formed by mechanically separating the semiconductor layer from the base, and the separated semiconductor layer is reused for forming the subsequent SOI substrate. Thus, a large SOI substrate having a diameter of 400 mm or more, which has been difficult to obtain by conventional methods, can be obtained.

Abstract: A cause of deteriorating the hydrogen termination on the surface of a wafer is found to be water adsorbed on the surface. By exposing the wafer to an inert gas atmosphere containing an H2 gas so as to suppress the oxidation reaction due to the water, it is possible to improve the hydrogen termination on the wafer surface.

Abstract: A method of determining pattern evolution of a semiconductor wafer during chemical mechanical polishing prior to polishing end point by determining the periodic change in the variance and FT or FFT frequency spectra of shear force and change in variance and FT or FFT frequency spectra of COF, shear force and/or down force between the semiconductor wafer and the polishing pad.