Patents by Inventor Akinobu Teramoto

Akinobu Teramoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8399862
    Abstract: When positively charged ions are implanted into a target substrate, charge-up damage may occur on the target substrate. In order to suppress charge-up caused by secondary electrons emitted from the target substrate when positively charged ions are implanted, a conductive member is installed at a position facing the target substrate and electrically grounded with respect to a high frequency. Further, a field intensity generated in the target substrate may be reduced by controlling an RF power applied to the target substrate in pulse mode.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: March 19, 2013
    Assignees: National University Corporation Tohoku University, Tokyo Electron Limited
    Inventors: Tadahiro Ohmi, Tetsuya Goto, Akinobu Teramoto, Takaaki Matsuoka
  • Publication number: 20130052816
    Abstract: A method of producing a semiconductor transistor involving formation of an ohmic electrode on an active layer composed of a GaN-based semiconductor includes a process of forming a first layer 11 composed of tantalum nitride on an active layer 3 and a second layer 12 composed of Al layered on the first layer 11 and a process of forming ohmic electrodes 9s and 9d in ohmic contact with the active layer 3 by heat treating the first layer 11 and the second layer 12 at a temperature of from 520° C. to 600° C.
    Type: Application
    Filed: March 2, 2011
    Publication date: February 28, 2013
    Applicants: TOHOKU UNIVERISTY, ADVANCED POWER DEVICE RESEARCH ASSOCIATION
    Inventors: Hiroshi Kambayashi, Akinobu Teramoto, Tadahiro Ohmi
  • Publication number: 20130032819
    Abstract: The semiconductor transistor according the present invention includes an active layer composed of a GaN-based semiconductor and a gate insulating film formed on the active layer. The gate insulating film has a first insulating film including one or more compounds selected from the group consisting of Al2O3, HfO2, ZrO2, La2O3, and Y2O3 formed on the active layer, and a second insulating film composed of SiO2 formed on the first insulating film.
    Type: Application
    Filed: March 2, 2011
    Publication date: February 7, 2013
    Applicants: TOHOKU UNIVERISTY, ADVANCED POWER DEVICE RESEARCH ASSOCIATION
    Inventors: Hiroshi Kambayashi, Katsunori Ueno, Takehiko Nomura, Yoshihiro Sato, Akinobu Teramoto, Tadahiro Ohmi
  • Patent number: 8362567
    Abstract: In a semiconductor device, the degree of flatness of 0.3 nm or less in terms of a peak-to-valley (P-V) value is realized by rinsing a silicon surface with hydrogen-added ultrapure water in a light-screened state and in a nitrogen atmosphere and a contact resistance of 10?11 ?cm2 or less is realized by setting a work function difference of 0.2 eV or less between an electrode and the silicon. Thus, the semiconductor device can operate on a frequency of 10 GHz or higher.
    Type: Grant
    Filed: July 12, 2007
    Date of Patent: January 29, 2013
    Assignees: National University Corporation Tohoku University, Foundation for Advancement of International Science
    Inventors: Tadahiro Ohmi, Akinobu Teramoto, Rihito Kuroda
  • Publication number: 20130001280
    Abstract: Metal nanoink for bonding an electrode of a semiconductor die and an electrode of a substrate and/or bonding an electrode of a semiconductor die and an electrode of another semiconductor die by sintering under pressure is produced by injecting oxygen into an organic solvent in the form of oxygen nanobubbles or oxygen bubbles either before or after metal nanoparticles whose surfaces are coated with a dispersant are mixed into the organic solvent. Bumps are formed on the electrode of the semiconductor die and the electrode of the substrate by ejecting microdroplets of the metal nanoink onto the electrodes, the semiconductor die is turned upside down and overlapped in alignment over the substrate, and then, the metal nanoparticles of the bumps are sintered under pressure by pressing and heating the bumps between the electrodes. As a result, generation of voids during sintering under pressure is minimized.
    Type: Application
    Filed: August 21, 2012
    Publication date: January 3, 2013
    Applicants: SHINKAWA LTD., ULVAC, INC., TOHOKU UNIVERSITY
    Inventors: Toru MAEDA, Tetsuro TANIKAWA, Akinobu TERAMOTO, Masaaki ODA
  • Patent number: 8328928
    Abstract: Metal nanoink (100) for bonding an electrode of a semiconductor die and an electrode of a substrate and/or bonding an electrode of a semiconductor die and an electrode of another semiconductor die by sintering under pressure is produced by injecting oxygen into an organic solvent (105) in the form of oxygen nanobubbles (125) or oxygen bubbles (121) either before or after metal nanoparticles (101) whose surfaces are coated with a dispersant (102) are mixed into the organic solvent (105). Bumps are formed on the electrode of the semiconductor die and the electrode of the substrate by ejecting microdroplets of the metal nanoink (100) onto the electrodes, the semiconductor die is turned upside down and overlapped in alignment over the substrate, and then, the metal nanoparticles of the bumps are sintered under pressure by pressing and heating the bumps between the electrodes. As a result, generation of voids during sintering under pressure is minimized.
    Type: Grant
    Filed: July 8, 2009
    Date of Patent: December 11, 2012
    Assignees: Shinkawa Ltd., Tohoku University, Ulvac, Inc.
    Inventors: Toru Maeda, Tetsuro Tanikawa, Akinobu Teramoto, Masaaki Oda
  • Publication number: 20120308714
    Abstract: In a deposited thin film for use in a semiconductor device or the like, adsorption of contaminants is a problem. In the case in which a gas pressure in a chamber is maintained in a viscous flow region, the adsorption of the organic substances is significantly decreased as compared with the case in which the gas pressure is maintained in a molecular flow region. The gas pressure is controlled so that it can be set in the molecular flow region when forming the deposited thin film, and set in the viscous flow region when such deposition is not being performed. Thus, the deposited thin film is formed with less contamination from the organic substances.
    Type: Application
    Filed: June 7, 2012
    Publication date: December 6, 2012
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Tadahiro OHMI, Akinobu TERAMOTO
  • Publication number: 20120292743
    Abstract: In a silicon wafer which has a surface with a plurality of terraces formed stepwise by single-atomic-layer steps, respectively, no slip line is formed.
    Type: Application
    Filed: August 3, 2012
    Publication date: November 22, 2012
    Inventors: Tadahiro OHMI, Akinobu TERAMOTO, Tomoyuki SUWA
  • Patent number: 8314449
    Abstract: A MIS transistor, formed on a semiconductor substrate, assumed to comprise a semiconductor substrate (702, 910) comprising a projecting part (704, 910B) with at least two different crystal planes on the surface on a principal plane, a gate insulator (708, 920B) for covering at least a part of each of said at least two different crystal planes constituting the surface of the projecting part, a gate electrode (706, 930B), comprised on each of said at least two different crystal planes constituting the surface of the projecting part, which sandwiches the gate insulator with the said at least two different planes, and a single conductivity type diffusion region (710a, 710b, 910c, 910d) formed in the projecting part facing each of said at least two different crystal planes and individually formed on both sides of the gate electrode. Such a configuration allows control over increase in the element area and increase of channel width.
    Type: Grant
    Filed: October 22, 2009
    Date of Patent: November 20, 2012
    Assignee: Foundation For Advancement Of International Science
    Inventors: Takefumi Nishimuta, Hiroshi Miyagi, Tadahiro Ohmi, Shigetoshi Sugawa, Akinobu Teramoto
  • Publication number: 20120234491
    Abstract: A plasma processing apparatus in which consumption of expensive krypton and xenon gases is suppressed as much as possible while reducing damage on a workpiece during plasma processing. In plasma processing of a substrate using a rare gas, two or more kinds of different rare gases are employed, and an inexpensive argon gas is used as one rare gas and any one or both of krypton and xenon gases having a larger collision cross-sectional area against electron than that of the argon gas is used as the other gas. Consequently, consumption of expensive krypton and xenon gases is suppressed as much as possible and damage on a workpiece is reduced during plasma processing.
    Type: Application
    Filed: May 11, 2012
    Publication date: September 20, 2012
    Inventors: Tadahiro OHMI, Akinobu Teramoto
  • Publication number: 20120208375
    Abstract: In a semiconductor device formed on a silicon surface which has a substantial (110) crystal plane orientation, the silicon surface is flattened so that an arithmetical mean deviation of surface Ra is not greater than 0.15 nm, preferably, 0.09 nm, which enables to manufacture an n-MOS transistor of a high mobility. Such a flattened silicon surface is obtained by repeating a deposition process of a self-sacrifice oxide film in an oxygen radical atmosphere and a removing process of the self-sacrifice oxide film, by cleaning the silicon surface in deaerated H2O or a low OH density atmosphere, or by strongly terminating the silicon surface by hydrogen or heavy hydrogen. The deposition process of the self-sacrifice oxide film may be carried out by isotropic oxidation.
    Type: Application
    Filed: April 23, 2012
    Publication date: August 16, 2012
    Inventors: Tadahiro Ohmi, Shigetoshi Sugawa, Akinobu Teramoto, Hiroshi Akahori, Keiichi Nii
  • Patent number: 8217270
    Abstract: A multilayered circuit board which is provided with a low-permittivity interlayer insulating film, and which can significantly improve the performance such as signal transmission characteristics of the multilayered circuit board such as a package and a printed board, because the surface in contact with the interlayer insulating film of the circuit board has no unevenness to eliminate the lowering of production yield and the deterioration of high-frequency signal transmission characteristics; and electronic equipment using the circuit board.
    Type: Grant
    Filed: August 18, 2006
    Date of Patent: July 10, 2012
    Assignee: Tohoku University
    Inventors: Tadahiro Ohmi, Akinobu Teramoto, Akihiro Morimoto
  • Publication number: 20120146102
    Abstract: An accumulation mode transistor has an impurity concentration of a semiconductor layer in a channel region at a value higher than 2×1017 cm?3 to achieve a large gate voltage swing.
    Type: Application
    Filed: February 13, 2012
    Publication date: June 14, 2012
    Inventors: Tadahiro Ohmi, Akinobu Teramoto, Rihito Kuroda
  • Patent number: 8198195
    Abstract: A plasma processing apparatus in which consumption of expensive krypton and xenon gases is suppressed as much as possible while reducing damage on a workpiece during plasma processing. In plasma processing of a substrate using a rare gas, two or more kinds of different rare gases are employed, and an inexpensive argon gas is used as one rare gas and any one or both of krypton and xenon gases having a larger collision cross-sectional area against electron than that of the argon gas is used as the other gas. Consequently, consumption of expensive krypton and xenon gases is suppressed as much as possible and damage on a workpiece is reduced during plasma processing.
    Type: Grant
    Filed: September 26, 2005
    Date of Patent: June 12, 2012
    Assignee: Tadahiro Ohmi
    Inventors: Tadahiro Ohmi, Akinobu Teramoto
  • Patent number: 8183670
    Abstract: In a semiconductor device formed on a silicon surface which has a substantial (110) crystal plane orientation, the silicon surface is flattened so that an arithmetical mean deviation of surface Ra is not greater than 0.15 nm, preferably, 0.09 nm, which enables to manufacture an n-MOS transistor of a high mobility. Such a flattened silicon surface is obtained by repeating a deposition process of a self-sacrifice oxide film in an oxygen radical atmosphere and a removing process of the self-sacrifice oxide film, by cleaning the silicon surface in deaerated H2O or a low OH density atmosphere, or by strongly terminating the silicon surface by hydrogen or heavy hydrogen. The deposition process of the self-sacrifice oxide film may be carried out by isotropic oxidation.
    Type: Grant
    Filed: January 9, 2007
    Date of Patent: May 22, 2012
    Assignee: Foundation for Advancement of International Science
    Inventors: Tadahiro Ohmi, Shigetoshi Sugawa, Akinobu Teramoto, Hiroshi Akahori, Keiichi Nii
  • Patent number: 8138527
    Abstract: An accumulation mode transistor has an impurity concentration of a semiconductor layer in a channel region at a value higher than 2×1017 cm?3 to achieve a large gate voltage swing.
    Type: Grant
    Filed: July 12, 2007
    Date of Patent: March 20, 2012
    Assignees: National University Corporation Tohoku University, Foundation For Advancement of International Science
    Inventors: Tadahiro Ohmi, Akinobu Teramoto, Rihito Kuroda
  • Patent number: 8134376
    Abstract: In a method for measuring an electronic device which is an object to be measured, a passive element is connected to the electronic device in parallel, and electric parameters of the electronic device are extracted by measuring an impedance of the entire circuit.
    Type: Grant
    Filed: January 17, 2006
    Date of Patent: March 13, 2012
    Assignee: Tohoku University
    Inventors: Tadahiro Ohmi, Akinobu Teramoto
  • Patent number: 8093918
    Abstract: An electronic device that includes an actual operation circuit that operates during an actual operation of the electronic device, a second test circuit and a third test circuit that operate during a test of the electronic device, and a power supply section. The power supply section, during the actual operation of the electronic device, does not apply a power supply voltage to the second test circuit and applies power supply voltages to the actual operation circuit and the third test circuit. The power supply section, to obtain identification of the electronic device, applies a power supply voltage to the second test circuit.
    Type: Grant
    Filed: August 18, 2010
    Date of Patent: January 10, 2012
    Assignees: National University Corporation Tohoku University, Advantest Corporation
    Inventors: Toshiyuki Okayasu, Shigetoshi Sugawa, Akinobu Teramoto
  • Patent number: 8067809
    Abstract: A semiconductor storage device with excellent electrical characteristics (write/erase characteristics) by favorable nitrogen concentration profile of a gate insulating film, and a method for manufacturing the semiconductor device. The semiconductor device fabricating method operates by transferring charges through a gate insulating film formed between a semiconductor substrate and a gate electrode, including introducing an oxynitriding species previously diluted by plasma excitation gas into a plasma processing apparatus, generating an oxynitriding species by a plasma, and forming an oxynitride film on the semiconductor substrate as the gate insulating film. The oxynitriding species contains NO gas at a ratio of 0.00001 to 0.01% to the total volume of gas introduced into the plasma processing apparatus.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: November 29, 2011
    Assignees: Tokyo Electron Limited, Tohoku University
    Inventors: Junichi Kitagawa, Shigenori Ozaki, Akinobu Teramoto, Tadahiro Ohmi
  • Patent number: 8030182
    Abstract: By hydrogen-terminating a semiconductor surface using a solution containing HF2? ions and an oxidant, the hydrogen termination can be quickly carried out. In this case, the semiconductor surface is silicon having a (111) surface, a (110) surface, or a (551) surface.
    Type: Grant
    Filed: September 20, 2005
    Date of Patent: October 4, 2011
    Assignee: Tadahiro OHMI
    Inventors: Tadahiro Ohmi, Akinobu Teramoto, Hiroshi Akahori