Patents by Inventor Akio Nishida
Akio Nishida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6532159Abstract: A switching power supply unit comprises: a transformer, a main switching element, a rectifying smoothing circuit, a mode switching circuit and a delay circuit. The transformer has a primary winding, a secondary winding and a bias winding. The main switching element is connected to the primary winding and receives an output of the bias winding as a positive feedback so as to form a ringing choke converter operating in self-excitation oscillation. The rectifying smoothing circuit is connected to the bias winding. The mode switching circuit is turned on and off depending on whether or not the rectifying smoothing voltage of the rectifying smoothing circuit is a threshold voltage or higher. The delay circuit is coupled to the mode switching circuit and is connected between the main switching element and the bias winding and delays the output of the bias winding and applies the delayed output to the main switching element.Type: GrantFiled: April 17, 2001Date of Patent: March 11, 2003Assignee: Murata Manufacturing Co., Ltd.Inventors: Akio Nishida, Hiroshi Takemura
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Patent number: 6529392Abstract: An RCC type switching power supply unit with a transformer having a primary winding, a secondary winding, and a feedback winding, a main switching element receiving a feedback signal from the feedback winding and for turning on and off the current of the primary winding, a rectifying and smoothing circuit having a rectifying element and a smoothing element connected to the secondary winding, and a control circuit connected between the feedback winding and the control terminal of the main switching element. A delay circuit by which the turning on of the main switching element is prohibited for a certain period of time after the current of the rectifying element has become zero and a switching circuit by which the delay time of the delay circuit is changed by two or more stages are provided.Type: GrantFiled: September 6, 2001Date of Patent: March 4, 2003Assignee: Murata Manufacturing Co., Ltd.Inventors: Akio Nishida, Ryota Tani, Koji Nakahira
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Publication number: 20030006433Abstract: A semiconductor integrated circuit device, e.g., a memory cell of SRAM, is formed of a pair of inverters having their input and output points connected crisscross and formed of drive n-channel MISFETs and load p-channel MISFETs. The n-channel MISFETs and p-channel MISFETs have their back gates supplied with the power voltage and ground voltage, respectively. The MISFETs are formed with the formation of a metal silicide layer on the gate electrodes G and source regions (hatched areas) and without the formation of a metal silicide layer on the drain regions, respectively, whereby the leak current of the MISFETs having a voltage difference between the drain regions and wells can be reduced and thus the power consumption can be reduced.Type: ApplicationFiled: June 14, 2002Publication date: January 9, 2003Inventors: Kota Funayama, Yasuko Yoshida, Masaru Nakamichi, Akio Nishida
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Patent number: 6498100Abstract: In a method of manufacturing a semiconductor device having a memory mat portion in which an active region and a field region are formed densely, after a polishing stopper film is deposited on a semiconductor substrate, there are formed grooves by etching a polishing stopper film of a field region and the semiconductor substrate. Then, after an insulating film is deposited so as to fill the grooves, then insulating film is partly removed from the memory mat portion by etching. Under this state, the insulating film is chemically mechanically polished until the polishing stopper film is exposed. The film thickness of the polishing stopper film on the active region can be reduced, and an electrical element isolation characteristic of the field region can be improved.Type: GrantFiled: November 30, 2001Date of Patent: December 24, 2002Assignee: Hitachi, Ltd.Inventors: Akio Nishida, Kikuo Kusukawa, Toshiaki Yamanaka, Natsuki Yokoyama, Shinichiro Kimura, Norio Suzuki, Osamu Tsuchiya, Atsushi Ogishima
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Publication number: 20020186572Abstract: A switching power supply includes a control circuit disposed between a feedback winding and a switching device. The control circuit includes an on-period control circuit that, in an operation under a non-low load condition, controls an on-period of the switching device such that the on-period decreases with decreasing load, a minimum on-period setting circuit that disables the on-period control circuit in an operation under a low load condition so that the on-period of the switching device does not become shorter than a predetermined minimum on-period, and an off-period control circuit that controls an off-period of the switching device in the operation under the low load condition such that the off-period increases with decreasing load. As a result, the output voltage is maintained at a constant value in accordance with a feedback signal.Type: ApplicationFiled: May 22, 2002Publication date: December 12, 2002Applicant: Murata Manufacturing Co., Ltd.Inventors: Akio Nishida, Hiroshi Takemura
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Publication number: 20020187596Abstract: A low threshold voltage NMIS area and a high threshold voltage PMIS area are set by a photoresist mask also used for well formation. Using a photoresist mask with openings for the NMIS and PMIS, the NMIS and PMIS areas are set by one ion implantation step. After gate oxidation, ion implantation is conducted through an amorphous silicon film onto wells, channels, and gate electrodes. A plurality of CMIS threshold voltages can be set and the gate electrodes of both polarities can be formed in a reduced number of steps using photoresist. This solves the problem in which photomasks are required as many as there are ion implantation types for wells, channel stoppers, gate electrodes, and threshold voltage control and hence the number of manufacturing steps and the production cost are increased.Type: ApplicationFiled: June 6, 2002Publication date: December 12, 2002Applicant: Hitachi, Ltd.Inventors: Toshiaki Yamanaka, Akio Nishida, Yasuko Yoshida, Shuji Ikeda, Kenichi Kuroda, Shiro Kamohara, Shinichiro Kimura, Eiichi Murakami, Hideyuki Matsuoka, Masataka Minami
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Publication number: 20020179940Abstract: The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.Type: ApplicationFiled: June 3, 2002Publication date: December 5, 2002Inventors: Kenichi Osada, Koichiro Ishibashi, Yoshikazu Saitoh, Akio Nishida, Masaru Nakamichi, Naoki Kitai
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Publication number: 20020136031Abstract: A switching power supply unit includes a control circuit including a turn-off circuit for turning of a first switch element Q1, which has been in an ON state, and an off-period control circuit for, based on a feedback signal from an output-voltage detecting circuit, controlling the turning-on of the first switch element to be further delayed as a load is lighter. The off-period control circuit includes a transistor as a second switch element which is provided in series between a feedback winding and the control terminal of the first switch element and which is controlled to be turned on and off based on the feedback signal from the output-voltage detecting circuit. A switching frequency is set to be lower as the load is lighter, such that power consumption at the light load is reduced.Type: ApplicationFiled: March 5, 2002Publication date: September 26, 2002Applicant: Murata Manufacturing Co., Ltd.Inventors: Satoshi Yamaguchi, Akio Nishida, Hiroshi Takemura
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Patent number: 6433443Abstract: A switching power supply having two or more DC outputs includes a DC power supply, a transformer having a primary winding, at least two secondary windings, and a feedback winding, a main switching element having an off-state period and an on-state period, connected in series to the primary winding and to be turned on by a voltage generated in the feedback winding, the main switching element having a control terminal and a threshold voltage to turn the main switching element on; and a rectifying circuit connected to each secondary winding, a starting circuit which initially turns on the main switching element at startup of the power supply and a switching circuit provided between the two DC outputs, and wherein, when the switching circuit is turned on, a voltage generated in the feedback winding is lowered during the off-state period of the main switching element and a voltage to be applied to the control terminal of the main switching element is controlled so as to be less than the threshold voltage, and theType: GrantFiled: January 9, 2001Date of Patent: August 13, 2002Assignee: Murata Manufacturing Co., Ltd.Inventors: Akio Nishida, Ryota Tani, Koji Nakahira, Tomohiro Yamada
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Publication number: 20020075085Abstract: A switching transistor is connected to a primary winding of a transformer, an oscillation frequency control circuit is connected to a feedback winding, the oscillation frequency control circuit controls a first controlling transistor, and the first controlling transistor controls the delay time when the switching transistor is turned on. The oscillation frequency control circuit is set in a first operation mode in which the above delay does not take place at the rated load, in a second operation mode in which the oscillation frequency is controlled such that the oscillation frequency becomes constant or slowly decreases at light loading and in a third operation mode in which the oscillation frequency is further decreased while a switch is switched on.Type: ApplicationFiled: October 22, 2001Publication date: June 20, 2002Applicant: Murata Manufacturing Co., Ltd.Inventors: Akio Nishida, Ryota Tani, Koji Nakahira
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Publication number: 20020057583Abstract: A switching power supply unit includes a control output circuit, a non-control output circuit, and a regulator circuit. With this switching power supply unit, it is no longer necessary to set the voltage of the non-control output to be greater than a required value when the control output circuit is unloaded or lightly loaded. The regulator circuit is connected to the non-control output circuit and includes a first transistor defining a first impedance element connected in series to the non-control output circuit, a second transistor defining a second impedance element connected between the control output circuit and the base of the first transistor, and a voltage control circuit controlling the impedance of the second transistor such that the output voltage of the regulator circuit is maintained constant.Type: ApplicationFiled: October 31, 2001Publication date: May 16, 2002Applicant: Murata Manufacturing Co., Ltd.Inventors: Akio Nishida, Hiroshi Takemura
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Publication number: 20020055261Abstract: In a method of manufacturing a semiconductor device having a memory mat portion in which an active region and a field region are formed densely, after a polishing stopper film is deposited on a semiconductor substrate, there are formed grooves by etching a polishing stopper film of a field region and the semiconductor substrate. Then, after an insulating film is deposited so as to fill the grooves, then insulating film is partly removed from the memory mat portion by etching. Under this state, the insulating film is chemically mechanically polished until the polishing stopper film is exposed. The film thickness of the polishing stopper film on the active region can be reduced, and an electrical element isolation characteristic of the field region can be improved.Type: ApplicationFiled: November 30, 2001Publication date: May 9, 2002Applicant: Hitachi, Ltd.Inventors: Akio Nishida, Kikuo Kusukawa, Toshiaki Yamanaka, Natsuki Yokoyama, Shinichiro Kimura, Norio Suzuki, Osamu Tsuchiya, Atsushi Ogishima
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Patent number: 6380085Abstract: In a method of manufacturing a semiconductor device having a memory mat portion in which an active region and a field region are formed densely, after a polishing stopper film is deposited on a semiconductor substrate, there are formed grooves by etching a polishing stopper film of a field region and the semiconductor substrate. Then, after an insulating film is deposited so as to fill the grooves, then insulating film is partly removed from the memory mat portion by etching. Under this state, the insulating film is chemically mechanically polished until the polishing stopper film is exposed. The film thickness of the polishing stopper film on the active region can be reduced, and an electrical element isolation characteristic of the field region can be improved.Type: GrantFiled: December 29, 2000Date of Patent: April 30, 2002Assignee: Hitachi, Ltd.Inventors: Akio Nishida, Kikuo Kusukawa, Toshiaki Yamanaka, Natsuki Yokoyama, Shinichiro Kimura, Norio Suzuki, Osamu Tsuchiya, Atsushi Ogishima
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Publication number: 20020045360Abstract: This semiconductor device manufacturing method comprises the steps of: forming a thick gate oxide film (thick oxide film) in a first region of a substrate, forming a thin gate oxide film (thin oxide layer) in a second region, and then, applying oxynitridation to these gate oxide films; forming gate electrodes to 1d on these gate oxide films; and implanting an ion that contains nitrogen or nitrogen atoms into at least one part of an interface between the hick gate oxide film (thick oxide film) and the substrate before or after the step of forming the gate electrodes, thereby forming a highly oxy-nitrided region. In this manner, in a semiconductor device in which there coexist a MISFET having a thin gate insulation film and a MISFET having a thick gate insulation film, hot carrier reliability of the MISFET having the thick gate insulation film is improved.Type: ApplicationFiled: August 31, 2001Publication date: April 18, 2002Inventors: Eiichi Murakami, Akio Nishida, Kazunori Umeda, Kousuke Okuyama, Toshiaki Yamanaka, Jiro Yugami, Shinichiro Kimura
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Publication number: 20020027787Abstract: An RCC type switching power supply unit with a transformer having a primary winding, a secondary winding, and a feedback winding, a main switching element receiving a feedback signal from the feedback winding and for turning on and off the current of the primary winding, a rectifying and smoothing circuit having a rectifying element and a smoothing element connected to the secondary winding, and a control circuit connected between the feedback winding and the control terminal of the main switching element. A delay circuit by which the turning on of the main switching element is prohibited for a certain period of time after the current of the rectifying element has become zero and a switching circuit by which the delay time of the delay circuit is changed by two or more stages are provided.Type: ApplicationFiled: September 6, 2001Publication date: March 7, 2002Applicant: Murata Manufacturing Co., Ltd.Inventors: Akio Nishida, Ryota Tani, Koji Nakahira
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Publication number: 20020011602Abstract: A switching power supply unit comprises: a transformer, a main switching element, a rectifying smoothing circuit, a mode switching circuit and a delay circuit. The transformer has a primary winding, a secondary winding and a bias winding. The main switching element is connected to the primary winding and receives an output of the bias winding as a positive feedback so as to form a ringing choke converter operating in self-excitation oscillation. The rectifying smoothing circuit is connected to the bias winding. The mode switching circuit is turned on and off depending on whether or not the rectifying smoothing voltage of the rectifying smoothing circuit is a threshold voltage or higher. The delay circuit is coupled to the mode switching circuit and is connected between the main switching element and the bias winding and delays the output of the bias winding and applies the delayed output to the main switching element.Type: ApplicationFiled: April 17, 2001Publication date: January 31, 2002Applicant: Murata Manufacturing Co., Ltd.Inventors: Akio Nishida, Hiroshi Takemura
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Publication number: 20010053597Abstract: In a method of manufacturing a semiconductor device having a memory mat portion in which an active region and a field region are formed densely, after a polishing stopper film is deposited on a semiconductor substrate, there are formed grooves by etching a polishing stopper film of a field region and the semiconductor substrate. Then, after an insulating film is deposited so as to fill the grooves, then insulating film is partly removed from the memory mat portion by etching. Under this state, the insulating film is chemically mechanically polished until the polishing stopper film is exposed. The film thickness of the polishing stopper film on the active region can be reduced, and an electrical element isolation characteristic of the field region can be improved.Type: ApplicationFiled: December 29, 2000Publication date: December 20, 2001Applicant: Hitachi, Ltd.Inventors: Akio Nishida, Kikuo Kusukawa, Toshiaki Yamanaka, Natsuki Yokoyama, Shinichiro Kimura, Norio Suzuki, Osamu Tsuchiya, Atsushi Ogishima
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Patent number: 6295211Abstract: A switching power supply unit includes a DC power supply, a transformer having a primary winding, a secondary winding and a feedback winding, a main switching element connected in series to the primary winding, and a control circuit connected between the feedback winding and the control terminal of the main switching element, so that a DC output can be obtained. In this switching power supply unit, there are provided a voltage generating unit disposed on the primary side of the transformer to output a voltage according to a load power, and a delay circuit for reducing the switching frequency by delaying the turn-on of the main switching element according to a voltage output from the voltage generating unit thereby to prolong the OFF time of the main switching element.Type: GrantFiled: January 11, 2000Date of Patent: September 25, 2001Assignee: Murata Manufacturing Co., Ltd.Inventors: Akio Nishida, Ryota Tani, Koji Nakahira
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Patent number: 6285566Abstract: A self-oscillation switching power supply apparatus of the ringing choke converter type comprises a transformer T including a primary winding N1, a secondary winding N2, and a feedback winding NB; a switching transistor Q1 which oscillates in a self-oscillating fashion in response to a feedback signal from the feedback winding NB thereby turning on and off the current flowing through the primary winding; a rectifying and smoothing circuit connected to the secondary winding; an oscillation frequency control circuit including a control transistor Q3 for controlling a control signal input to the switching transistor Q1 thereby controlling the control transistor Q3 so as to extend the off-time in the self-oscillation period of the switching transistor Q1; and an oscillation frequency control disabling circuit for disabling the control of the control transistor Q3 in accordance with a remote signal.Type: GrantFiled: January 21, 1999Date of Patent: September 4, 2001Assignee: Murata Manufacturing Co., Ltd.Inventors: Koji Nakahira, Ryuji Okamura, Ryota Tani, Akio Nishida
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Publication number: 20010011753Abstract: A gate electrode of each MISFET is formed on a substrate in an active region whose periphery is defined by an element isolation trench, and crosses the active region so as to extend from one end thereof to the other end thereof. The gate electrode has a gate length in a boundary region defined between the active region and the element isolation trench, which gate length is greater than a gate length in a central portion of the active region. The gate electrode is configured in an H-type flat pattern as a whole. Further, the gate electrode covers the whole of one side extending along a gate-length direction, of the boundary region defined between the active region L and the element isolation trench, and parts of two sides thereof extending along a gate-width direction. The MISFETs are respectively formed in electrically separated wells and are connected in series so as to constitute part of a reference voltage generating circuit.Type: ApplicationFiled: February 1, 2001Publication date: August 9, 2001Inventors: Akio Nishida, Noriyuki Yabuoshi, Yasuko Yoshida, Kazuhiro Komori, Sousuke Tsuji, Hideo Miwa, Mitsuhiro Higuchi, Koichi Imato