Patents by Inventor Akio Nishida

Akio Nishida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor memory device and a method of manufacturing the same, a method of manufacturing a vertical MISFET and a vertical MISFET, and a method of manufacturing a semiconductor device and a semiconductor device
    Patent number: 7972920
    Abstract: Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are each comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film.
    Type: Grant
    Filed: February 4, 2010
    Date of Patent: July 5, 2011
    Assignees: Hitachi ULSI Systems Co., Ltd., Renesas Electronics Corp.
    Inventors: Hiraku Chakihara, Kousuke Okuyama, Masahiro Moniwa, Makoto Mizuno, Keiji Okamoto, Mitsuhiro Noguchi, Tadanori Yoshida, Yasuhiko Takahshi, Akio Nishida
  • Semiconductor integrated circuit device with reduced leakage current
    Patent number: 7964484
    Abstract: The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.
    Type: Grant
    Filed: June 25, 2009
    Date of Patent: June 21, 2011
    Assignees: Renesas Electronics Corporation, Hitachi ULSI Systems Co., Ltd.
    Inventors: Kenichi Osada, Koichiro Ishibashi, Yoshikazu Saitoh, Akio Nishida, Masaru Nakamichi, Naoki Kitai
  • Semiconductor integrated circuit device
    Patent number: 7893505
    Abstract: In order to provide a semiconductor integrated circuit device such as a high-performance semiconductor integrated circuit device capable of reducing a soft error developed in each memory cell of a SRAM, the surface of a wiring of a cross-connecting portion, of a SRAM memory cell having a pair of n-channel type MISFETs whose gate electrodes and drains are respectively cross-connected, is formed in a shape that protrudes from the surface of a silicon oxide film. A silicon nitride film used as a capacitive insulating film, and an upper electrode are formed on the wiring. A capacitance can be formed of the wiring, the silicon nitride film and the upper electrode.
    Type: Grant
    Filed: January 30, 2009
    Date of Patent: February 22, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Akio Nishida, Yasuko Yoshida, Shuji Ikeda
  • METHOD OF MANUFACTURING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    Publication number: 20110021022
    Abstract: In forming five trenches buried with an intermediate conductive layer for connecting transfer MISFETs and driving MISFETs with vertical MISFETs formed thereover, in which the second and third trenches, and the first, fourth, and fifth trenches are formed separately by twice etching using first and second photoresist films as a mask. Since all the trenches can be formed at a good accuracy even in a case where the shortest distance between the first trench and the second or third trench, and the shortest distance between the second or third trench and the fourth trench is smaller than the resolution limit for the exposure light, the distance between each of the five trenches arranged in one identical memory cell can be reduced to be smaller than resolution limit for the exposure light.
    Type: Application
    Filed: October 4, 2010
    Publication date: January 27, 2011
    Inventors: Hiraku Chakihara, Mitsuhiro Noguchi, Masahiro Tadokoro, Naonori Wada, Akio Nishida
  • Method of manufacturing a semiconductor integrated circuit device
    Patent number: 7833905
    Abstract: In forming five trenches buried with an intermediate conductive layer for connecting transfer MISFETs and driving MISFETs with vertical MISFETs formed thereover, in which the second and third trenches, and the first, fourth, and fifth trenches are formed separately by twice etching using first and second photoresist films as a mask. Since all the trenches can be formed at a good accuracy even in a case where the shortest distance between the first trench and the second or third trench, and the shortest distance between the second or third trench and the fourth trench is smaller than the resolution limit for the exposure light, the distance between each of the five trenches arranged in one identical memory cell can be reduced to be smaller than resolution limit for the exposure light.
    Type: Grant
    Filed: May 5, 2009
    Date of Patent: November 16, 2010
    Assignee: Renesas Electronics Corp.
    Inventors: Hiraku Chakihara, Mitsuhiro Noguchi, Masahiro Tadokoro, Naonori Wada, Akio Nishida
  • NONVOLATILE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING NONVOLATILE SEMICONDUCTOR DEVICE
    Publication number: 20100190330
    Abstract: A semiconductor substrate having a main surface, first and second floating gates formed spaced apart from each other on the main surface of the semiconductor substrate, first and second control gates respectively located on the first and second floating gates, a first insulation film formed on the first control gate, a second insulation film formed on the second control gate to contact the first insulation film, and a gap portion formed at least between the first floating gate and the second floating gate by achieving contact between the first insulation film and the second insulation film are included. With this, a function of a nonvolatile semiconductor device can be ensured and a variation in a threshold voltage of a floating gate can be suppressed.
    Type: Application
    Filed: March 19, 2010
    Publication date: July 29, 2010
    Applicant: Renesas Technology Corp.
    Inventors: Yasuaki YONEMOCHI, Hisakazu Otoi, Akio Nishida, Shigeru Shiratake
  • Semiconductor Memory Device and a Method of Manufacturing the Same, A Method of Manufacturing a Vertical MISFET and a Vertical MISFET, and a Method of Manufacturing a Semiconductor Device and a Semiconductor Device
    Publication number: 20100136778
    Abstract: Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are each comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film.
    Type: Application
    Filed: February 4, 2010
    Publication date: June 3, 2010
    Inventors: Hiraku Chakihara, Kousuke Okuyama, Masahiro Moniwa, Makoto Mizuno, Keiji Okamoto, Mitsuhiro Noguchi, Tadanori Yoshida, Yasuhiko Takahshi, Akio Nishida
  • Power supply unit
    Patent number: 7719139
    Abstract: A power supply unit includes a main power-supply circuit and a secondary power-supply circuit which are connected to an alternating current power supply AC. The main power-supply circuit includes a full-wave rectifier and an input current control circuit corresponding to a harmonic current suppression circuit. The input current control circuit includes a resistor as circuit current detection element and a control circuit for controlling a switch element by detecting a current flowing in the resistor. A connection is provided such that a current flowing in a diode as a second rectifying circuit of the secondary power-supply circuit may return to the alternating current power supply through the resistor.
    Type: Grant
    Filed: February 17, 2005
    Date of Patent: May 18, 2010
    Assignee: Murata Macufacturing Co., Ltd.
    Inventors: Yoshiyuki Uno, Akio Nishida, Hiroshi Takemura
  • Nonvolatile semiconductor device and method of manufacturing nonvolatile semiconductor device
    Patent number: 7705392
    Abstract: A semiconductor substrate having a main surface, first and second floating gates formed spaced apart from each other on the main surface of the semiconductor substrate, first and second control gates respectively located on the first and second floating gates, a first insulation film formed on the first control gate, a second insulation film formed on the second control gate to contact the first insulation film, and a gap portion formed at least between the first floating gate and the second floating gate by achieving contact between the first insulation film and the second insulation film are included. With this, a function of a nonvolatile semiconductor device can be ensured and a variation in a threshold voltage of a floating gate can be suppressed.
    Type: Grant
    Filed: April 13, 2006
    Date of Patent: April 27, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Yasuaki Yonemochi, Hisakazu Otoi, Akio Nishida, Shigeru Shiratake
  • Semiconductor memory device and a method of manufacturing the same, a method of manufacturing a vertical MISFET and a vertical MISFET, and a method of manufacturing a semiconductor device and a semiconductor device
    Patent number: 7701020
    Abstract: Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are each comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film.
    Type: Grant
    Filed: February 2, 2009
    Date of Patent: April 20, 2010
    Assignees: Renesas Technology Corp., Hitachi Ulsi Systems Co., Ltd.
    Inventors: Hiraku Chakihara, Kousuke Okuyama, Masahiro Moniwa, Makoto Mizuno, Keiji Okamoto, Mitsuhiro Noguchi, Tadanori Yoshida, Yasuhiko Takahshi, Akio Nishida
  • NONVOLATILE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING NONVOLATILE SEMICONDUCTOR DEVICE
    Publication number: 20100044772
    Abstract: A semiconductor substrate having a main surface, first and second floating gates formed spaced apart from each other on the main surface of the semiconductor substrate, first and second control gates respectively located on the first and second floating gates, a first insulation film formed on the first control gate, a second insulation film formed on the second control gate to contact the first insulation film, and a gap portion formed at least between the first floating gate and the second floating gate by achieving contact between the first insulation film and the second insulation film are included. With this, a function of a nonvolatile semiconductor device can be ensured and a variation in a threshold voltage of a floating gate can be suppressed.
    Type: Application
    Filed: November 5, 2009
    Publication date: February 25, 2010
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Yasuaki YONEMOCHI, Hisakazu OTOI, Akio NISHIDA, Shigeru SHIRATAKE
  • SEMICONDUCTOR CHIP HAVING GETTERING LAYER, AND METHOD FOR MANUFACTURING THE SAME
    Publication number: 20090286354
    Abstract: In a semiconductor chip A wherein an element layer 2 having transistors and the like is formed on the front face, and the back face is joined to an underlying member, such as a package substrate, the thickness T is made 100 ?m or less, and thereafter, a gettering layer 3 is formed on the back face of the semiconductor chip A. The gettering layer 3 is formed, for example, by polishing the back face of said semiconductor chip A using a polishing machine. Thereby, the yield of devices can be improved in the step for assembling the package.
    Type: Application
    Filed: July 24, 2009
    Publication date: November 19, 2009
    Applicant: Renesas Technology Corp.
    Inventors: KAZUHITO MATSUKAWA, Tsuyoshi Koga, Akio Nishida, Yoshiko Higashide, Jun Shibata, Hiroshi Tobimatsu
  • METHOD OF MANUFACTURING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    Publication number: 20090275193
    Abstract: In forming five trenches buried with an intermediate conductive layer for connecting transfer MISFETs and driving MISFETs with vertical MISFETs formed thereover, in which the second and third trenches, and the first, fourth, and fifth trenches are formed separately by twice etching using first and second photoresist films as a mask. Since all the trenches can be formed at a good accuracy even in a case where the shortest distance between the first trench and the second or third trench, and the shortest distance between the second or third trench and the fourth trench is smaller than the resolution limit for the exposure light, the distance between each of the five trenches arranged in one identical memory cell can be reduced to be smaller than resolution limit for the exposure light.
    Type: Application
    Filed: May 5, 2009
    Publication date: November 5, 2009
    Inventors: Hiraku Chakihara, Mitsuhiro Noguchi, Masahiro Tadokoro, Naonori Wada, Akio Nishida
  • Semiconductor integrated circuit device with reduced leakage current
    Publication number: 20090269899
    Abstract: The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.
    Type: Application
    Filed: June 25, 2009
    Publication date: October 29, 2009
    Inventors: Kenichi OSADA, Koichiro ISHIBASHI, Yoshikazu SAITOH, Akio NISHIDA, Masaru NAKAMICHI, Naoki KITAI
  • Method of manufacturing a semiconductor integrated circuit device
    Patent number: 7595266
    Abstract: In forming five trenches buried with an intermediate conductive layer for connecting transfer MISFETs and driving MISFETs with vertical MISFETs formed thereover, in which the second and third trenches, and the first, fourth, and fifth trenches are formed separately by twice etching using first and second photoresist films as a mask. Since all the trenches can be formed at a good accuracy even in a case where the shortest distance between the first trench and the second or third trench, and the shortest distance between the second or third trench and the fourth trench is smaller than the resolution limit for the exposure light, the distance between each of the five trenches arranged in one identical memory cell can be reduced to be smaller than resolution limit for the exposure light.
    Type: Grant
    Filed: June 26, 2008
    Date of Patent: September 29, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Hiraku Chakihara, Mitsuhiro Noguchi, Masahiro Tadokoro, Naonori Wada, Akio Nishida
  • SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20090218608
    Abstract: In order to provide a semiconductor integrated circuit device such as a high-performance semiconductor integrated circuit device capable of reducing a soft error developed in each memory cell of a SRAM, the surface of a wiring of a cross-connecting portion, of a SRAM memory cell having a pair of n-channel type MISFETs whose gate electrodes and drains are respectively cross-connected, is formed in a shape that protrudes from the surface of a silicon oxide film. A silicon nitride film used as a capacitive insulating film, and an upper electrode are formed on the wiring. A capacitance can be formed of the wiring, the silicon nitride film and the upper electrode.
    Type: Application
    Filed: January 30, 2009
    Publication date: September 3, 2009
    Inventors: Akio NISHIDA, Yasuko Yoshida, Shuji Ikeda
  • Semiconductor chip having gettering layer, and method for manufacturing the same
    Patent number: 7582950
    Abstract: In a semiconductor chip A wherein an element layer 2 having transistors and the like is formed on the front face, and the back face is joined to an underlying member, such as a package substrate, the thickness T is made 100 ?m or less, and thereafter, a gettering layer 3 is formed on the back face of the semiconductor chip A. The gettering layer 3 is formed, for example, by polishing the back face of said semiconductor chip A using a polishing machine. Thereby, the yield of devices can be improved in the step for assembling the package.
    Type: Grant
    Filed: July 27, 2005
    Date of Patent: September 1, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Kazuhito Matsukawa, Tsuyoshi Koga, Akio Nishida, Yoshiko Higashide, Jun Shibata, Hiroshi Tobimatsu
  • POWER SUPPLY UNIT
    Publication number: 20090200870
    Abstract: A power supply unit includes a main power-supply circuit and a secondary power-supply circuit which are connected to an alternating current power supply AC. The main power-supply circuit includes a full-wave rectifier and an input current control circuit corresponding to a harmonic current suppression circuit. The input current control circuit includes a resistor as circuit current detection element and a control circuit for controlling a switch element by detecting a current flowing in the resistor. A connection is provided such that a current flowing in a diode as a second rectifying circuit of the secondary power-supply circuit may return to the alternating current power supply through the resistor.
    Type: Application
    Filed: February 17, 2005
    Publication date: August 13, 2009
    Inventors: Yoshiyuki Uno, Akio Nishida, Hiroshi Takemura
  • Semiconductor integrated circuit device with reduced leakage current
    Patent number: 7569881
    Abstract: The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.
    Type: Grant
    Filed: April 9, 2008
    Date of Patent: August 4, 2009
    Assignees: Renesas Technology Corporation, Hitachi ULSI Systems Co., Ltd.
    Inventors: Kenichi Osada, Koichiro Ishibashi, Yoshikazu Saitoh, Akio Nishida, Masaru Nakamichi, Naoki Kitai
  • DISCHARGE TUBE LIGHTING APPARATUS
    Publication number: 20090160352
    Abstract: A discharge tube lighting apparatus includes a converter that converts a voltage received from an alternating-current or direct-current power supply into a predetermined direct-current voltage and an inverter that converts an output voltage of the converter into an alternating-current voltage having a predetermined frequency. The inverter performs burst control based on an externally input dimming signal. The converter operates regardless of the active or inactive period of the burst control of the inverter and performs negative feedback control in response to a detection signal of a tube current in the active period of the inverter.
    Type: Application
    Filed: March 13, 2009
    Publication date: June 25, 2009
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Akio NISHIDA, Shigeru ARAI