Abstract: The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.

Abstract: A manufacturing process for a semiconductor integrated circuit device which prevents occurrence of reaction between metal wiring and a boron-doped silicon plug over it in heat treatment for a MOS transistor to be formed over them and reduces the possibility of rise in contact resistance. Metal boride is formed on an exposed metal surface in the bottom of an opening made in an interlayer insulating film over the metal wiring. In order to facilitate formation of such metal boride, metal oxide remaining on the metal surface is removed with an aqueous ammonia solution. The meal surface is irradiated with high energy ultraviolet light in order to remove organic matter remaining in the opening and facilitate removal of the metal oxide with the aqueous ammonia solution.

Abstract: In a semiconductor device, the ohmic contact at the junction between the metal interconnection and the semiconductor layer is lowered by depositing a first conductor layer comprised of, for example, tungsten nitride and a second conductor layer comprised of, for example, tungsten silicide successively from the lower layer so as to cover the upper surface of intermediate conductive layers comprised of a metal, for example, tungsten as a main interconnection material, subsequently introducing an impurity, for example, boron (b) to the second conductor layer, then patterning the first and the second conductor layers thereby forming a conductor layer, and then forming a lower semiconductor layer comprised of, for example, polycrystal silicon for forming a semiconductor region for source and drain of load MISFET of SRAM so as to be in contact with the conductor layer.

Abstract: In forming five trenches buried with an intermediate conductive layer for connecting transfer MISFETs and driving MISFETs with vertical MISFETs formed thereover, the second and third trenches, and the first, fourth, and fifth trenches are formed separately by twice etching using first and second photoresist films as a mask. Since all the trenches can be formed at a good accuracy even in a case where the shortest distance between the first trench and the second or third trench, and the shortest distance between the second or third trench and the fourth trench is smaller than the resolution limit for the exposure light, the distance between each of the five trenches arranged in one identical memory cell can be reduced to be smaller than the resolution limit for the exposure light.

Abstract: This semiconductor device manufacturing method comprises the steps of: forming a thick gate oxide film (thick oxide film) in a first region of a substrate, forming a thin gate oxide film (thin oxide layer) in a second region, and then, applying oxynitridation to these gate oxide films; forming gate electrodes to 1d on these gate oxide films; and implanting an ion that contains nitrogen or nitrogen atoms into at least one part of an interface between the hick gate oxide film (thick oxide film) and the substrate before or after the step of forming the gate electrodes, thereby forming a highly oxy-nitrided region. In this manner, in a semiconductor device in which there coexist a MISFET having a thin gate insulation film and a MISFET having a thick gate insulation film, hot carrier reliability of the MISFET having the thick gate insulation film is improved.

Abstract: An object is to improve soft error resistance of the memory cell of an SRAM without increasing its chip size. In deep through-holes formed by perforating a silicon oxide film, a silicon nitride film and a silicon oxide film, a capacitor element having a TiN film as a lower electrode, a silicon nitride film as an insulator and a TiN film as an upper electrode. This capacitor element is connected between a storage node and a supply voltage line, between a storage node and a reference voltage line, or between storage nodes of the memory cell of the SRAM.

Abstract: The invention provides a semiconductor memory device comprising a plurality of word lines, a plurality of bit lines, and a plurality of static memory cells each having a first, second, third, fourth, fifth, and sixth transistors. While each of channels of the first, second, third, and fourth transistors are formed vertical against a substrate of the semiconductor memory device. Each of semiconductor regions forming a source or a drain of the fifth and sixth transistors forms a PN junction against the substrate. According to another aspect of the invention, the SRAM device of the invention has a plurality of SRAM cells, at least one of which is a vertical SRAM cell comprising at least four vertical transistors onto a substrate, and each vertical transistor includes a source, a drain, and a channel therebetween aligning in one aligning line which penetrates into the substrate surface at an angle greater than zero degree.

Abstract: This semiconductor device manufacturing method comprises the steps of: forming a thick gate oxide film (thick oxide film) in a first region of a substrate, forming a thin gate oxide film (thin oxide layer) in a second region, and then, applying oxynitridation to these gate oxide films; forming gate electrodes to 1d on these gate oxide films; and implanting an ion that contains nitrogen or nitrogen atoms into at least one part of an interface between the hick gate oxide film (thick oxide film) and the substrate before or after the step of forming the gate electrodes, thereby forming a highly oxy-nitrided region. In this manner, in a semiconductor device in which there coexist a MISFET having a thin gate insulation film and a MISFET having a thick gate insulation film, hot carrier reliability of the MISFET having the thick gate insulation film is improved.

Abstract: Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs respectively comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on their corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source, respectively. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are respectively comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film.

Abstract: A switching power supply unit includes a transformer including a primary winding, a secondary winding, and a feedback winding; an input power supply and a first switching element that are connected in series with the primary winding; a control circuit provided between one end of the feedback winding and a control terminal of the first switching element; a rectification circuit connected to the secondary winding; and an output voltage detection circuit for detecting output voltage output from the rectification circuit and for sending a feedback signal to the control circuit. The control circuit includes an on-period control circuit for stabilizing the output voltage by turning off the first switching element in an on-state in accordance with the feedback signal. The control circuit also includes an off-period control circuit for stabilizing the output voltage by delaying turning on of the first switching element in accordance with the feedback signal.

Abstract: In order to provide a semiconductor integrated circuit device such as a high-performance semiconductor integrated circuit device capable of reducing a soft error developed in each memory cell of a SRAM, the surface of a wiring of a cross-connecting portion, of a SRAM memory cell having a pair of n-channel type MISFETs whose gate electrodes and drains are respectively cross-connected, is formed in a shape that protrudes from the surface of a silicon oxide film. A silicon nitride film used as a capacitive insulating film, and an upper electrode are formed on the wiring. A capacitance can be formed of the wiring, the silicon nitride film and the upper electrode, and a soft error produced due to an &agr; ray can be reduced. Since a capacitance can be formed even at each sidewall of the wiring, an increase in capacity can be achieved.

Abstract: A low threshold voltage NMIS area and a high threshold voltage PMIS area are set by a photoresist mask also used for well formation. Using a photoresist mask with openings for the NMIS and PMIS, the NMIS and PMIS areas are set by one ion implantation step. After gate oxidation, ion implantation is conducted through an amorphous silicon film onto wells, channels, and gate electrodes. A plurality of CMIS threshold voltages can be set and the gate electrodes of both polarities can be formed in a reduced number of steps using photoresist. This solves the problem in which photomasks are required as many as there are ion implantation types for wells, channel stoppers, gate electrodes, and threshold voltage control and hence the number of manufacturing steps and the production cost are increased.

Abstract: The invention provides a semiconductor memory device comprising a plurality of word lines, a plurality of bit lines, and a plurality of static memory cells each having a first, second, third, fourth, fifth, and sixth transistors. While each of channels of the first, second, third, and fourth transistors are formed vertical against a substrate of the semiconductor memory device. Each of semiconductor regions forming a source or a drain of the fifth and sixth transistors forms a PN junction against the substrate. According to another aspect of the invention, the SRAM device of the invention has a plurality of SRAM cells, at least one of which is a vertical SRAM cell comprising at least four vertical transistors onto a substrate, and each vertical transistor includes a source, a drain, and a channel therebetween aligning in one aligning line which penetrates into the substrate surface at an angle greater than zero degree.

Abstract: A switching power supply unit includes a control output circuit, a non-control output circuit, and a regulator circuit. With this switching power supply unit, it is no longer necessary to set the voltage of the non-control output to be greater than a required value when the control output circuit is unloaded or lightly loaded. The regulator circuit is connected to the non-control output circuit and includes a first transistor defining a first impedance element connected in series to the non-control output circuit, a second transistor defining a second impedance element connected between the control output circuit and the base of the first transistor, and a voltage control circuit controlling the impedance of the second transistor such that the output voltage of the regulator circuit is maintained constant.

Abstract: A gate electrode of each MISFET is formed on a substrate in an active region whose periphery is defined by an element isolation trench, and crosses the active region so as to extend from one end thereof to the other end thereof. The gate electrode has a gate length in a boundary region defined between the active region and the element isolation trench which is greater than a gate length in a central portion of the active region. The gate electrode is configured in an H-type flat pattern. Further, the gate electrode covers the whole of one side extending along a gate-length direction, of the boundary region defined between the active region L and the element isolation trench, and parts of two sides thereof extending along a gate-width direction. The MISFETs are formed in electrically separated wells and are connected in series to constitute part of a reference voltage generating circuit.

Abstract: The invention provides a semiconductor memory device comprising a plurality of word lines, a plurality of bit lines, and a plurality of static memory cells each having a first, second, third, fourth, fifth, and sixth transistors. While each of channels of the first, second, third, and fourth transistors are formed vertical against a substrate of the semiconductor memory device. Each of semiconductor regions forming a source or a drain of the fifth and sixth transistors forms a PN junction against the substrate. According to another aspect of the invention, the SRAM device of the invention has a plurality of SRAM cells, at least one of which is a vertical SRAM cell comprising at least four vertical transistors onto a substrate, and each vertical transistor includes a source, a drain, and a channel therebetween aligning in one aligning line which penetrates into the substrate surface at an angle greater than zero degree.

Abstract: A gate electrode of each MISFET is formed on a substrate in an active region whose periphery is defined by an element isolation trench, and crosses the active region so as to extend from one end thereof to the other end thereof. The gate electrode has a gate length in a boundary region defined between the active region and the element isolation trench which is greater than a gate length in a central portion of the active region. The gate electrode is configured in an H-type flat pattern. Further, the gate electrode covers the whole of one side extending along a gate-length direction, of the boundary region defined between the active region L and the element isolation trench, and parts of two sides thereof extending along a gate-width direction. The MISFETs are formed in electrically separated wells and are connected in series to constitute part of a reference voltage generating circuit.

Abstract: A switching power supply unit includes a control circuit including a turn-off circuit for turning of a first switch element Q1, which has been in an ON state, and an off-period control circuit for, based on a feedback signal from an output-voltage detecting circuit, controlling the turning-on of the first switch element to be further delayed as a load is lighter. The off-period control circuit includes a transistor as a second switch element which is provided in series between a feedback winding and the control terminal of the first switch element and which is controlled to be turned on and off based on the feedback signal from the output-voltage detecting circuit. A switching frequency is set to be lower as the load is lighter, such that power consumption at the light load is reduced.

Abstract: A switching transistor is connected to a primary winding of a transformer, an oscillation frequency control circuit is connected to a feedback winding, the oscillation frequency control circuit controls a first controlling transistor, and the first controlling transistor controls the delay time when the switching transistor is turned on. The oscillation frequency control circuit is set in a first operation mode in which the above delay does not take place at the rated load, in a second operation mode in which the oscillation frequency is controlled such that the oscillation frequency becomes constant or slowly decreases at light loading and in a third operation mode in which the oscillation frequency is further decreased while a switch is switched on.

Abstract: This semiconductor device manufacturing method comprises the steps of: forming a thick gate oxide film (thick oxide film) in a first region of a substrate, forming a thin gate oxide film (thin oxide layer) in a second region, and then, applying oxynitridation to these gate oxide films; forming gate electrodes to 1d on these gate oxide films; and implanting an ion that contains nitrogen or nitrogen atoms into at least one part of an interface between the hick gate oxide film (thick oxide film) and the substrate before or after the step of forming the gate electrodes, thereby forming a highly oxy-nitrided region. In this manner, in a semiconductor device in which there coexist a MISFET having a thin gate insulation film and a MISFET having a thick gate insulation film, hot carrier reliability of the MISFET having the thick gate insulation film is improved.