Patents by Inventor Akio SUGAHARA
Akio SUGAHARA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11093172Abstract: A semiconductor memory device includes first and second planes of memory cells, and a control circuit configured to perform a write operation on the memory cells to store first and second bits per memory cell, and to perform a first read operation using a first read voltage to read the first bits and a second read operation using second and third read voltages to read the second bits. In response to a first instruction, the control circuit performs the first and second read operations to read the first bits from the first plane and the second bits from the second plane, respectively. In response to a second read instruction, the control circuit performs the second and first read operations to read the second bits from the first plane and the first bits from the second plane, respectively.Type: GrantFiled: August 29, 2019Date of Patent: August 17, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Akio Sugahara, Masahiro Yoshihara
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Publication number: 20210210124Abstract: In one embodiment, a semiconductor storage device includes a plurality of memory chips, at least one of the memory chips including a first controller configured to be shifted to a wait state of generating a peak current, before generating the peak current in accordance with a command. The device further includes a control chip including a second controller configured to search a state of the first controller and control, based on a result of searching the state of the first controller, whether or not to issue a cancel instruction for the wait state to the first controller that has been shifted to the wait state.Type: ApplicationFiled: March 16, 2021Publication date: July 8, 2021Applicant: TOSHIBA MEMORY CORPORATIONInventors: Akio SUGAHARA, Yoshikazu HARADA, Shoichiro HASHIMOTO
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Publication number: 20210202007Abstract: A semiconductor memory device according to an embodiment includes a plurality of planes including a plurality of blocks each being a set of memory cells, and a sequencer configured to execute a first operation, and a second operation shorter than the first operation. Upon receiving a first command set that instructs execution of the first operation, the sequencer is configured to execute the first operation. Upon receiving a second command set that instructs execution of the second operation while the first operation is being executed, the sequencer is configured to suspend the first operation and execute the second operation or execute the second operation in parallel with the first operation, based on an address of a block that is a target of the first operation and an address of a block that is a target of the second operation.Type: ApplicationFiled: March 15, 2021Publication date: July 1, 2021Applicant: Kioxia CorporationInventors: Akio SUGAHARA, Akihiro IMAMOTO, Toshifumi WATANABE, Mami KAKOI, Kohei MASUDA, Masahiro YOSHIHARA, Naofumi ABIKO
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Publication number: 20210158879Abstract: A method of controlling a memory device includes receiving an address indicating a region in a memory cell array and generating one or more voltages supplied to the memory cell array in parallel with receiving the address.Type: ApplicationFiled: February 5, 2021Publication date: May 27, 2021Applicant: TOSHIBA MEMORY CORPORATIONInventors: Akio SUGAHARA, Takaya HANDA, Ryosuke ISOMURA, Kazuto UEHARA, Junichi SATO, Norichika ASAOKA, Masashi YAMAOKA, Bushnaq SANAD, Yuzuru SHIBAZAKI, Noriyasu KUMAZAKI, Yuri TERADA
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Publication number: 20210142833Abstract: A semiconductor storage device includes a sense amplifier configured to read and program data in memory cells, a first latch circuit to store read data or program data, a second latch circuit to store the first data transferred from the first latch circuit or the second data before the second data is transferred into the first latch circuit, an input/output circuit to output the first data stored in the second latch circuit and to transfer the second data received thereby to the second latch circuit, and a control circuit. Upon receiving a read command while the control circuit is performing a program operation on program data stored in second latch circuit, the control circuit interrupts the program operation to perform the read operation and resumes the program operation on the program data in response to a resume write command sequence that does not include the program data.Type: ApplicationFiled: January 19, 2021Publication date: May 13, 2021Inventors: Junichi SATO, Akio SUGAHARA
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Patent number: 10991402Abstract: In one embodiment, a semiconductor storage device includes a plurality of memory chips, at least one of the memory chips including a first controller configured to be shifted to a wait state of generating a peak current, before generating the peak current in accordance with a command. The device further includes a control chip including a second controller configured to search a state of the first controller and control, based on a result of searching the state of the first controller, whether or not to issue a cancel instruction for the wait state to the first controller that has been shifted to the wait state.Type: GrantFiled: April 2, 2020Date of Patent: April 27, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Akio Sugahara, Yoshikazu Harada, Shoichiro Hashimoto
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Publication number: 20210090643Abstract: According to one embodiment, a memory system includes n memory cells, each capable of storing j bits of data; and a controller. The controller is configured to write a first portion of each of first data to n-th data from among n×j data with consecutive logical addresses to the n memory cells one by one. The first data has a lowest logical address among the n×j pieces of data. The first data to the n-th data have ascending consecutive logical addresses. The controller is configured to write the first portion of one of the first to n-th data as a first bit of the j bits, and write the first portion of another one of the first to n-th data except said one of the first to n-th data as a second bit of the j bits.Type: ApplicationFiled: September 11, 2020Publication date: March 25, 2021Applicant: Kioxia CorporationInventors: Naomi TAKEDA, Masanobu SHIRAKAWA, Akio SUGAHARA
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Patent number: 10957404Abstract: According one embodiment, a memory device includes: a memory cell array; a voltage generation circuit generating one or more voltages supplied to the memory cell array; an input/output circuit receiving an address indicating a region in the memory cell array; and a control circuit controlling operations of the memory cell array. The voltage generation circuit generates the voltages during reception of the address.Type: GrantFiled: September 11, 2019Date of Patent: March 23, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Akio Sugahara, Takaya Handa, Ryosuke Isomura, Kazuto Uehara, Junichi Sato, Norichika Asaoka, Masashi Yamaoka, Bushnaq Sanad, Yuzuru Shibazaki, Noriyasu Kumazaki, Yuri Terada
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Publication number: 20210055887Abstract: A memory device includes a memory cell array configured to store data, a control circuit configured to control the memory cell array in response to a command; and a receiver configured to be placed in an active state based on a first signal, a second signal, or an operation result of an address and the command, and be enabled to receive a command or data.Type: ApplicationFiled: November 6, 2020Publication date: February 25, 2021Applicant: TOSHIBA MEMORY CORPORATIONInventors: Akio SUGAHARA, Yuji NAGAI
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Patent number: 10930357Abstract: A semiconductor storage device includes a memory cell array, a temperature sensor configured to generate a first temperature signal corresponding to a temperature of the memory cell array in response to a first command periodically generated during a waiting period of the memory cell array, a storage circuit configured to store the first temperature signal and update the first temperature signal each time the first command is generated during the waiting period, and a voltage generation circuit configured to generate a voltage to be applied to the memory cell array based on the first temperature signal stored in the storage circuit.Type: GrantFiled: August 29, 2019Date of Patent: February 23, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Yuri Terada, Noriyasu Kumazaki, Yasufumi Kajiyama, Akio Sugahara, Masahiro Yoshihara
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Patent number: 10910023Abstract: A semiconductor storage device includes a sense amplifier configured to read and program data in memory cells, a first latch circuit to store read data or program data, a second latch circuit to store the first data transferred from the first latch circuit or the second data before the second data is transferred into the first latch circuit, an input/output circuit to output the first data stored in the second latch circuit and to transfer the second data received thereby to the second latch circuit, and a control circuit. Upon receiving a read command while the control circuit is performing a program operation on program data stored in second latch circuit, the control circuit interrupts the program operation to perform the read operation and resumes the program operation on the program data in response to a resume write command sequence that does not include the program data.Type: GrantFiled: August 5, 2020Date of Patent: February 2, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Junichi Sato, Akio Sugahara
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Publication number: 20200402550Abstract: A semiconductor storage device includes a sense amplifier configured to read and program data in memory cells, a first latch circuit to store read data or program data, a second latch circuit to store the first data transferred from the first latch circuit or the second data before the second data is transferred into the first latch circuit, an input/output circuit to output the first data stored in the second latch circuit and to transfer the second data received thereby to the second latch circuit, and a control circuit. Upon receiving a read command while the control circuit is performing a program operation on program data stored in second latch circuit, the control circuit interrupts the program operation to perform the read operation and resumes the program operation on the program data in response to a resume write command sequence that does not include the program data.Type: ApplicationFiled: August 5, 2020Publication date: December 24, 2020Inventors: Junichi SATO, Akio SUGAHARA
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Patent number: 10860250Abstract: A memory device includes a memory cell array configured to store data, a control circuit configured to control the memory cell array in response to a command; and a receiver configured to be placed in an active state based on a first signal, a second signal, or an operation result of an address and the command, and be enabled to receive a command or data.Type: GrantFiled: January 11, 2019Date of Patent: December 8, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Akio Sugahara, Yuji Nagai
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Publication number: 20200294604Abstract: A semiconductor storage device includes first and second planes each including a plurality of memory cells, an input/output circuit configured to receive data to be written in the memory cells from a controller, and a control circuit. The first plane includes a first sense amplifier circuit electrically connected to a first memory cell of the first plane and a first latch circuit connected in series between the input/output circuit and the first sense amplifier circuit. The control circuit is configured to carry out a first write operation on the first memory cell using the first latch circuit in response to a first command, and while carrying out the first write operation on the first memory cell, accept a second command to carry out a second write operation on a second memory cell of the second plane before use of the first latch circuit during the first write operation has ended.Type: ApplicationFiled: June 2, 2020Publication date: September 17, 2020Inventors: Akihiro IMAMOTO, Akio SUGAHARA
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Patent number: 10777239Abstract: A semiconductor storage device includes a sense amplifier configured to read and program data in memory cells, a first latch circuit to store read data or program data, a second latch circuit to store the first data transferred from the first latch circuit or the second data before the second data is transferred into the first latch circuit, an input/output circuit to output the first data stored in the second latch circuit and to transfer the second data received thereby to the second latch circuit, and a control circuit. Upon receiving a read command while the control circuit is performing a program operation on program data stored in second latch circuit, the control circuit interrupts the program operation to perform the read operation and resumes the program operation on the program data in response to a resume write command sequence that does not include the program data.Type: GrantFiled: August 29, 2018Date of Patent: September 15, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Junichi Sato, Akio Sugahara
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Publication number: 20200241796Abstract: A semiconductor memory device includes first and second planes of memory cells, and a control circuit configured to perform a write operation on the memory cells to store first and second bits per memory cell, and to perform a first read operation using a first read voltage to read the first bits and a second read operation using second and third read voltages to read the second bits. In response to a first instruction, the control circuit performs the first and second read operations to read the first bits from the first plane and the second bits from the second plane, respectively. In response to a second read instruction, the control circuit performs the second and first read operations to read the second bits from the first plane and the first bits from the second plane, respectively.Type: ApplicationFiled: August 29, 2019Publication date: July 30, 2020Inventors: Akio SUGAHARA, Masahiro YOSHIHARA
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Publication number: 20200234744Abstract: In one embodiment, a semiconductor storage device includes a plurality of memory chips, at least one of the memory chips including a first controller configured to be shifted to a wait state of generating a peak current, before generating the peak current in accordance with a command. The device further includes a control chip including a second controller configured to search a state of the first controller and control, based on a result of searching the state of the first controller, whether or not to issue a cancel instruction for the wait state to the first controller that has been shifted to the wait state.Type: ApplicationFiled: April 2, 2020Publication date: July 23, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventors: Akio SUGAHARA, Yoshikazu HARADA, Shoichiro HASHIMOTO
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Publication number: 20200202958Abstract: According one embodiment, a memory device includes: a memory cell array; a voltage generation circuit generating one or more voltages supplied to the memory cell array; an input/output circuit receiving an address indicating a region in the memory cell array; and a control circuit controlling operations of the memory cell array. The voltage generation circuit generates the voltages during reception of the address.Type: ApplicationFiled: September 11, 2019Publication date: June 25, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventors: Akio SUGAHARA, Takaya HANDA, Ryosuke ISOMURA, Kazuto UEHARA, Junichi SATO, Norichika ASAOKA, Masashi YAMAOKA, Bushnaq SANAD, Yuzuru SHIBAZAKI, Noriyasu KUMAZAKI, Yuri TERADA
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Publication number: 20200202957Abstract: A semiconductor storage device includes a memory cell array, a temperature sensor configured to generate a first temperature signal corresponding to a temperature of the memory cell array in response to a first command periodically generated during a waiting period of the memory cell array, a storage circuit configured to store the first temperature signal and update the first temperature signal each time the first command is generated during the waiting period, and a voltage generation circuit configured to generate a voltage to be applied to the memory cell array based on the first temperature signal stored in the storage circuit.Type: ApplicationFiled: August 29, 2019Publication date: June 25, 2020Inventors: Yuri TERADA, Noriyasu KUMAZAKI, Yasufumi KAJIYAMA, Akio SUGAHARA, Masahiro YOSHIHARA
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Patent number: 10679706Abstract: A semiconductor storage device includes first and second planes each including a plurality of memory cells, an input/output circuit configured to receive data to be written in the memory cells from a controller, and a control circuit. The first plane includes a first sense amplifier circuit electrically connected to a first memory cell of the first plane and a first latch circuit connected in series between the input/output circuit and the first sense amplifier circuit. The control circuit is configured to carry out a first write operation on the first memory cell using the first latch circuit in response to a first command, and while carrying out the first write operation on the first memory cell, accept a second command to carry out a second write operation on a second memory cell of the second plane before use of the first latch circuit during the first write operation has ended.Type: GrantFiled: February 26, 2019Date of Patent: June 9, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Akihiro Imamoto, Akio Sugahara