Abstract: In one embodiment, a semiconductor storage device includes a plurality of memory chips, at least one of the memory chips including a first controller configured to be shifted to a wait state of generating a peak current, before generating the peak current in accordance with a command. The device further includes a control chip including a second controller configured to search a state of the first controller and control, based on a result of searching the state of the first controller, whether or not to issue a cancel instruction for the wait state to the first controller that has been shifted to the wait state.

Abstract: A semiconductor storage device includes first and second planes each including a plurality of memory cells, an input/output circuit configured to receive data to be written in the memory cells from a controller, and a control circuit. The first plane includes a first sense amplifier circuit electrically connected to a first memory cell of the first plane and a first latch circuit connected in series between the input/output circuit and the first sense amplifier circuit. The control circuit is configured to carry out a first write operation on the first memory cell using the first latch circuit in response to a first command, and while carrying out the first write operation on the first memory cell, accept a second command to carry out a second write operation on a second memory cell of the second plane before use of the first latch circuit during the first write operation has ended.

Abstract: A non-volatile semiconductor storage device includes a memory cell array and a control circuit configured to control a data write operation for the memory cell array in a first or second write mode in response to a write command sequence. In the first write mode, the control circuit performs a first write operation, which includes an operation in which one or more bit lines are charged according to write data and an operation in which a write voltage is applied to a selected word line according to address data included in the write command sequence. In the second write mode, the control circuit performs a second write operation, which includes the operation in which the one or more bit lines are charged according to the write data and does not include the operation in which the write voltage is applied to the selected word line.

Abstract: A semiconductor storage device includes a sense amplifier configured to read and program data in memory cells, a first latch circuit to store read data or program data, a second latch circuit to store the first data transferred from the first latch circuit or the second data before the second data is transferred into the first latch circuit, an input/output circuit to output the first data stored in the second latch circuit and to transfer the second data received thereby to the second latch circuit, and a control circuit. Upon receiving a read command while the control circuit is performing a program operation on program data stored in second latch circuit, the control circuit interrupts the program operation to perform the read operation and resumes the program operation on the program data in response to a resume write command sequence that does not include the program data.

Abstract: In one embodiment, a semiconductor storage device includes a plurality of memory chips, at least one of the memory chips including a first controller configured to be shifted to a wait state of generating a peak current, before generating the peak current in accordance with a command. The device further includes a control chip including a second controller configured to search a state of the first controller and control, based on a result of searching the state of the first controller, whether or not to issue a cancel instruction for the wait state to the first controller that has been shifted to the wait state.

Abstract: A memory device includes a memory cell array configured to store data, a control circuit configured to control the memory cell array in response to a command; and a receiver configured to be placed in an active state based on a first signal, a second signal, or an operation result of an address and the command, and be enabled to receive a command or data.

Abstract: In one embodiment, a semiconductor storage device includes a plurality of memory chips, at least one of the memory chips including a first controller configured to be shifted to a wait state of generating a peak current, before generating the peak current in accordance with a command. The device further includes a control chip including a second controller configured to search a state of the first controller and control, based on a result of searching the state of the first controller, whether or not to issue a cancel instruction for the wait state to the first controller that has been shifted to the wait state.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell, a bit line, a sense amplifier, a word line, and a row decoder. A write operation repeats a program loop including a program operation, first and second verify operations. The row decoder applies a first read voltage to the word line in the first and second verify operations. When the write operation is not suspended, the sense amplifier senses a voltage of the bit line for a first sense period in the first verify operation. When the write operation is suspended, the sense amplifier senses the voltage of the bit line for a second sense period shorter than the first sense period in the initial first verify operation after a resumption of the write operation.

Abstract: A semiconductor memory device includes first and second planes, first and second latch circuits for the first plane of memory cells, wherein data stored in the first latch circuit is transferred to the first plane of memory cells via the second latch circuit, third and fourth latch circuits for the second plane of memory cells, wherein data stored in the third latch circuit is transferred to the second plane of memory cells via the fourth latch circuit, and a control circuit configured to perform a sequence of operations in response to commands, the sequence of operations including a first operation to transfer first data associated with the commands from the first latch circuit to the second latch circuit and, concurrently with the first operation, a second operation to transfer second data associated with the commands into the third latch circuit.

Abstract: According to one embodiment, a semiconductor storage device includes a plurality of semiconductor chips and a control unit. The plurality of semiconductor chips is configured to connect to a signal transmission path and is controlled individually by individual chip enable signals. The plurality of semiconductor chips each includes a termination circuit connected to the signal transmission path. When one of the semiconductor chips is selected to input or output data, the control unit activates the termination circuit provided in the semiconductor chip that is not selected based on a first instruction signal and the chip enable signal.

Abstract: In one embodiment, a semiconductor storage device includes a plurality of memory chips, at least one of the memory chips including a first controller configured to be shifted to a wait state of generating a peak current, before generating the peak current in accordance with a command. The device further includes a control chip including a second controller configured to search a state of the first controller and control, based on a result of searching the state of the first controller, whether or not to issue a cancel instruction for the wait state to the first controller that has been shifted to the wait state.

Abstract: A non-volatile semiconductor storage device includes a memory cell array and a control circuit configured to control a data write operation for the memory cell array in a first or second write mode in response to a write command sequence. In the first write mode, the control circuit performs a first write operation, which includes an operation in which one or more bit lines are charged according to write data and an operation in which a write voltage is applied to a selected word line according to address data included in the write command sequence. In the second write mode, the control circuit performs a second write operation, which includes the operation in which the one or more bit lines are charged according to the write data and does not include the operation in which the write voltage is applied to the selected word line.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell, a bit line, a sense amplifier, a word line, and a row decoder. A write operation repeats a program loop including a program operation, first and second verify operations. The row decoder applies a first read voltage to the word line in the first and second verify operations. When the write operation is not suspended, the sense amplifier senses a voltage of the bit line for a first sense period in the first verify operation. When the write operation is suspended, the sense amplifier senses the voltage of the bit line for a second sense period shorter than the first sense period in the initial first verify operation after a resumption of the write operation.

Abstract: According to one embodiment, a semiconductor storage device includes a plurality of semiconductor chips and a control unit. The plurality of semiconductor chips is configured to connect to a signal transmission path and is controlled individually by individual chip enable signals. The plurality of semiconductor chips each includes a termination circuit connected to the signal transmission path. When one of the semiconductor chips is selected to input or output data, the control unit activates the termination circuit provided in the semiconductor chip that is not selected based on a first instruction signal and the chip enable signal.

Abstract: A semiconductor memory device includes memory cells, a sense amplifier unit including a first latch circuit, and a control unit configured to execute read and write operations on the memory cells. The control unit, while executing the write operation on the memory cells, responsive to a write suspend command followed by a read command, performs a data saving operation, the read operation, and a data restoring operation prior to resuming the write operation. The data saving operation includes transferring first data stored in the first latch circuit to an external device, the first data including at least a result of verify operation performed on the memory cells. The data restoring operation includes transferring the first data to the first latch circuit.

Abstract: According to one embodiment, a semiconductor storage device includes a plurality of semiconductor chips and a control unit. The plurality of semiconductor chips is configured to connect to a signal transmission path and is controlled individually by individual chip enable signals. The plurality of semiconductor chips each includes a termination circuit connected to the signal transmission path. When one of the semiconductor chips is selected to input or output data, the control unit activates the termination circuit provided in the semiconductor chip that is not selected based on a first instruction signal and the chip enable signal.

Abstract: A semiconductor memory device includes memory cells, a sense amplifier unit including a first latch circuit, and a control unit configured to execute read and write operations on the memory cells. The control unit, while executing the write operation on the memory cells, responsive to a write suspend command followed by a read command, performs a data saving operation, the read operation, and a data restoring operation prior to resuming the write operation. The data saving operation includes transferring first data stored in the first latch circuit to an external device, the first data including at least a result of verify operation performed on the memory cells. The data restoring operation includes transferring the first data to the first latch circuit.

Abstract: According to one embodiment, a semiconductor storage device includes a plurality of semiconductor chips and a control unit. The plurality of semiconductor chips is configured to connect to a signal transmission path and is controlled individually by individual chip enable signals. The plurality of semiconductor chips each includes a termination circuit connected to the signal transmission path. When one of the semiconductor chips is selected to input or output data, the control unit activates the termination circuit provided in the semiconductor chip that is not selected based on a first instruction signal and the chip enable signal.

Abstract: According to one embodiment, a semiconductor storage device includes a plurality of semiconductor chips and a control unit. The plurality of semiconductor chips is configured to connect to a signal transmission path and is controlled individually by individual chip enable signals. The plurality of semiconductor chips each includes a termination circuit connected to the signal transmission path. When one of the semiconductor chips is selected to input or output data, the control unit activates the termination circuit provided in the semiconductor chip that is not selected based on a first instruction signal and the chip enable signal.

Abstract: A semiconductor memory device includes a memory cell array, a sense amplifier, a register, a controller. The memory cell array includes a memory cell. The sense amplifier connects to the bit line. The register holds write data, and a write voltage. The controller outputs a busy signal. The controller causes the register to hold the write data and the write voltage upon receiving the first command, and resumes the write operation based on the write data and the write voltage held in the register upon receiving the resumption command.