Patents by Inventor Akira Furuya

Akira Furuya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120134065
    Abstract: An electrostatic chuck device including: a plurality of adsorption areas having an electrode generating electrostatic attractive force; and a control portion controlling the electrostatic attractive force against each of the plurality of the adsorption areas independently of other adsorption areas.
    Type: Application
    Filed: November 28, 2011
    Publication date: May 31, 2012
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Akira Furuya, Takamitsu Kitamura
  • Publication number: 20120003821
    Abstract: A method for fabricating a semiconductor device includes performing thermal cleaning for a surface of a silicon substrate in an atmosphere including hydrogen under a condition that a thermal cleaning temperature is higher than or equal to 700° C. and is lower than or equal to 1060° C., and a thermal cleaning time is longer than or equal to 5 minutes and is shorter than or equal to 15 minutes; forming a first AlN layer on the substrate with a first V/III source ratio, the forming of the first AlN layer including supplying an Al source to the surface of the substrate without supplying a N source, and supplying both the Al source and the N source; forming a second AlN layer on the first AlN layer with a second V/III source ratio that is greater than the first ratio; and forming a GaN-based semiconductor layer on the second AlN layer.
    Type: Application
    Filed: June 29, 2011
    Publication date: January 5, 2012
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Keiichi Yui, Akira Furuya, Ken Nakata, Takamitsu Kitamura, Isao Makabe
  • Publication number: 20120003820
    Abstract: A method for fabricating a semiconductor device includes forming an AlN layer on a substrate made of silicon by supplying an Al source without supplying a N source and then supplying both the Al source and the N source, and forming a GaN-based semiconductor layer on the AlN layer after the forming of the AlN layer. The forming of the AlN layer grows the AlN layer so as to satisfy the following: 76500/x0.81y<53800/x0.83 where x is a thickness of the AlN layer and y is an FWHM of a rocking curve of a (002) plane of the AlN layer.
    Type: Application
    Filed: June 29, 2011
    Publication date: January 5, 2012
    Applicant: SUMITOMO ELECTRIC INDUSTRIES LTD.
    Inventors: Keiichi Yui, Isao Makabe, Ken Nakata, Takamitsu Kitamura, Akira Furuya
  • Patent number: 8025707
    Abstract: A tubular channel is disposed in a path of air that flows from an inlet to a dirty side. The cross sectional area of the tubular channel is smaller than the cross-sectional area of the inlet. A dust outlet is disposed in a wall in a path of the air that flows out of the exit of the tubular channels to the dirty side. The dust outlet extends through the wall of the air cleaner from the inside to the outside. As the air blasts out of the dust outlet, dust in the air cleaner is discharged to the outside.
    Type: Grant
    Filed: December 18, 2008
    Date of Patent: September 27, 2011
    Assignee: Fuji Jukogyo Kabushiki Kaisha
    Inventor: Akira Furuya
  • Patent number: 8013257
    Abstract: The present invention provides an electronic component which is capable of effectively suppressing the characteristic deterioration of the passive element portion. An electronic component comprises a ceramic substrate, a passive element portion on the substrate, an insulator layer which is provided over the passive element portion and comprises a through-hole, a lead terminal which is fitted in the through-hole of the insulator layer and electrically connected to the passive element portion, and an external connection terminal which is electrically connected to the lead terminal. The insulator layer comprises a first face on the side of the passive element portion, a second face on the side opposite the passive element portion, and a third face which connects the first face and the second face and constitutes the peripheral face of the insulator layer, the external connection terminal is in contact with the lead terminal and the second face and the third face of the insulator layer.
    Type: Grant
    Filed: December 24, 2008
    Date of Patent: September 6, 2011
    Assignee: TDK Corporation
    Inventors: Akira Furuya, Masahiro Miyazaki, Hiroshi Take, Keisuke Takasugi
  • Publication number: 20110155578
    Abstract: An objective of this invention is to reliably form a plating film. The following two steps are sequentially conducted: step 101 of connecting a film-formation surface of a wafer 109 to a cathode electrode 107, making the film-formation surface inclined from the surface of a plating solution 103 and immersing the wafer 109 into the plating solution 103 with applying a first current between the cathode electrode 107 and an Cu anode electrode 105 disposed in the plating solution 103, and step 103 of, after immersing the film-formation surface in the plating solution 103, applying a second current between the cathode electrode 107 and the Cu anode electrode 105 to form a metal film on the film-formation surface by electrolytic plating. In step 101, the first current is controlled on the basis of an inclination angle between the liquid surface and the film-formation surface.
    Type: Application
    Filed: March 9, 2011
    Publication date: June 30, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Akira FURUYA, Yasuaki TSUCHIYA
  • Publication number: 20110079909
    Abstract: A generation of a void in a recessed section is inhibited. A method for manufacturing a semiconductor device includes: an operation of forming recessed sections in an insulating film, which is formed on a semiconductor substrate; an operation of forming a seed film in the recessed section; an operation of forming a cover metal film in the recessed section; an operation of selectively removing the cover metal film to expose the seed film over the bottom section of the recessed section; and an operation to carrying out a growth of a plated film to fill the recessed section by utilizing the seed film exposed in the bottom section of the recessed section as a seed.
    Type: Application
    Filed: October 5, 2010
    Publication date: April 7, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Akira FURUYA
  • Patent number: 7883935
    Abstract: Aimed at improving adhesiveness between upper and lower interconnects in semiconductor devices, a semiconductor device of the present invention includes a second dielectric multi-layered film formed on a substrate, and containing a lower interconnect; a first dielectric multi-layered film formed on the second dielectric multi-layered film, and having a recess; an MOx film formed on the inner wall of the recess, and containing a metal M and oxygen as major components; an M film formed on the MOx film, and containing the M as a major component; and an electric conductor formed on the M film so as to fill the recess, and containing Cu as a major component, wherein the surficial portion of the interconnect fallen straight under the bottom of the recess has an oxygen concentration of 1% or smaller.
    Type: Grant
    Filed: April 12, 2010
    Date of Patent: February 8, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Akira Furuya
  • Patent number: 7859080
    Abstract: The invention provides an electronic component which has an improved breakdown limit value of withstand voltage and improved insulation properties and which can be made compact and provided with a multiplicity of layers and a great capacity. The electronic component includes a first conductor having a bottom conductor formed on a substrate and a raised conductor formed to protrude from the bottom conductor, a dielectric film formed on the raised conductor, and a second conductor formed on the dielectric film to constitute a capacitor element in combination with the raised conductor and the dielectric film.
    Type: Grant
    Filed: December 1, 2006
    Date of Patent: December 28, 2010
    Assignee: TDK Corporation
    Inventors: Hajime Kuwajima, Akira Furuya, Masahiro Miyazaki, Makoto Shibata
  • Patent number: 7854824
    Abstract: A method of manufacturing a semiconductor device includes measuring the reflectance at the surface of a semiconductor substrate provided with concave portions and deciding a deposition parameter that represents a deposition condition corresponding to the measured reflectance. Then, a metal film is formed on the semiconductor substrate under a condition corresponding to the deposition parameter.
    Type: Grant
    Filed: February 12, 2008
    Date of Patent: December 21, 2010
    Assignee: Renesas Electronics Corporation
    Inventor: Akira Furuya
  • Publication number: 20100246090
    Abstract: To provide a thin film capacitor having a device structure for suppressing peeling between an insulating film and a substrate. A thin film capacitor 100 has a laminate structure that is formed by laminating a lower electrode 20, a dielectric film 30, and an upper electrode 40 in sequence on a substrate 10. An adhesion layer 41 is formed on a side surface of the lower electrode 20 via the dielectric film 30, and an insulating film 50 in contact with the adhesion layer 41 covers the laminate structure. According to this device structure, the adhesion layer 41 having excellent adhesiveness to the insulating film 50 is disposed between the insulating film 50 and the dielectric film 30, so that peeling of the insulating film 50 can be suppressed.
    Type: Application
    Filed: March 4, 2010
    Publication date: September 30, 2010
    Applicant: TDK CORPORATION
    Inventors: Toshiyuki YOSHIZAWA, Akira FURUYA, Masaomi ISHIKURA, Keisuke TAKASUGI, Hiroshi TAKE
  • Patent number: 7800229
    Abstract: An improved SIV resistance and an improved EM resistance are achieved in the coupling structure containing copper films. A semiconductor device includes: a semiconductor substrate; a second insulating layer formed on or over the semiconductor substrate; a second barrier metal film, formed on the second insulating film, and being capable of preventing copper from diffusing into the second insulating film; and an electrically conducting film formed on the second barrier metal film so as to be in contact with the second barrier metal film, and containing copper and carbon, wherein a distribution of carbon concentration along a depositing direction in the second electrically conducting film includes a first peak and a second peak.
    Type: Grant
    Filed: February 12, 2007
    Date of Patent: September 21, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Akira Furuya, Koji Arita, Tetsuya Kurokawa, Kaori Noda
  • Publication number: 20100210102
    Abstract: Aimed at improving adhesiveness between upper and lower interconnects in semiconductor devices, a semiconductor device of the present invention includes a second dielectric multi-layered film formed on a substrate, and containing a lower interconnect; a first dielectric multi-layered film formed on the second dielectric multi-layered film, and having a recess; an MOx film formed on the inner wall of the recess, and containing a metal M and oxygen as major components; an M film formed on the MOx film, and containing the M as a major component; and an electric conductor formed on the M film so as to fill the recess, and containing Cu as a major component, wherein the surficial portion of the interconnect fallen straight under the bottom of the recess has an oxygen concentration of 1% or smaller.
    Type: Application
    Filed: April 12, 2010
    Publication date: August 19, 2010
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Akira FURUYA
  • Patent number: 7755191
    Abstract: A semiconductor device includes a first copper-containing conductive film formed on a substrate, insulating films formed on the first copper-containing conductive film with a concave portion reaching the first copper-containing conductive film, a second barrier insulating film formed to cover the side wall of the concave portion of these insulating films, a second adhesive alloy film made of copper and a dissimilar element other than copper, and coming in contact with the first copper-containing conductive film at the bottom surface of the concave portion and in contact with the second barrier insulating film at the side wall of the concave portion to cover the inside wall of the concave portion, and a second copper-containing conductive film containing copper as a main component, and formed on the second adhesive alloy film in contact with the second adhesive alloy film to fill the concave portion.
    Type: Grant
    Filed: March 20, 2007
    Date of Patent: July 13, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Akira Furuya
  • Patent number: 7745240
    Abstract: A manufacturing method of a light-emitting element includes emitting a laser light to a division region for separating a light-emitting element formed on a substrate, physically dividing the substrate along the division region, and removing a surface layer on at least one of the side faces of the substrate that is exposed by the dividing of the substrate.
    Type: Grant
    Filed: July 12, 2007
    Date of Patent: June 29, 2010
    Assignee: Eudyna Devices Inc.
    Inventor: Akira Furuya
  • Patent number: 7737037
    Abstract: An object of the invention is to provide a semiconductor device which includes a barrier metal having high adhesiveness and diffusion barrier properties and a method of manufacturing the semiconductor device. The invention provides a semiconductor device manufacturing method including forming a first layer made of a material containing silicon on a base substance; forming a second layer containing metal and nitrogen on the first layer; and exposing the second layer to active species obtained from plasma in an atmosphere including reducing gas.
    Type: Grant
    Filed: July 23, 2008
    Date of Patent: June 15, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Akira Furuya, Nobuyuki Otsuka, Hiroshi Okamura, Shinichi Ogawa
  • Patent number: 7728434
    Abstract: Aimed at improving adhesiveness between upper and lower interconnects in semiconductor devices, a semiconductor device of the present invention includes a second dielectric multi-layered film formed on a substrate, and containing a lower interconnect; a first dielectric multi-layered film formed on the second dielectric multi-layered film, and having a recess; an MOx film formed on the inner wall of the recess, and containing a metal M and oxygen as major components; an M film formed on the MOx film, and containing the M as a major component; and an electric conductor formed on the M film so as to fill the recess, and containing Cu as a major component, wherein the surficial portion of the interconnect fallen straight under the bottom of the recess has an oxygen concentration of 1% or smaller.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: June 1, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Akira Furuya
  • Publication number: 20100127404
    Abstract: In a method for manufacturing a semiconductor device, insulation resistance of the porous film is stabilized, and leakage current between adjacent interconnects provides an improved reliability in signal propagation therethrough. The method includes: sequentially forming over a semiconductor substrate a porous film and a patterned resist film; forming a concave exposed surface of the substrate; forming a non-porous film covering the interior wall of the concave portion and the porous film; selectively removing the non-porous film from the bottom of the concave portion and the non-porous film by anisotropic etch; forming a barrier metal film covering the porous film and the interior wall; and forming a metallic film on the barrier metal film to fill the concave portion. The anisotropic etch process uses an etching gas with mixing ratio MR, 45?MR?100, where MR=((gaseous “nitrogen” containing compound)+(inert gas))/(gaseous “fluorine” containing compound).
    Type: Application
    Filed: January 19, 2010
    Publication date: May 27, 2010
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Akira FURUYA
  • Publication number: 20100116535
    Abstract: A thin-film device incorporates a device main body and four terminal electrodes. The device main body has four side surfaces. The terminal electrodes are disposed to touch respective portions of the side surfaces. The device main body includes a lower conductor layer that is not used to form a passive element, and an upper conductor layer used to form the passive element. The upper and lower conductor layers include respective lead electrode portions that have respective end faces located at the side surfaces of the device main body. At the side surfaces of the device main body, the end face of the lead electrode portion of the lower conductor layer and the end face of the lead electrode portion of the upper conductor layer are electrically and physically connected to each other. The terminal electrodes touch these end faces and are thereby connected to the upper and lower conductor layers.
    Type: Application
    Filed: January 15, 2010
    Publication date: May 13, 2010
    Applicant: TDK Corporation
    Inventors: Hajime Kuwajima, Masahiro Miyazaki, Akira Furuya
  • Patent number: 7683740
    Abstract: An electronic component having: a substrate, a lower conductor layer provided on the substrate; an inorganic dielectric film that covers the lower conductor layer; and an upper conductor layer having an upper electrode portion provided on the inorganic dielectric film. The lower conductor layer has a lower electrode portion that together with the upper electrode portion and the inorganic dielectric film constitutes a capacitor, and a coil portion that constitutes an inductor. The entire inorganic dielectric film is formed integrally, and the lower conductor layer is in contact only with the substrate, inorganic dielectric film, and upper conductor layer.
    Type: Grant
    Filed: July 24, 2007
    Date of Patent: March 23, 2010
    Assignee: TDK Corporation
    Inventors: Toshiyuki Yoshizawa, Masahiro Miyazaki, Akira Furuya, Masaomi Ishikura, Hajime Kuwajima