Abstract: In one embodiment, a semiconductor device includes a first diffusion layer of a first conductivity type and a second diffusion layer of a second conductivity type that are provided in a semiconductor layer at a distance, the second conductivity type being an opposite conductivity type of the first conductivity type, a first insulating film and a second insulating film that are provided on the semiconductor layer between the first diffusion layer and the second diffusion layer at a distance, a gate electrode provided on the first insulating film, and a threshold regulating electrode provided on the second insulating film.

Abstract: In one embodiment, a semiconductor device includes a substrate, a gate insulator on the substrate, and a gate electrode on the gate insulator. The device further includes a source diffusion layer of a first conductivity type and a drain diffusion layer of a second conductivity type disposed on a surface of the substrate so as to sandwich the gate electrode. The device further includes a junction forming region disposed between the source diffusion layer and the drain diffusion layer so as to contact the source diffusion layer. The junction forming region includes a source extension layer of the first conductivity type, a pocket layer of the second conductivity type above the source extension layer, and a diffusion suppressing layer disposed between the source extension layer and the pocket layer and containing carbon so as to suppress diffusion of impurities between the source extension layer and the pocket layer.

Abstract: In one embodiment, a semiconductor device includes a first diffusion layer of a first conductivity type and a second diffusion layer of a second conductivity type that are provided in a semiconductor layer at a distance, the second conductivity type being an opposite conductivity type of the first conductivity type, a first insulating film and a second insulating film that are provided on the semiconductor layer between the first diffusion layer and the second diffusion layer at a distance, a gate electrode provided on the first insulating film, and a threshold regulating electrode provided on the second insulating film.

Abstract: In one embodiment, a semiconductor device includes a first diffusion layer of a first conductive type and a second diffusion layer of a second conductive type which is a reverse conductive type of the first conductive type, the first conductive type first diffusion layer and the second conductive type diffusion layer being spaced apart and provided in a semiconductor layer, a pocket region of the second conductive type which is provided on a surface portion of the semiconductor layer adjacently to the first diffusion layer, and a first extension region of the first conductive type which is provided in the semiconductor layer to cover at least a portion of the pocket region. A second diffusion layer side end portion of the first extension region is positioned closer to a second diffusion layer side than a second diffusion layer side end portion of the pocket region.

Abstract: According to one embodiment, a MOS semiconductor device comprises a first gate insulating film formed on a region of part of a channel of a semiconductor substrate, in which a transistor is to be formed, a first gate electrode formed on the first gate insulating film, a second gate insulating film formed on remaining part of the channel, the second gate insulating film including an impurity added to the second gate insulating film to increase a threshold value of the channel immediately under the second gate insulating film, and a second gate electrode formed on the second gate insulating film.

Abstract: Structures and methods are presented relating to formation of finFET semiconducting devices. A finFET device is presented comprising fin(s) formed on a substrate, wherein the fin(s) has a needle-shaped profile. The needle-shaped profile, in conjunction with at least a buffer layer or a doped layer, epitaxially formed on the fin(s), facilitates strain to be induced into the fin(s) by the buffer layer or the doped layer. The fin(s) can comprise silicon aligned on a first plane, while at least one of the buffer layer or the doped layer are grown on a second plane, the alignment of the first and second planes are disparate and are selected such that formation of the buffer layer or the doped layer generates a stress in the fin(s). The generated stress results in a strain being induced into the fin(s) channel region, which can improve electron and/or hole mobility in the channel.

Abstract: According to one embodiment, a pass gate provided between a data holding unit of an SRAM cell and a bit line, includes a first tunnel transistor and a first diode connected in series between the data holding unit and the bit line, and a second tunnel transistor and a second diode connected in series between the data holding unit and the bit line and connected in parallel to the first tunnel transistor and the first diode. Gate electrodes of the first tunnel transistor and the second tunnel transistor are connected to a word line. The first diode and the second diode have rectification in mutually opposite directions between the data holding unit and the bit line.

Abstract: Semiconductor devices and methods of fabricating semiconductor devices are provided. Two or more layers can be formed on a silicon substrate, wherein one or more of the layers are used for controlling an isolation recess. A first layer can comprise a first material and a second layer can comprise a second material.

Abstract: Structures and methods are presented relating to formation of finFET semiconducting devices. A finFET device is presented comprising fin(s) formed on a substrate, wherein the fin(s) has a needle-shaped profile. The needle-shaped profile, in conjunction with at least a buffer layer or a doped layer, epitaxially formed on the fin(s), facilitates strain to be induced into the fin(s) by the buffer layer or the doped layer. The fin(s) can comprise silicon aligned on a first plane, while at least one of the buffer layer or the doped layer are grown on a second plane, the alignment of the first and second planes are disparate and are selected such that formation of the buffer layer or the doped layer generates a stress in the fin(s). The generated stress results in a strain being induced into the fin(s) channel region, which can improve electron and/or hole mobility in the channel.

Abstract: In one embodiment, a semiconductor device includes a substrate, a gate insulator on the substrate, and a gate electrode on the gate insulator. The device further includes a source diffusion layer of a first conductivity type and a drain diffusion layer of a second conductivity type disposed on a surface of the substrate so as to sandwich the gate electrode. The device further includes a junction forming region disposed between the source diffusion layer and the drain diffusion layer so as to contact the source diffusion layer. The junction forming region includes a source extension layer of the first conductivity type, a pocket layer of the second conductivity type above the source extension layer, and a diffusion suppressing layer disposed between the source extension layer and the pocket layer and containing carbon so as to suppress diffusion of impurities between the source extension layer and the pocket layer.

Abstract: Structures and methods are presented relating to formation of finFET semiconducting devices. An approach is presented to facilitate formation of a pMOS finFET which can be combined with a nMOS finFET to form a balanced CMOS device. A Si:C layer can be utilized to suppress diffusion of group III and group V impurities, where suppression can utilize interstitial and substitutional phases. A Si:Ge layer can be utilized to facilitate determination of transition between a Si layer and a Si:C layer to enable a finFET to be formed having a required volume of fin material exposed for anticipated operation (e.g., a target Vth) of the finFET device.

Abstract: Semiconductor devices and methods of making semiconductor devices are provided. Boron diffusion into source/drain regions is restricted by a vertical and lateral confinement area formed on the surfaces of the source/drain regions. In an aspect, a silicon-carbon layer formed on the surface of the channel region suppresses boron diffusion toward a first source/drain region and toward at least a second source/drain region.

Abstract: Methods and structure are provided to facilitate isolation of respective ground plane regions in an SOTB semiconductor device. In one aspect a shallow STI trench can be combined with Si:C or Si:C/SiGe layers to confine n-type and p-type regions. In a further aspect, Ge can be implanted at the bottom of a shallow STI trench and subsequently oxidized to form SiGe oxide thereby extending the effective isolation provided by the shallow STI trench. In an aspect, a shallow STI trench can be extended to expose an underlying layer of SiGe, wherein the SiGe is subsequently oxidized to extending the effective isolation provide by the shallow STI trench. Such aspects enable a shallow STI trench to be seamlessly filled while having an extended region of isolation.

Abstract: A semiconductor device according to one embodiment includes: a semiconductor layer formed on a semiconductor substrate; a gate electrode formed on the semiconductor layer via a gate insulating film; an impurity diffusion suppression layer formed between the semiconductor substrate and the semiconductor layer and including a C-containing Si-based crystal containing a first impurity, the C-containing Si-based crystal being configured to suppress diffusion of a second impurity having a p-type conductivity type, and the C-containing Si-based crystal with the first impurity having a function of suppressing generation of fixed charge in the C-containing Si-based crystal; and p-type source/drain regions formed in the semiconductor substrate, the impurity diffusion suppression layer and the semiconductor layer in sides of the gate electrode, the p-type source/drain region having an extension region in the semiconductor layer and containing the second impurity.

Abstract: A semiconductor device according to one embodiment includes: a gate electrode formed on a semiconductor substrate via a gate insulating film; Si:C layers formed on the semiconductor substrate in sides of the gate electrode; p-type source/drain regions formed in sides of the gate electrode in the semiconductor substrate, and a part of the p-type source/drain regions being formed in the Si:C layers; and silicide layers formed on the Si:C layers.

Abstract: A semiconductor device is disclosed, which comprises a gate electrode having a laminated structure of a polycrystalline silicon film or a polycrystalline germanium film containing arsenic and a first nickel silicide layer formed in sequence on an element forming region of a semiconductor substrate through a gate insulating film, a sidewall insulating film formed on a side surface of the gate electrode, source/drain layers containing arsenic formed in the element forming region at both side portions of the gate electrode, and second nickel silicide layers formed on the source/drain layers, wherein a peak concentration of arsenic contained in the gate electrode is at least 1/10 of a peak concentration of arsenic contained in the source/drain layers.

Abstract: A semiconductor device according to one embodiment includes: a semiconductor substrate; a first impurity diffusion suppression layer formed on the semiconductor substrate for suppressing diffusion of a channel impurity; an impurity channel layer formed on the first impurity diffusion suppression layer and containing the channel impurity; a second impurity diffusion suppression layer formed on the impurity channel layer for suppressing diffusion of the channel impurity; a channel layer formed on the second impurity diffusion suppression layer; a gate insulating film formed on the channel layer; and a gate electrode formed on the gate insulating film.

Abstract: According to one embodiment, a semiconductor device contains a gate electrode, SiGe layers, Si layers, source/drain regions, and silicide layers. The gate electrode is formed on a semiconductor substrate via a gate insulating film. The SiGe layers are formed on both sides of the gate electrode on the semiconductor substrate. Over half of a region of the SiGe layers is higher than an interface between the semiconductor substrate and the gate insulating film. The Si layers are formed on the SiGe layers. The source/drain regions are formed on both sides of the gate electrode in the Si layers, the SiGe layers and the semiconductor substrate. The silicide layers are formed on the Si layers.

Abstract: A semiconductor device includes a semiconductor substrate; a first impurity diffusion suppression layer and a thicker second impurity diffusion suppression layer formed on the semiconductor substrate in first and second isolated transistor regions; first and second crystal layers formed on the first and second impurity diffusion suppression layers; first and second gate electrodes formed on the first and second crystal layers; first and second p-type channel regions formed in the semiconductor substrate, the first impurity diffusion suppression layer and respective of the first and second crystal layers below the first and second gate electrodes; and first and second source/drain regions formed on both sides of the first and second channel region; wherein the first and second p-type channels have lower impurity concentrations in respective of the first and second crystal layers than in the semiconductor substrate.

Abstract: A semiconductor device according to one embodiment includes: a gate electrode formed on a semiconductor substrate via a gate insulating film; Si:C layers formed on the semiconductor substrate in sides of the gate electrode; p-type source/drain regions formed in sides of the gate electrode in the semiconductor substrate, and a part of the p-type source/drain regions being formed in the Si:C layers; and silicide layers formed on the Si:C layers.