Patents by Inventor Akira Hokazono

Akira Hokazono has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6573583
    Abstract: Provided is a semiconductor device, comprising a gate electrode formed on a semiconductor substrate, source/drain diffusion layers formed on both sides of the gate electrode, a gate electrode side-wall on the side of the source/drain diffusion layer and a gate side-wall insulating film covering a part of the upper surface of the semiconductor substrate in the vicinity of the gate electrode and having an L-shaped/reversed L-shaped cross-sectional shape, and a semiconductor layer extending over the gate side-wall insulating film covering a part of the upper surface of the semiconductor substrate in the vicinity of the gate electrode.
    Type: Grant
    Filed: December 19, 2001
    Date of Patent: June 3, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Akira Hokazono
  • Patent number: 6545317
    Abstract: A gate electrode is provided via a gate insulating film formed between the source and drain regions on a semiconductor substrate, wherein the sidewall of the gate electrode excluding the exposed part formed at the upper part thereof facing the source and drain regions is covered with a sidewall insulating film, and an epitaxial film is formed on the exposed part of the sidewall of the gate electrode but not formed on a top surface of the gate electrode. An element isolation region formed on the semiconductor substrate is composed of a first insulating film formed in the semiconductor substrate and a second insulating film which is formed inside the first insulating film and has a lower epitaxial growth rate than that of the first insulating film, and the surface of the source and drain regions is covered with a silicon layer, part of which runs onto the surface of the first insulating film.
    Type: Grant
    Filed: June 28, 2001
    Date of Patent: April 8, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Hokazono, Mariko Takayanagi
  • Patent number: 6436776
    Abstract: A shallow impurity diffusion layer adjacent to a gate electrode is formed by forming a side-wall insulating film of the gate electrode twice, and a MOS transistor of the salicide type having improved short-channel effect is embodied. An impurity diffusion layer portion not adjacent to a gate electrode of a source/drain region is formed first by self-alignment with a first side-wall insulating film. After an impurity diffusion layer adjacent to the gate electrode is formed by self-alignment with the gate electrode, a second side-wall insulating film is formed. Silicide films are formed on the gate electrode and source/drain region by self-alignment with the second side-wall insulating film.
    Type: Grant
    Filed: March 30, 2001
    Date of Patent: August 20, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeo Nakayama, Akira Hokazono
  • Publication number: 20020079551
    Abstract: Provided is a semiconductor device, comprising a gate electrode formed on a semiconductor substrate, source/drain diffusion layers formed on both sides of the gate electrode, a gate electrode side-wall on the side of the source/drain diffusion layer and a gate side-wall insulating film covering a part of the upper surface of the semiconductor substrate in the vicinity of the gate electrode and having an L-shaped/reversed L-shaped cross-sectional shape, and a semiconductor layer extending over the gate side-wall insulating film covering a part of the upper surface of the semiconductor substrate in the vicinity of the gate electrode.
    Type: Application
    Filed: December 19, 2001
    Publication date: June 27, 2002
    Inventor: Akira Hokazono
  • Publication number: 20020000611
    Abstract: A gate electrode is provided via a gate insulating film formed between the source and drain regions on a semiconductor substrate, wherein the sidewall of the gate electrode excluding the exposed part formed at the upper part thereof facing the source and drain regions is covered with a sidewall insulating film, and an epitaxial film is formed on the exposed part of the sidewall of the gate electrode but not formed on a top surface of the gate electrode. An element isolation region formed on the semiconductor substrate is composed of a first insulating film formed in the semiconductor substrate and a second insulating film which is formed inside the first insulating film and has a lower epitaxial growth rate than that of the first insulating film, and the surface of the source and drain regions is covered with a silicon layer, part of which runs onto the surface of the first insulating film.
    Type: Application
    Filed: June 28, 2001
    Publication date: January 3, 2002
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Akira Hokazono, Mariko Takayanagi
  • Publication number: 20010034085
    Abstract: A shallow impurity diffusion layer adjacent to a gate electrode is formed by forming a side-wall insulating film of the gate electrode twice, and a MOS transistor of the salicide type having improved short-channel effect is embodied. An impurity diffusion layer portion not adjacent to a gate electrode of a source/drain region is formed first by self-alignment with a first side-wall insulating film. After an impurity diffusion layer adjacent to the gate electrode is formed by self-alignment with the gate electrode, a second side-wall insulating film is formed. Silicide films are formed on the gate electrode and source/drain region by self-alignment with the second side-wall insulating film.
    Type: Application
    Filed: March 30, 2001
    Publication date: October 25, 2001
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takeo Nakayama, Akira Hokazono
  • Patent number: 6025211
    Abstract: On the surface of a hydrogen-terminated diamond 1 formed by terminating a surface 2 of either a homoepitaxial diamond or a heteroepitaxial diamond or a surface-flattened polycrystal diamond are formed a drain-ohmic contact 4 and a source-ohmic contact 3 of gold or platinum, an insulating layer 5 formed of silicon oxide (SiO.sub.x : 1.ltoreq.X.ltoreq.2) and a gate electrode 6 mounted on said insulating layer, and the surface other than the element forming region is set to be an insulating region being non-hydrogen-terminated, for example, oxygen-terminated, and the elements formed on said region is being isolated.
    Type: Grant
    Filed: September 22, 1998
    Date of Patent: February 15, 2000
    Assignee: Tokyo Gas Co., Ltd.
    Inventors: Takefumi Ishikura, Satoshi Yamashita, Hiroshi Kawarada, Akira Hokazono
  • Patent number: 5854496
    Abstract: On the surface of a hydrogen-terminated diamond 1 formed by terminating a surface 2 of either a homoepitaxial diamond or a heteroepitaxial diamond or a surface-flattened polycrystal diamond are formed a drain-ohmic contact 4 and a source-ohmic contact 3 of gold or platinum, an insulating layer 5 formed of silicon oxide (SiO.sub.x : 1.ltoreq.X.ltoreq.2) and a gate electrode 6 mounted on said insulating layer, and the surface other than the element forming region is set to be an insulating region being non-hydrogen-terminated, for example, oxygen-terminated, and the elements formed on said region is being isolated.
    Type: Grant
    Filed: August 29, 1997
    Date of Patent: December 29, 1998
    Assignee: Tokyo Gas Co., Ltd.
    Inventors: Takefumi Ishikura, Satoshi Yamashita, Hiroshi Kawarada, Akira Hokazono