Abstract: A semiconductor device according to one embodiment includes: adjacent first and second transistors each formed on a semiconductor substrate, the first and second transistors respectively having first and second gate electrodes and sharing a source/drain region therebetween; a first insulating film formed on the first gate electrode; a second insulating film formed on the second gate electrode and comprising a region thicker than the first insulating film; and a self-aligned contact plug connected to the source/drain region, a horizontal distance from a center position of the self-aligned contact plug to the second gate electrode being less than a horizontal distance from a center position between the first and second gate electrodes to the second gate electrode.

Abstract: A semiconductor device is disclosed, which comprises a gate electrode having a laminated structure of a polycrystalline silicon film or a polycrystalline germanium film containing arsenic and a first nickel silicide layer formed in sequence on an element forming region of a semiconductor substrate through a gate insulating film, a sidewall insulating film formed on a side surface of the gate electrode, source/drain layers containing arsenic formed in the element forming region at both side portions of the gate electrode, and second nickel silicide layers formed on the source/drain layers, wherein a peak concentration of arsenic contained in the gate electrode is at least 1/10 of a peak concentration of arsenic contained in the source/drain layers.

Abstract: A semiconductor device according to one embodiment includes: a semiconductor layer formed on a semiconductor substrate; a gate electrode formed on the semiconductor layer via a gate insulating film; an impurity diffusion suppression layer formed between the semiconductor substrate and the semiconductor layer and including a C-containing Si-based crystal containing a first impurity, the C-containing Si-based crystal being configured to suppress diffusion of a second impurity having a p-type conductivity type, and the C-containing Si-based crystal with the first impurity having a function of suppressing generation of fixed charge in the C-containing Si-based crystal; and p-type source/drain regions formed in the semiconductor substrate, the impurity diffusion suppression layer and the semiconductor layer in sides of the gate electrode, the p-type source/drain region having an extension region in the semiconductor layer and containing the second impurity.

Abstract: In one aspect of the present invention, a semiconductor device may include a Si substrate, a gate electrode provided on the semiconductor via a gate dielectric layer, a first epitaxially grown layer provided on the Si substrate, a channel region provided in the Si substrate below the gate electrode, a source/drain region provided in the first epitaxially grown layer sandwiching the channel region, and having a first conductivity type impurity, a second epitaxially grown layer provided between the channel region and the first epitaxially grown layer, and provided below the gate electrode, and having a second conductivity type impurity opposite to the first conductivity type.

Abstract: A semiconductor device is disclosed, which comprises a gate electrode having a laminated structure of a polycrystalline silicon film or a polycrystalline germanium film containing arsenic and a first nickel silicide layer formed in sequence on an element forming region of a semiconductor substrate through a gate insulating film, a sidewall insulating film formed on a side surface of the gate electrode, source/drain layers containing arsenic formed in the element forming region at both side portions of the gate electrode, and second nickel silicide layers formed on the source/drain layers, wherein a peak concentration of arsenic contained in the gate electrode is at least 1/10 of a peak concentration of arsenic contained in the source/drain layers.

Abstract: A semiconductor device according to one embodiment includes: a semiconductor substrate comprising first and second transistor regions that are isolated by an element isolation region; a first impurity diffusion suppression layer formed on the semiconductor substrate in the first transistor region; a second impurity diffusion suppression layer formed on the semiconductor substrate in the second transistor region, and having a thickness larger than that of the first impurity diffusion suppression layer; a first crystal layer formed on the first impurity diffusion suppression layer; a second crystal layer formed on the second impurity diffusion suppression layer; a first gate electrode formed on the first crystal layer via a first gate insulating film; a second gate electrode formed on the second crystal layer via a second gate insulating film; a first channel region formed in a region in the semiconductor substrate, the first impurity diffusion suppression layer and the first crystal layer below the first gate

Abstract: A semiconductor device according to one embodiment includes: a semiconductor substrate; a gate electrode formed on the semiconductor substrate via a gate insulating film; a first silicide layer formed on the gate electrode; a channel region formed in the semiconductor substrate below the gate electrode; source/drain regions formed in regions in the semiconductor substrate, the regions sandwiching the channel region; and second silicide layers formed on the source/drain regions and having an average grain size smaller than that of the first silicide layer or an average number of compositional boundaries in a crystal grain larger than that of the first silicide layer.

Abstract: A semiconductor device according to one embodiment includes: a semiconductor substrate; a first impurity diffusion suppression layer formed on the semiconductor substrate for suppressing diffusion of a channel impurity; an impurity channel layer formed on the first impurity diffusion suppression layer and containing the channel impurity; a second impurity diffusion suppression layer formed on the impurity channel layer for suppressing diffusion of the channel impurity; a channel layer formed on the second impurity diffusion suppression layer; a gate insulating film formed on the channel layer; and a gate electrode formed on the gate insulating film.

Abstract: In one aspect of the present invention, a semiconductor device may include a plurality of fins disposed substantially parallel to each other at predetermined intervals on a semiconductor substrate, a gate electrode formed to partially sandwich therein the both side surfaces, in the longitudinal direction, of each of the plurality of fins with an insulating film interposed between the gate electrode and each of the side surfaces of each fin, and a semiconductor layer formed on each of at least some of side surfaces of the plurality of fins, wherein the semiconductor layer in a region located on an outer side surface, in the longitudinal direction, of each of two fins which are located at both ends of the line of the plurality of fins is thinner than the semiconductor layer in a region located on each of side surfaces, in the longitudinal direction and other than the outer surfaces of the two fins, of the plurality of fins.

Abstract: A semiconductor device comprising: a semiconductor substrate; an n-type MIS transistor which is formed on the semiconductor substrate and has a first metal gate electrode and a first polycrystalline silicon layer formed on the first metal gate electrode; a p-type MIS transistor which is formed on the semiconductor substrate and has a second metal gate electrode and a second polycrystalline silicon layer, the second metal gate electrode containing at least one metallic element different from that of the first metal gate electrode, and the second polycrystalline silicon layer being formed on the second metal gate electrode and having the same conductivity type as that of the first polycrystalline silicon layer.

Abstract: In one aspect of the present invention, a semiconductor device may include a plurality of fins disposed substantially parallel to each other at predetermined intervals on a semiconductor substrate, a gate electrode formed to partially sandwich therein the both side surfaces, in the longitudinal direction, of each of the plurality of fins with an insulating film interposed between the gate electrode and each of the side surfaces of each fin, and a semiconductor layer formed on each of at least some of side surfaces of the plurality of fins, wherein the semiconductor layer in a region located on an outer side surface, in the longitudinal direction, of each of two fins which are located at both ends of the line of the plurality of fins is thinner than the semiconductor layer in a region located on each of side surfaces, in the longitudinal direction and other than the outer surfaces of the two fins, of the plurality of fins.

Abstract: In one aspect of the present invention, a semiconductor device may include a Si substrate, a gate electrode provided on the semiconductor via a gate dielectric layer, a first epitaxially grown layer provided on the Si substrate, a channel region provided in the Si substrate below the gate electrode, a source/drain region provided in the first epitaxially grown layer sandwiching the channel region, and having a first conductivity type impurity, a second epitaxially grown layer provided between the channel region and the first epitaxially grown layer, and provided below the gate electrode, and having a second conductivity type impurity opposite to the first conductivity type.

Abstract: A semiconductor device according to an embodiment of the present invention comprises a first transistor including: a first source layer and a first drain layer both formed in one surface of a semiconductor substrate; a first silicide layer formed on the first source layer and the first drain layer; a first gate electrode formed on a first gate insulating film formed on the surface of the semiconductor substrate and having a second silicide layer; and a silicon nitride film formed on the sidewall of the first gate electrode; a second transistor including: a second source layer and a second drain layer both formed in the surface of the semiconductor substrate; a third silicide layer formed on the second source layer and the second drain layer and equal in thickness to the first silicide layer; a second gate electrode formed on a second gate insulating film formed on the surface of the semiconductor substrate and having a fourth silicide layer thinner in thickness than the second silicide layer.

Abstract: A semiconductor device includes an n-channel MIS transistor and a p-channel MIS transistor. The n-channel MIS transistor includes a first source region formed in a semiconductor region on a substrate, a first drain region formed in the semiconductor region apart from the first source region, a first gate insulating film, and a first gate electrode formed on the first gate insulating film. The p-channel MIS transistor includes a second source region formed in the semiconductor region, a second drain region formed in the semiconductor region apart from the second source region, a second gate insulating film, and a second gate electrode formed on the second gate insulating film. The first and second drain regions are arranged to be connected to each other and made of the same material, and one of the first and second source regions is made of a material different from the first and second drain regions.

Abstract: A semiconductor device includes a p-type well region, n+-type diffusion regions formed in the surface region of the p-type well region, a gate electrode containing silicon and formed above the p-type well region with a gate insulating film disposed therebetween, and NiSi films formed in the surface regions of the n+-type diffusion regions. In the semiconductor device, p-type impurity is doped in the depth direction from the surface of the NiSi film and the impurity profile of p-type impurity is so formed that a peak concentration of not lower than 1E20 cm?3 will be provided in a preset depth position of the NiSi film and the concentration in the interface between the NiSi film and the n+-type diffusion region and the concentration in a position deeper than the interface will not be higher than 5E19 cm?3.

Abstract: A semiconductor layer in which a primary part of a FinFET is formed, i.e., a fin has a shape which is long in a direction x and short in a direction y. A width of the fin in the direction y changes on three stages. First, in a channel area between gate electrodes each having a gate length Lg, the width of the fin in the direction y is Wch. Further, the width of the fin in the direction y in a source/drain extension area adjacent to the channel area in the direction x is Wext (>Wch). Furthermore, the width of the fin in the direction y in a source/drain area adjacent to the source/drain extension area in the direction x is Wsd (>Wext).

Abstract: A semiconductor device is disclosed, which comprises a gate electrode having a laminated structure of a polycrystalline silicon film or a polycrystalline germanium film containing arsenic and a first nickel silicide layer formed in sequence on an element forming region of a semiconductor substrate through a gate insulating film, a sidewall insulating film formed on a side surface of the gate electrode, source/drain layers containing arsenic formed in the element forming region at both side portions of the gate electrode, and second nickel silicide layers formed on the source/drain layers, wherein a peak concentration of arsenic contained in the gate electrode is at least 1/10 of a peak concentration of arsenic contained in the source/drain layers.

Abstract: A semiconductor layer in which a primary part of a FinFET is formed, i.e., a fin has a shape which is long in a direction x and short in a direction y. A width of the fin in the direction y changes on three stages. First, in a channel area between gate electrodes each having a gate length Lg, the width of the fin in the direction y is Wch. Further, the width of the fin in the direction y in a source/drain extension area adjacent to the channel area in the direction x is Wext (>Wch). Furthermore, the width of the fin in the direction y in a source/drain area adjacent to the source/drain extension area in the direction x is Wsd (>Wext).

Abstract: A semiconductor device has a first and a second semiconductor layer provided on an insulating film on a support substrate. A first memory cell transistor, which constitutes a part of a memory cell in an SRAM, has a first gate electrode of a first conductivity type and first source/drain diffusion layers of a second conductivity type opposite to the first conductivity type. The following expression is fulfilled the thickness of the first conductivity type?one-third of a length of the first gate electrode in its channel length. A first peripheral transistor, which constitutes a part of a peripheral circuit, has a third gate electrode and a third source/drain diffusion layers. The following expression is satisfied the thickness of the second semiconductor layer>one-third of a length of the third gate electrode in its channel length direction.

Abstract: A semiconductor device having active regions connected by an interconnect line, which includes first and second transistors each having active regions and formed spaced apart from each other in a semiconductor substrate, an isolation region for isolating the first and second transistors from each other, a slit formed in the isolation region to allow those paired active regions of the first and second transistors which are opposed to each other with the isolation region interposed therebetween to communicate with each other through it, a conductive film formed on the inner walls of the slit, and an interconnect layer having first and second portions, each of which is electrically connected with a corresponding one of the paired active regions, and a third portion which is formed along the slit on the isolation region to connect the first and second portions with each other.