Patents by Inventor Akira Morita

Akira Morita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100194734
    Abstract: An integrated circuit device includes: a data line driving circuit that is provided for each of a plurality of data signal supply lines and supplies a multiplexed data signal to a corresponding data signal supply line among the plurality of data signal supply lines; a pattern output circuit; and an order setting circuit, wherein a plurality of data signals after demultiplexing obtained by demultiplexing the multiplexed data signal by a demultiplexer are supplied to a plurality of pixels in one horizontal scanning period, the pattern output circuit outputs, as an output rotation pattern, at each frame or each set of plural frames, one of first rotation pattern—M-th (M is a natural number of 2 or more) rotation pattern, which are rotation patterns each defining an order of driving first pixel—p-th (p is a natural number of 2 or more) pixel among the plurality of pixels.
    Type: Application
    Filed: January 29, 2010
    Publication date: August 5, 2010
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Akira MORITA
  • Publication number: 20100194718
    Abstract: An integrated circuit device includes: a data line driving circuit provided for each of a plurality of data signal supply lines that supplies a multiplexed data signal to a corresponding data signal supply line; an order offset register that stores a first order offset setting value; an order setting circuit that sets the order of driving the first pixel; and an order offset addition circuit corresponding to the data line driving circuit. When the data line driving circuit drives the q-th (q is a natural number less than p) pixel in the r-th (r is a natural number less than p) place in the order, the order offset addition circuit processes addition of an order offset correction value based on the r-th order offset setting value among the first order offset setting value.
    Type: Application
    Filed: January 29, 2010
    Publication date: August 5, 2010
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Akira MORITA
  • Patent number: 7758717
    Abstract: On a hot plate, jigs and wafers are joined by bonding wax. A first transport mechanism, a posture change mechanism, a pusher and a second transport mechanism transport the jigs joined with the wafers from the hot plate to a treating transport mechanism. The treating transport mechanism immerses the jigs joined with the wafers in a treating solution stored in a treating tank. Thus, the wafers may be thinned, or otherwise treated, without a turn table directly contacting and damaging the wafers as in the prior art.
    Type: Grant
    Filed: February 27, 2006
    Date of Patent: July 20, 2010
    Assignee: Dainippon Screen Mfg. Co., Ltd.
    Inventors: Koji Hasegawa, Akira Morita, Kenichiro Arai
  • Patent number: 7746336
    Abstract: A power supply circuit for supplying a voltage to a counter electrode which faces a pixel electrode in an electro-optic device, an electro-optic material being disposed between the counter electrode and the pixel electrode, includes: an operational amplifier which drives the counter electrode; and an operational amplifier control circuit which controls at least one of a slew rate and an electric current drive capacity of the operational amplifier. The operational amplifier control circuit increases at least one of the slew rate and the electric current drive capacity of the operational amplifier, during a control time starting at a start timing of a write-in to the pixel electrode, and brings the slew rate and the electric current drive capacity of the operational amplifier back to the state prior to the control time after passing the control time.
    Type: Grant
    Filed: October 3, 2005
    Date of Patent: June 29, 2010
    Assignee: Seiko Epson Corporation
    Inventor: Akira Morita
  • Patent number: 7741871
    Abstract: An integrated circuit device includes a high-speed serial interface circuit that includes a receiver circuit that receives differential signals through a serial bus, first and second guard terminals that prevent radiation, first and second terminals that are disposed between the first and second guard terminals and receive the differential signals, a first power supply terminal to which a high-voltage-side power supply voltage for the receiver circuit is supplied, and a second power supply terminal to which a low-voltage-side power supply voltage is supplied. A first switch element is provided between a line from the first guard terminal and a line from the second power supply terminal, and a second switch element is provided between a line from the second guard terminal and a line from the second power supply terminal. The first and second switch elements are turned ON in a high-speed serial interface mode.
    Type: Grant
    Filed: March 16, 2009
    Date of Patent: June 22, 2010
    Assignee: Seiko Epson Corporation
    Inventor: Akira Morita
  • Patent number: 7733160
    Abstract: A power supply circuit includes a voltage booster circuit that generates a boosted voltage by boosting a second voltage with respect to a first voltage, and a limiter circuit that limits a potential of the boosted voltage. The limiter circuit discharges a charge to or charges a charge from a power supply line so that the boosted voltage becomes a given target voltage, the second voltage being supplied to the power supply line. The voltage booster circuit changes a boost capability corresponding to an output load of the power supply circuit.
    Type: Grant
    Filed: January 25, 2008
    Date of Patent: June 8, 2010
    Assignee: Seiko Epson Corporation
    Inventor: Akira Morita
  • Patent number: 7701425
    Abstract: A display driver including a shift register which shifts a shift start signal based on a shift clock to output a shift output from flip-flops thereof; a shift register control circuit which controls the shift register; a data latch which fetches display data on a display data bus, based on the shift output of the shift register; and a drive circuit which drives data lines based on the display data that has been fetched into the data latch. The shift register control circuit supplies the shift clock to the shift register in a vertical scan period, to cause the shift register to fetch display data for one horizontal scan, then halts the supply of the shift clock, and also supplies the shift clock to the shift register in a vertical blanking period, to clear the contents held in the shift register.
    Type: Grant
    Filed: July 9, 2004
    Date of Patent: April 20, 2010
    Assignee: Seiko Epson Corporation
    Inventors: Akira Morita, Yuichi Toriumi
  • Patent number: 7692615
    Abstract: A display driver which drives a data line connected to a pixel electrode through a switching element, the pixel electrode facing a common electrode with an electro-optical substance interposed, and a voltage being supplied to the common electrode based on a polarity reversal signal. The display driver includes: a polarity reversal signal generation circuit which generates the polarity reversal signal which specifies the timing at which the polarity of a voltage applied to the electro-optical substance is reversed; and a driver section which supplies a drive voltage based on display data to the data line so that the polarity of the voltage applied to the electro-optical substance is reversed in synchronization with the polarity reversal signal.
    Type: Grant
    Filed: August 30, 2004
    Date of Patent: April 6, 2010
    Assignee: Seiko Epson Corporation
    Inventor: Akira Morita
  • Publication number: 20100053145
    Abstract: An integrated circuit device includes: a plurality of data line driving circuits that drive a plurality of data voltage supply lines; and a correction data calculation section that calculates correction data for correcting differences in data voltages outputted from the plurality of data line driving circuits, wherein the correction data calculation section executes, in one horizontal scanning period in a non-display period in a vertical scanning period, a first mode to obtain the correction data corresponding to a data line driving circuit to be corrected among the plurality of data line driving circuits.
    Type: Application
    Filed: August 27, 2009
    Publication date: March 4, 2010
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Akira MORITA
  • Publication number: 20100053129
    Abstract: An integrated circuit device includes: a plurality of data line driving circuits that drive a plurality of data voltage supply lines; a comparator that compares a data voltage corresponding to a data line driving circuit to be corrected among the plurality of data line driving circuits with a comparator reference voltage; a correction data calculation section that calculates correction data for correcting a difference in the data voltage based on a comparison result given from the comparator; and a plurality of correction circuits that each correct image data based on the correction data given from the correction data calculation section, and output the image data after correction processing to a corresponding data line driving circuit among the plurality of data line driving circuits.
    Type: Application
    Filed: August 27, 2009
    Publication date: March 4, 2010
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Akira MORITA
  • Patent number: 7671853
    Abstract: A signal output adjustment circuit includes a decoder which decodes command data from a memory, a control register in which control data corresponding to first command data is set when the decoder determines that the command data is the first command data, a buffer in which the control data corresponding to second command data is stored when the decoder determines that the command data is the second command data, and an output adjustment circuit which reads the control data stored in the buffer and outputs the control data in synchronization with a data fetch signal, based on a value set in the control register. At least one of permission/rejection of inversion output of the data fetch signal and output timing of the data fetch signal is set based on the value set in the control register.
    Type: Grant
    Filed: August 6, 2004
    Date of Patent: March 2, 2010
    Assignee: Seiko Epson Corporation
    Inventor: Akira Morita
  • Patent number: 7663619
    Abstract: A power supply circuit including: a high-potential-side voltage generation circuit which generates a high-potential-side voltage to be supplied to the common electrode; a low-potential-side voltage generation circuit which generates a low-potential-side voltage to be supplied to the common electrode; and a switch circuit which alternately supplies the high-potential-side voltage and the low-potential-side voltage to the common electrode as a common electrode voltage.
    Type: Grant
    Filed: December 19, 2005
    Date of Patent: February 16, 2010
    Assignee: Seiko Epson Corporation
    Inventor: Akira Morita
  • Patent number: 7663586
    Abstract: A reference voltage generation circuit, including: first to Jth (J is an integer greater than one) gamma correction data registers in which gamma correction data for generating a plurality of reference voltages is set; and a reference voltage select circuit which selects K select voltages from first to Lth (L is an integer greater than two, and K is a natural number smaller than L) select voltages arranged in potential descending order or potential ascending order and outputs the K select voltages as first to Kth reference voltages in potential descending order or potential ascending order, based on the gamma correction data set in one of the first to Jth gamma correction data registers, wherein the first to Kth reference voltages are output as the reference voltages.
    Type: Grant
    Filed: March 1, 2006
    Date of Patent: February 16, 2010
    Assignee: Seiko Epson Corporation
    Inventor: Akira Morita
  • Publication number: 20100021817
    Abstract: An electrode structure for a lithium secondary battery including: a main active material layer including a metal powder selected from silicon, tin and an alloy thereof that can store and discharge of lithium by electrochemical reaction, and a binder of an organic polymer; and a wherein the collector. The main active material layer includes a powder of a support material for supporting the electron conduction of the main active material layer in addition to the metal powder and the powder of the support material are particles having a spherical, pseudo-spherical or pillar shape with an average particle size of 0.3 to 1.35 times the thickness of the main active material layer. The support material is one or more selected from graphite, oxides of transition metals and metals that do not electrochemically form alloy with lithium. Organic polymer compounded with a conductive polymer is used for the binder.
    Type: Application
    Filed: October 2, 2009
    Publication date: January 28, 2010
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Soichiro Kawakami, Akira Morita, Takao Ogura
  • Patent number: 7633478
    Abstract: A power supply circuit including a high-potential-side voltage generation circuit and a low-potential-side voltage generation circuit which respectively generate a high-potential-side voltage and a low-potential-side voltage to be supplied to a common electrode, and alternately supplying the high-potential-side voltage and the low-potential-side voltage to the common electrode as a common electrode voltage so that polarity of the common electrode voltage is the same in consecutive first and second horizontal scan periods. When a precharge voltage of data lines in a precharge period in the first horizontal scan period is higher than the average voltage of the data lines set after the precharge period, the power supply circuit controls the supply capability of the common electrode voltage in a precharge period of the data lines in the second horizontal scan period.
    Type: Grant
    Filed: January 18, 2006
    Date of Patent: December 15, 2009
    Assignee: Seiko Epson Corporation
    Inventor: Akira Morita
  • Patent number: 7615314
    Abstract: An electrode structure for a lithium secondary battery including: a main active material layer including a metal powder selected from silicon, tin and an alloy thereof that can store and discharge lithium by electrochemical reaction, and a binder of an organic polymer; and a current collector. The main active material layer includes a powder of a support material for supporting the electron conduction of the main active material layer in addition to the metal powder and the powder of the support material are particles having a spherical, pseudo-spherical or pillar shape with an average particle size of 0.3 to 1.35 times the thickness of the main active material layer. The support material is one or more selected from graphite, oxides of transition metals and metals that do not electrochemically form alloy with lithium. Organic polymer compounded with a conductive polymer is used for the binder.
    Type: Grant
    Filed: December 8, 2005
    Date of Patent: November 10, 2009
    Assignee: Canon Kabushiki Kaisha
    Inventors: Soichiro Kawakami, Akira Morita, Takao Ogura
  • Patent number: 7609256
    Abstract: A power supply circuit including: a high-potential-side voltage generation circuit which generates a high-potential-side voltage; a low-potential-side voltage generation circuit which generates a low-potential-side voltage; and a switch circuit which alternately supplies the high-potential-side voltage and the low-potential-side voltage to the common electrode as a common electrode voltage. The power supply circuit performs supply capability control of the common electrode voltage which changes at least one of current drive capability of the high-potential-side voltage generation circuit, an output voltage level of the high-potential-side voltage generation circuit, current drive capability of the low-potential-side voltage generation circuit, and an output voltage level of the low-potential-side voltage generation circuit according to a total value generated based on grayscale data for the number of dots of one scan line.
    Type: Grant
    Filed: December 20, 2005
    Date of Patent: October 27, 2009
    Assignee: Seiko Epson Corporation
    Inventor: Akira Morita
  • Publication number: 20090244036
    Abstract: An integrated circuit device includes: a high-speed serial interface circuit including a receiver circuit that receives a differential signal through a serial bus; a first terminal into which a first signal included in the differential signal is inputted; a second terminal into which a second signal included in the differential signal is inputted; a receiver circuit power supply terminal to which a power supply voltage applied to a high-voltage side of the receiver circuit is supplied; a first terminating resistor provided between the first terminal and a first node; a second terminating resistor provided between the second terminal and a second node; and a switching element provided between the first and the second nodes. In the device, the switching element is turned on in a high-speed serial interface mode and is turned off in a parallel interface mode by using the power supply from the receiver circuit power supply terminal.
    Type: Application
    Filed: March 12, 2009
    Publication date: October 1, 2009
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Akira MORITA
  • Publication number: 20090237174
    Abstract: An integrated circuit device includes a high-speed serial interface circuit that includes a receiver circuit that receives differential signals through a serial bus, first and second guard terminals that prevent radiation, first and second terminals that are disposed between the first and second guard terminals and receive the differential signals, a first power supply terminal to which a high-voltage-side power supply voltage for the receiver circuit is supplied, and a second power supply terminal to which a low-voltage-side power supply voltage is supplied. A first switch element is provided between a line from the first guard terminal and a line from the second power supply terminal, and a second switch element is provided between a line from the second guard terminal and a line from the second power supply terminal. The first and second switch elements are turned ON in a high-speed serial interface mode.
    Type: Application
    Filed: March 16, 2009
    Publication date: September 24, 2009
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Akira MORITA
  • Publication number: 20090239118
    Abstract: A catalyst layer of a solid polymer fuel cell includes a catalyst structural body, a membrane present on at least part of a surface of the catalyst structural body and including a first water-repellent material having a functional group, particles having a second water-repellent material, and an electrolyte.
    Type: Application
    Filed: March 18, 2009
    Publication date: September 24, 2009
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Akira Morita, Yoshinobu Okumura