Patents by Inventor Akira Nagai

Akira Nagai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7193009
    Abstract: An electronic device for high frequency signals having a small dielectric loss and a high efficiency is provided, in which a low dielectric loss tangent resin composition is used, for coping with high frequency signals, as an insulating layer. The electronic device is fabricated using an insulating layer containing a crosslinked structure of a crosslinking ingredient represented by the following general formula (I): (where R represents a hydrocarbon skeleton, R1, which may be identical or different from each other, represents a hydrogen atom or a hydrocarbon group of 1 to 20 carbon atoms, R2, R3 and R4, which may be identical or different from each other, each represents a hydrogen atom or a hydrocarbon group of 1 to 6 carbon atoms, m is an integer of 1 to 4 and n is an integer of 2 or greater).
    Type: Grant
    Filed: May 9, 2003
    Date of Patent: March 20, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Satoru Amou, Akira Nagai, Shinji Yamada, Takao Ishikawa, Akio Takahashi
  • Patent number: 7112627
    Abstract: A curing low dielectric loss tangent film using a low dielectric loss tangent composition containing a polyfunctional styrene compound having excellent dielectric characteristics, and a wiring film using the same as an insulating layer are provided. The low dielectric loss tangent film contains a high molecular weight material and a crosslinking ingredient with a weight average molecular weight of 1000 or less having a plurality of styrene groups shown by the following general formula: (where R represents a hydrocarbon skeleton, R1, which may be identical or different with each other, represents a hydrogen atom or a hydrocarbon group of 1 to 20 carbon atoms, R2, R3 and R4, which may be identical or different with each other, each represents a hydrogen atom or an alkyl group of 1 to 6 carbon atoms, m represents an integer of 1 to 4, and n represents an integer of 2 or greater).
    Type: Grant
    Filed: March 12, 2003
    Date of Patent: September 26, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Satoru Amou, Shinji Yamada, Takao Ishikawa, Akira Nagai, Masatoshi Sugimasa
  • Publication number: 20060182941
    Abstract: There is provided a fiber-reinforced composite material containing fibers having an average fiber diameter of 4 to 200 nm and a matrix material, the composite material having a visible light transmittance of 60% or more at a wavelength of 400 to 700 nm, which is a conversion value based on a thickness of 50 ?m. A fiber-reinforced composite material composed of a matrix material and a fiber aggregate impregnated therewith is provided, in which when a segment length of a bright region corresponding to a pore region of the fiber aggregate is represented by L, which is obtained by statistical analysis of a unidirectional run-length image formed from a binary image obtained by binarization of a scanning electron microscopic image of the fiber aggregate, the total length of segments that satisfy L?4.5 ?m is 30% or less of the total analyzed length.
    Type: Application
    Filed: January 18, 2006
    Publication date: August 17, 2006
    Applicants: PIONEER CORPORATION, HITACHI, LTD., ROHM CO., LTD., KYOTO UNIVERSITY, MITSUBISHI CHEMICAL CORPORATION
    Inventors: Hiroyuki Yano, Junji Sugiyama, Masaya Nogi, Shin-ichiro Iwamoto, Keishin Handa, Akira Nagai, Takao Miwa, Yoshitaka Takezawa, Toshiyuki Miyadera, Takashi Kurihara, Tohru Matsuura, Nobutatsu Koshoubu, Tohru Maruno
  • Patent number: 7091620
    Abstract: A semiconductor device includes a semiconductor chip formed with connection terminals, an elastic structure interposed between a main surface of the chip and a wiring substrate formed with wirings connected at first ends thereof to the connection terminals, and bump electrodes connected to the other ends of the wirings. The connection terminals may be at a center part or in peripheral part(s) of the chip main surface and both the elastic structure and wiring substrate are not provided at locations of connection terminals. A resin body seals at least the connection terminals and the exposed first ends of wirings (leads). In a scheme in which the connection terminals are located in a peripheral part of the chip main surface, the wiring substrate protrudes beyond the chip boundary where the connection terminals are arranged, and the resin body shape is restricted by the protruding part of the wiring substrate.
    Type: Grant
    Filed: April 28, 2005
    Date of Patent: August 15, 2006
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd., Akita Electronics Systems, Co., Ltd.
    Inventors: Chuichi Miyazaki, Yukiharu Akiyama, Masnori Shibamoto, Tomoaki Kudaishi, Ichiro Anjoh, Kunihiko Nishi, Asao Nishimura, Hideki Tanaka, Ryosuke Kimoto, Kunihiro Tsubosaki, Akio Hasebe, Takehiro Ohnishi, Noriou Shimada, Shuji Eguchi, Hiroshi Koyama, Akira Nagai, Masahiko Ogino
  • Patent number: 7038325
    Abstract: In a semiconductor device having a three-layered buffer layer comprising core layer 1 having interconnected foams such as a three-dimensional reticular structure and adhesive layers 2 provided on both sides of the core layer as a stress buffer layer between semiconductor chip 5 and wiring 4 to lessen a thermal stress generated between the semiconductor device and the package substrate, where a thickness ratio of the core layer 1 to total buffer layer is at least 0.2, the production process can be simplified by using such a buffer layer, thereby improving the mass production capacity and enhancing the package reliability.
    Type: Grant
    Filed: April 23, 2004
    Date of Patent: May 2, 2006
    Assignees: Hitachi Cable, Ltd., Renesas Technology Corp.
    Inventors: Masahiko Ogino, Shuji Eguchi, Akira Nagai, Takumi Ueno, Masanori Segawa, Hiroyoshi Kokaku, Toshiaki Ishii, Ichiro Anjoh, Asao Nishimura, Chuichi Miyazaki, Mamoru Mita, Norio Okabe
  • Patent number: 6998958
    Abstract: A remote control system for precisely identifying a distance from the vehicle to an entry key and favorably controlling a vehicle-mounted device such as a door corresponding to the distance. The system comprises a transmitter transmitting different types of response demand signals within a predetermined communication area outside the vehicle, a vehicle mounted receiver for receiving a response signal released from a portable transmitter/receiver in response to the reception of the response demand signal, a controller controlling the vehicle mounted device corresponding to the reception of the response signal by the vehicle mounted receiver. Locking and/or unlocking door(s) of the vehicle are controlled on the basis of whether or not the receiver receives the response signal to a response demand signal other than one having the largest communication area.
    Type: Grant
    Filed: June 25, 2004
    Date of Patent: February 14, 2006
    Assignees: Honda Giken Kogyo Kabushiki Kaisha, Hondalock Mfg., Co., Ltd.
    Inventors: Suguru Asakura, Akira Nagai, Kentaro Yoshimura, Munehisa Nozawa, Sadanori Watarai
  • Patent number: 6994806
    Abstract: A conductive paste for defogging heat wires of automobile windows contains a silver powder having particle size in the range of about 0.1 to 20 ?m, a molybdenum compound such as molybdenum silicide or molybdenum boride, a glass frit having s softening point of 730° C. or less and an organic vehicle. The conductive paste can uniformly darken the conductive heat wire regions of the automobile window without producing any harmful substances. Also, it can ensure sufficient bonding strength of lead wires.
    Type: Grant
    Filed: December 17, 2003
    Date of Patent: February 7, 2006
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Akira Nagai, Fumiya Adachi
  • Patent number: 6989600
    Abstract: CMOS logic LSI comprises, as a part thereof, n-channel MISFET's (Qn), p-channel MISFET's (Qp) and a first-layer wiring (11) to a third-layer (13) formed on a main surface of a silicon substrate (1), and as another part, a fourth-layer wiring (14) to a seventh-layer wiring (17) formed on a main surface of a glass substrate (30) different from the silicon substrate (1). The main surface of the silicon substrate (1) and the main surface of the glass substrate (30) are arranged in face-to-face relation with each other, and a plurality of microbumps (20A) formed at the uppermost portion of the silicon substrate (1) and a plurality of microbumps (20B) formed at the uppermost portion of the glass substrate (30) are electrically connected, thereby constituting the CMOS logic LSI as a whole.
    Type: Grant
    Filed: March 30, 2001
    Date of Patent: January 24, 2006
    Assignee: Renesas Technology Corporation
    Inventors: Masaharu Kubo, Ichiro Anjo, Akira Nagai, Osamu Kubo, Hiromi Abe, Hitoshi Akamine
  • Publication number: 20050230826
    Abstract: An object of the present invention is to manufacture a semiconductor device improved in the connection reliability between a bump electrode and a substrate electrode. Supposing that an elastic modulus of an adhesive material, which is used for the purpose of electrically connecting a metal bump and an interconnect pattern and sealing the circuit surface of LSI of an LSI chip, after thermosetting is Ea; an elastic modulus of an insulating material constituting the surface layer of a packaging substrate after thermosetting is Eb; and an elastic modulus of a core material, if the substrate is a multilayer substrate having a core layer, is Ec, the material system of the present invention satisfies the following rational expression at normal temperature or a thermal contact bonding temperature of the adhesive material: at least Ea<Eb<Ec, preferably ?Eb<Ea<Eb<3Ea(<Ec).
    Type: Application
    Filed: March 22, 2005
    Publication date: October 20, 2005
    Inventors: Naotaka Tanaka, Kenya Kawano, Akira Nagai, Koji Tasaki, Masaaki Yasuda
  • Publication number: 20050212142
    Abstract: A semiconductor device includes a semiconductor chip formed with connection terminals, an elastic structure interposed between a main surface of the chip and a wiring substrate formed with wirings connected at first ends thereof to the connection terminals, and bump electrodes connected to the other ends of the wirings. The connection terminals may be at a center part or in peripheral part(s) of the chip main surface and both the elastic structure and wiring substrate are not provided at locations of connection terminals. A resin body seals at least the connection terminals and the exposed first ends of wirings (leads). In a scheme in which the connection terminals are located in a peripheral part of the chip main surface, the wiring substrate protrudes beyond the chip boundary where the connection terminals are arranged, and the resin body shape is restricted by the protruding part of the wiring substrate.
    Type: Application
    Filed: April 28, 2005
    Publication date: September 29, 2005
    Inventors: Chuichi Miyazaki, Yukiharu Akiyama, Masnori Shibamoto, Tomoaki Kudaishi, Ichiro Anjoh, Kunihiko Nishi, Asao Nishimura, Hideki Tanaka, Ryosuke Kimoto, Kunihiro Tsubosaki, Akio Hasebe, Takehiro Ohnishi, Noriou Shimada, Shuji Eguchi, Hiroshi Koyama, Akira Nagai, Masahiko Ogino
  • Publication number: 20050200019
    Abstract: A semiconductor device includes a semiconductor chip formed with connection terminals, an elastic structure interposed between a main surface of the chip and a wiring substrate formed with wirings connected at first ends thereof to the connection terminals, and bump electrodes connected to the other ends of the wirings. The connection terminals may be at a center part or in peripheral part(s) of the chip main surface and both the elastic structure and wiring substrate are not provided at locations of connection terminals. A resin body seals at least the connection terminals and the exposed first ends of wirings (leads). In a scheme in which the connection terminals are located in a peripheral part of the chip main surface, the wiring substrate protrudes beyond the chip boundary where the connection terminals are arranged, and the resin body shape is restricted by the protruding part of the wiring substrate.
    Type: Application
    Filed: April 28, 2005
    Publication date: September 15, 2005
    Inventors: Chuichi Miyazaki, Yukiharu Akiyama, Masnori Shibamoto, Tomoaki Kudaishi, Ichiro Anjoh, Kunihiko Nishi, Asao Nishimura, Hideki Tanaka, Ryosuke Kimoto, Kunihiro Tsubosaki, Akio Hasebe, Takehiro Ohnishi, Noriou Shimada, Shuji Eguchi, Hiroshi Koyama, Akira Nagai, Masahiko Ogino
  • Patent number: 6940162
    Abstract: In a multi chip module of a structure wherein a plurality of bare or packaged semiconductor chips are mounted on a single wiring board and upper surfaces of the semiconductor chips are covered with a single heat spread plate, the whole space around the semiconductor chips thus sandwiched between the wiring board and the heat spread plate is filled with resin. By so doing, the semiconductor chips are interconnected through the resin, so that even if a stress is exerted on any of the chips, it is dispersed and therefore it is possible to diminish the occurrence of cracks in the chips and the heat spread plate caused by stress concentration. Besides, since the semiconductor chips and the heat spread plate are bonded together with resin, even if there are variations in size of the chips, both can be bonded easily. Further, the bonding of all the chips and the heat spread plate can be done in a single process.
    Type: Grant
    Filed: May 7, 2004
    Date of Patent: September 6, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Shuji Eguchi, Akira Nagai, Haruo Akahoshi, Takumi Ueno, Toshiya Satoh, Masahiko Ogino, Asao Nishimura, Ichiro Anjo, Hideki Tanaka
  • Patent number: 6888230
    Abstract: Semiconductor devices, semiconductor wafers, and semiconductor modules are provided, wherein: the semiconductor device has a small warp; damage at the chip edge and cracks occurring in a dropping test are scarcely generated; and the semiconductor device is superior in mounting reliability and mass producibility. The semiconductor includes a semiconductor chip 64; a porous stress relaxing layer 3 provided on the plane, whereon circuits and electrodes are formed, of the semiconductor chip; a circuit layer 2 provided on the stress relaxing layer and connected to the electrodes; and external terminals 10 provided on the circuit layer; wherein an organic protecting film 7 is formed on the plane, opposite to the stress relaxing layer, of the semiconductor chip, and respective side planes of the stress relaxing layer, the semiconductor chip 6, and the protecting film 7 are exposed outside on the same plane.
    Type: Grant
    Filed: October 28, 1999
    Date of Patent: May 3, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Masahiko Ogino, Takumi Ueno, Shuji Eguchi, Akira Nagai, Toshiya Satoh, Toshiaki Ishii, Hiroyoshi Kokaku, Tadanori Segawa, Nobutake Tsuyuno, Asao Nishimura, Ichiro Anjoh
  • Patent number: 6878448
    Abstract: The present invention provides a biphenyl based epoxy resin comprising a curing agent and an inorganic filler containing an alkali alkaline earth metal oxide wherein the epoxy resin has a variation rate of hardness at 25° C. and a relative humidity of 50% for 72 hours of less than 10% and a variation rate of flow at 25° C. and a relative humidity of 20% or below for 72 hours of less than 20%.
    Type: Grant
    Filed: September 25, 2001
    Date of Patent: April 12, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Toshiaki Ishii, Hiroyoshi Kokaku, Akira Nagai, Takao Miwa
  • Publication number: 20050064159
    Abstract: There are provided a resin composition comprising a crosslinking component with a weight average molecular weight of 1,000 or less having a plurality of styrene groups and represented by the following formula: wherein R is a hydrocarbon skeleton, each of R1s is a hydrogen atom or a hydrocarbon group, each of R2, R3 and R4 is a hydrogen atom or an alkyl group, m is an integer of 1 to 4, and n is an integer of 2 or more, at least one high-molecular weight compound, an inorganic filler, and at least one treating agent for said inorganic filler; its cured product; and a prepreg, a laminate sheet having a conductor layer, and a multilayer printed wiring board obtained by processing the conductor layer of the laminate sheet into wiring.
    Type: Application
    Filed: September 8, 2004
    Publication date: March 24, 2005
    Applicant: Hitachi Chemical Company, Ltd.
    Inventors: Satoru Amou, Morimichi Umino, Akira Nagai, Yoshihiro Nakamura, Nobuyuki Minami
  • Patent number: 6855952
    Abstract: A semiconductor device wherein a resin containing as a cross-linking component a compound having a plurality of styrene group and represented by chemical formula [1] is used as an insulating material: where R is a hydrocarbon structure which may have a substituent group or groups, R1 is hydrogen, methyl, or ethyl, m is and integer of 1 to 4, and n is an integer of not less than 2. With this, a semiconductor device and a semiconductor package which show excellent transmission characteristics and less power consumption are provided.
    Type: Grant
    Filed: March 28, 2003
    Date of Patent: February 15, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Akira Nagai, Satoru Amou, Shinji Yamada, Takao Ishikawa, Hiroshi Nakano
  • Publication number: 20050029515
    Abstract: An organic/inorganic oxide mixture has high capacitance density so as to realize a capacitor material that can be self-contained in a substrate. The mixture film made of inorganic oxide particle has a mean particle size of less than 90 nm dispersed in organic polymer, of which relative dielectric constant is more than 10 and thickness is less than 900 nm.
    Type: Application
    Filed: August 6, 2004
    Publication date: February 10, 2005
    Applicant: Hitachi, Ltd.
    Inventors: Akira Nagai, Toshiyuki Ohno, Fusao Hojo, Shinji Yamada, Mikio Konno, Yomokazu Tanase, Daisuke Naga
  • Publication number: 20050020781
    Abstract: There is provided a resin composition suitable for insulating materials for use in electronic parts for handling high frequency signals, low in dielectric constant and low in dielectric dissipation factor, capable of forming thin film by low temperature curing, excellent in the adhesiveness to conductive foil and excellent in flexibility; a cured product derived from the composition; and a film substrate and an electronic part using the composition.
    Type: Application
    Filed: February 26, 2004
    Publication date: January 27, 2005
    Inventors: Masatoshi Sugimasa, Akira Nagai, Shinji Yamada, Satoru Amou
  • Patent number: 6841628
    Abstract: The present invention relates to a resin composition which gives a resin product with a low hygroscopic property, an adhesive for connecting a circuit member and a circuit board, and provides a resin composition, an adhesive for connecting a circuit member and a circuit board comprising (A) a polyhydroxy polyether resin represented by the formula (I): wherein R1 to R8 each represent H, C1-4 alkyl group, C2-5 alkenyl group, C1-4 hydroxyalkyl group or halogen atom; Ra represents H or C1-2 alkyl group; Rb represents C2-13 alkyl group; and n is a recurring number, or the following formula (II): wherein R9 to R12 each represent H, C1-6 alkyl group, C1-6 hydroxyalkyl group or halogen atom; Rc to Rf each represent H, C1-6 alkyl group, cyclohexyl group, aryl group, aralkyl group or halogen atom; and m is a recurring number, and (B) a three dimensionally cross-linkable resin.
    Type: Grant
    Filed: February 9, 2001
    Date of Patent: January 11, 2005
    Assignee: Hitachi Chemical Co., Ltd.
    Inventors: Satoru Oota, Masami Yusa, Akira Nagai
  • Publication number: 20040251540
    Abstract: In a multi chip module of a structure wherein a plurality of bare or packaged semiconductor chips are mounted on a single wiring board and upper surfaces of the semiconductor chips are covered with a single heat spread plate, the whole space around the semiconductor chips thus sandwiched between the wiring board and the heat spread plate is filled with resin.
    Type: Application
    Filed: May 7, 2004
    Publication date: December 16, 2004
    Inventors: Shuji Eguchi, Akira Nagai, Haruo Akahoshi, Takumi Ueno, Toshiya Satoh, Masahiko Ogino, Asao Nishimura, Ichiro Anjo, Hideki Tanaka