Patents by Inventor Akira Nagai

Akira Nagai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6621154
    Abstract: A miniature semiconductor apparatus is outstanding in reflow resistance, temperature cycle property, and PCT resistance corresponding to high density packing, high densification, and speeding up of processing. The semiconductor apparatus has at least one stress cushioning layer on a semiconductor element with an electrode pad formed, having a conductor on the stress cushioning layer, having a conductor for conducting the electrode pad and conductor via a through hole passing through the stress cushioning layer between the electrode pad and the conductor, having an external electrode on the conductor, and having a stress cushioning layer in an area other than the area where the external electrode exists and a conductor protection layer on the conductor, wherein the stress cushioning layer includes crosslinking acrylonitrile-butadiene rubber having an epoxy resin which is solid at 25° C. and a carboxyl group.
    Type: Grant
    Filed: September 28, 2000
    Date of Patent: September 16, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Toshiya Satoh, Masahiko Ogino, Tadanori Segawa, Takao Miwa, Akira Nagai, Akihiro Yaguchi, Ichiro Anjo, Asao Nishimura
  • Publication number: 20030148558
    Abstract: CMOS logic LSI comprises, as a part thereof, n-channel MISFET's (Qn), p-channel MISFET's (Qp) and a first-layer wiring (11) to a third-layer (13) formed on a main surface of a silicon substrate (1), and as another part, a fourth-layer wiring (14) to a seventh-layer wiring (17) formed on a main surface of a glass substrate (30) different from the silicon substrate (1). The main surface of the silicon substrate (1) and the main surface of the glass substrate (30) are arranged in face-to-face relation with each other, and a plurality of microbumps (20A) formed at the uppermost portion of the silicon substrate (1) and a plurality of microbumps (20B) formed at the uppermost portion of the glass substrate (30) are electrically connected, thereby constituting the CMOS logic LSI as a whole.
    Type: Application
    Filed: October 3, 2002
    Publication date: August 7, 2003
    Inventors: Masaharu Kubo, Ichiro Anjo, Akira Nagai, Osamu Kubo, Hiromi Abe, Hitoshi Akamine
  • Publication number: 20030102465
    Abstract: A conductive paste for defogging heat wires of automobile windows contains a silver powder having particle size in the range of about 0.1 to 20 &mgr;m, a molybdenum compound such as molybdenum silicide or molybdenum boride, a glass frit having s softening point of 730° C. or less and an organic vehicle. The conductive paste can uniformly darken the conductive heat wire regions of the automobile window without producing any harmful substances. Also, it can ensure sufficient bonding strength of lead wires.
    Type: Application
    Filed: October 22, 2002
    Publication date: June 5, 2003
    Inventors: Akira Nagai, Fumiya Adachi
  • Patent number: 6573615
    Abstract: The present invention provides an electronic key system for a vehicle which is a type of starting the engine with pressing a button switch and can be operated at familiar mechanical movements thus easing the user or driver of an unfamiliar conception as well as improved in the operability and the protection against theft. When a quick-start switch mounted on the steering wheel is pressed after the code identification is valid, a CPU switches on the start switch to energize a starter motor. The CPU judges from a change in the voltage of an alternator that the engine starts running. As the engine runs, an ignition switch is automatically turned to the II position with a valet key inserted. The engine can be stopped by the valet key turning to the 0 position. In the parking state, the valet key may be detached from or accommodated in the ignition switch.
    Type: Grant
    Filed: September 15, 2000
    Date of Patent: June 3, 2003
    Assignee: Honda Giken Kogyo Kabushiki Kaisha
    Inventors: Suguru Asakura, Akira Nagai, Yoshikazu Imura, Kentaro Yoshimura, Munehisa Nozawa
  • Publication number: 20030071348
    Abstract: In a multi-chip module, a plurality of semiconductor chips are mounted on a single wiring board. Upper surfaces of the chips are covered with a single heat spread plate, and the whole space around the chips sandwiched between the wiring board and the heat spread plate is filled with resin. The semiconductor chips are interconnected through the resin so that any stress exerted on any chips is dispersed. This diminishes the occurrence of cracks caused by stress concentration. Since the chips and the heat spread plate are bonded together with resin, even if there are variations in size of the chips, both can be bonded easily. Further, the bonding of all the chips and the heat spread plate can be done in a single process.
    Type: Application
    Filed: November 25, 2002
    Publication date: April 17, 2003
    Inventors: Shuji Eguchi, Akira Nagai, Haruo Akahoshi, Takumi Ueno, Toshiya Satoh, Masahiko Ogino, Asao Nishimura, Ichiro Anjo, Hideki Tanaka
  • Publication number: 20030049193
    Abstract: The present invention provides a thermal stable low elastic modulus material, which has high thermal stability, is little in change in dynamic characteristics such as coefficient of thermal expansion and elastic modulus within a temperature of −50° C. to 300° C., has an elastic modulus at room temperature of 2-0.01 GPa and is high in reliability of electric insulation regardless of a temperature fluctuation, and provides a semiconductor device using the same.
    Type: Application
    Filed: March 15, 2002
    Publication date: March 13, 2003
    Inventors: Yuichi Satsu, Morimichi Umino, Takumi Ueno, Akio Takahashi, Akira Nagai, Toshiya Satoh, Shinji Yamada, Kazuhiro Suzuki
  • Publication number: 20030047351
    Abstract: The present invention provides a thermal stable low elastic modulus material, which has high thermal stability, is little in change in dynamic characteristics such as coefficient of thermal expansion and elastic modulus within a temperature of −50° C. to 300° C., has an elastic modulus at room temperature of 2-0.01 GPa and is high in reliability of electric insulation regardless of a temperature fluctuation, and provides a semiconductor device using the same.
    Type: Application
    Filed: July 5, 2002
    Publication date: March 13, 2003
    Inventors: Yuichi Satsu, Morimichi Umino, Takumi Ueno, Akio Takahashi, Akira Nagai, Toshiya Satoh, Shinji Yamada, Kazuhiro Suzuki
  • Publication number: 20030027942
    Abstract: The present invention relates to a resin composition which gives a resin product with a low hygroscopic property, an adhesive for connecting a circuit member and a circuit board, and provides a resin composition, an adhesive for connecting a circuit member and a circuit board comprising (A) a polyhydroxy polyether resin represented by the 1
    Type: Application
    Filed: August 9, 2002
    Publication date: February 6, 2003
    Inventors: Satoru Oota, Masami Yusa, Akira Nagai
  • Patent number: 6515371
    Abstract: A semiconductor device including a semiconductor chip having connection terminals in a peripheral part of a main surface thereof; an elastic body disposed on the main surface leaving the connection terminals exposed; an insulating tape formed on the elastic body and having openings in areas where the connection terminals are situated; plural leads formed on the top surface of the insulating tape, one end of each lead being connected to one of the connection terminals and the other end being disposed on the elastic body; plural bump electrodes formed on the other ends of the plural leads; and a resin body for sealing the connection terminals and one end of each of the leads, wherein the insulating tape protrudes beyond the chip where the plural connection terminals are arranged, and wherein the shape of the resin body is restricted by the protruding part of the insulating tape.
    Type: Grant
    Filed: October 23, 2001
    Date of Patent: February 4, 2003
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd., Akita Electronics Co., Ltd.
    Inventors: Yukiharu Akiyama, Tomoaki Kudaishi, Takehiro Ohnishi, Noriou Shimada, Shuji Eguchi, Asao Nishimura, Ichiro Anjo, Kunihiro Tsubosaki, Chuichi Miyazaki, Hiroshi Koyama, Masanori Shibamoto, Akira Nagai, Masahiko Ogino
  • Patent number: 6489013
    Abstract: A resin compound, which causes very little thermal stress even when a flip chip is mounted, has a low modulus of elasticity, and a heat resistance which is sufficiently high for solder floating at 300° C., and the resin compound also can be used in an adhesive film, a metal-clad adhesive film, a circuit board, and an assembly structure. The resin compound contains (A) a polyamide imide with siloxane bond, (B) a acrylic polymer with a weight-average molecular weight of 500,000 or more, (C) a thermoset resin, and (D) a solvent.
    Type: Grant
    Filed: February 21, 2001
    Date of Patent: December 3, 2002
    Assignees: Hitachi, Ltd., Shin-Kobe Electric Machinery
    Inventors: Akira Nagai, Masayuki Noda
  • Publication number: 20020158343
    Abstract: In a semiconductor device having a three-layered buffer layer comprising core layer 1 having interconnected foams such as a three-dimensional reticular structure and adhesive layers 2 proved on both sides of the core layer as a stress buffer layer between semiconductor chip 5 and wiring 4 to lessen a thermal stress generated between the semiconductor device and the package substrate, where a thickness ratio of core layer 1 to total buffer layer is at least 0.2, the production process can be simplified by using such a buffer layer, thereby improving the mass production capacity and enhancing the package reliability.
    Type: Application
    Filed: April 30, 2002
    Publication date: October 31, 2002
    Inventors: Masahiko Ogino, Shuji Eguchi, Akira Nagai, Takumi Ueno, Masanori Segawa, Hiroyoshi Kokaku, Toshiaki Ishii, Ichiro Anjoh, Asao Nishimura, Chuichi Miyazaki, Mamoru Mita, Norio Okabe
  • Publication number: 20020160185
    Abstract: A semiconductor device having a superior connection reliability is obtained by providing a buffer body for absorbing the difference of thermal expansion between the mounting substrate and the semiconductor element in a semiconductor package structure, even if an organic material is used for the mounting substrate. A film material is used as the body for buffering the thermal stress generated by the difference in thermal expansion between the mounting substrate and the semiconductor element. The film material has modulus of elasticity of at least 1 MPa in the reflow temperature range (200-250° C.).
    Type: Application
    Filed: May 6, 2002
    Publication date: October 31, 2002
    Inventors: Akira Nagai, Shuji Eguchi, Masahiko Ogino, Masanori Segawa, Toshiak Ishii, Nobutake Tsuyuno, Hiroyoshi Kokaku, Rie Hattori, Makoto Morishima, Ichiro Anjoh, Kunihiro Tsubosaki, Chuichi Miyazaki, Makoto Kitano, Mamoru Mita, Norio Okabe
  • Publication number: 20020146569
    Abstract: A sliding article, such as a window glass, with an electrode film having superior wear resistance and sufficient film strength, includes a sliding member and an electrode film formed on the sliding member, the electrode film containing an inorganic material made of at least one material selected from the group consisting of niobium silicide, titanium silicide, and zirconium silicide. The electrode film is formed from a conductive paste which preferably includes a glass frit, an organic vehicle and the inorganic material.
    Type: Application
    Filed: January 28, 2002
    Publication date: October 10, 2002
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Akira Nagai, Haruhiko Kano, Daizou Inoue
  • Publication number: 20020146565
    Abstract: The present invention provides a biphenyl based epoxy resin comprising a curing agent and an inorganic filler containing an alkali earth metal oxide wherein the epoxy resin has a variation rate of hardness at 25° C. and a relative humidity of 50% for 72 hours of less than 10% and a variation rate of flow at 25° C. and a relative humidity of 20% or below for 72 hours of less than 20%.
    Type: Application
    Filed: September 25, 2001
    Publication date: October 10, 2002
    Inventors: Toshiaki Ishll, Hiroyoshi Kokaku, Akira Nagai, Takao Miwa
  • Publication number: 20020130412
    Abstract: A semiconductor device and a manufacturing method thereof, which device includes a semiconductor element arranged to form integrated circuitry, a plurality of electrode pads formed on the side of the integrated circuitry formation surface of the semiconductor element, bump electrodes for electrically connecting to the electrode pads through a conductive layer, and a stress relaxation layer formed between the integrated circuitry formation surface and electrode pads on one hand and the bump electrodes and conductive layer on the other hand, the stress relaxation layer being adhered thereto, wherein more than one third of the stress relaxation layer from a surface thereof is cut away for removal and wherein the stress relaxation layer is subdivided into a plurality of regions. Accordingly, it is possible to provide a semiconductor device capable of offering high density mounting schemes with increased reliability while reducing production costs.
    Type: Application
    Filed: May 2, 2002
    Publication date: September 19, 2002
    Inventors: Akira Nagai, Takumi Ueno, Haruo Akahoshi, Syuji Eguchi, Masahiko Ogino, Toshiya Satoh, Asao Nishimura, Ichiro Anjoh
  • Patent number: 6452780
    Abstract: A capacitor including a ceramic body, a glass layer formed on each of opposite surfaces of the ceramic body, and a first metallic layer formed on the glass layer. Preferably, a lead terminal is connected to the first metallic layer or to a second metallic layer which is provided on the first metallic layer, by use of solder containing Pb in an amount of 2.5 wt. % or less. Preferably, a lead terminal which is plated with a substance containing Pb in an amount of 5 wt. % or less is soldered onto the first metallic layer or the second metallic layer.
    Type: Grant
    Filed: December 27, 2000
    Date of Patent: September 17, 2002
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Shinichi Kobayashi, Shuji Watanabe, Yoshitaka Kageyama, Akira Nagai, Osamu Yamaoka, Mitsuru Nagashima, Yuko Ihara
  • Patent number: 6433440
    Abstract: In a semiconductor device having a three-layered buffer layer comprising core layer 1 having interconnected foams such as a three-dimensional reticular structure and adhesive layers 2 provided on both sides of the core layer as a stress buffer layer between semiconductor chip 5 and wiring 4 to lessen a thermal stress generated between the semiconductor device and the package substrate, where a thickness ratio of core layer 1 to total buffer layer is at least 0.2, the production process can be simplified by using such a buffer layer, thereby improving the mass production capacity and enhancing the package reliability.
    Type: Grant
    Filed: June 5, 1998
    Date of Patent: August 13, 2002
    Assignees: Hitachi, Ltd., Hitachi Cable, Ltd.
    Inventors: Masahiko Ogino, Shuji Eguchi, Akira Nagai, Takumi Ueno, Masanori Segawa, Hiroyoshi Kokaku, Toshiaki Ishii, Ichiro Anjoh, Asao Nishimura, Chuichi Miyazaki, Mamoru Mita, Norio Okabe
  • Patent number: 6430027
    Abstract: A pulse generating capacitor is provided in which a capacitor element has electrodes provided on the front and rear faces thereof, and lead terminals connected to the electrodes by means of bonding members. The bonding members can contain Ag as a major component with a ZrO2 powder added thereto at a content of about 20% to 60% by volume. The capacitor solves a problem of crack generation on the capacitor element in response to thermal cycling, while maintaining the effects of preventing its pulse voltage from being decreased and enhancing the bonding strength of its lead terminals.
    Type: Grant
    Filed: September 24, 2001
    Date of Patent: August 6, 2002
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Shinichi Kobayashi, Yuko Ihara, Shuji Watanabe, Yoshitaka Kageyama, Akira Nagai
  • Patent number: 6423571
    Abstract: A method of forming a semiconductor device having a multi-layered wiring structure that includes a conductor layer to be electrically connected to a packaging substrate, with the multi-layered wiring structure being provided on a circuit formation surface of a semiconductor chip. Ball-like terminals are formed, disposed in a grid array on the surface of the multi-layered wiring structure on the packaging substrate side. The multi-layered wiring structure is formed to include a buffer layer for relieving a thermal stress provided between the semiconductor chip and the packaging substrate, due to the packaging procedure. In the semiconductor device formed, the wiring distance is shorter than that of a conventional semiconductor device, so that an inductance component becomes smaller, to thereby increase signal speed.
    Type: Grant
    Filed: June 20, 2001
    Date of Patent: July 23, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Masahiko Ogino, Akira Nagai, Shuji Eguchi, Toshiaki Ishii, Masanori Segawa, Haruo Akahoshi, Akio Takahashi, Takao Miwa, Naotaka Tanaka, Ichirou Anjou
  • Patent number: 6396145
    Abstract: A semiconductor device includes a semiconductor element arranged to form integrated circuitry, a plurality of electrode pads formed on the side of the integrated circuitry formation surface of the in semiconductor element, bump electrodes for external connection electrically connected to the electrode pads through a conductive layer, and a stress relaxation layer formed between the integrated circuitry formation surface and electrode pads on one hand and the bump electrodes and conductive layer on the other hand, the stress relaxation layer being adhered thereto, wherein more than one third of the stress relaxation layer from a surface thereof is cut away for removal and wherein the stress relaxation layer is subdivided into a plurality of regions.
    Type: Grant
    Filed: December 30, 1999
    Date of Patent: May 28, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Akira Nagai, Takumi Ueno, Haruo Akahoshi, Syuji Eguchi, Masahiko Ogino, Toshiya Satoh, Asao Nishimura, Ichiro Anjoh