Patents by Inventor Akira Nishiyama

Akira Nishiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7646072
    Abstract: It is possible to prevent the deterioration of device characteristic as much as possible. A semiconductor device includes: a semiconductor substrate; a gate insulating film provided above the semiconductor substrate and containing a metal, oxygen and an additive element; a gate electrode provided above the gate insulating film; and source/drain regions provided in the semiconductor substrate on both sides of the gate electrode. The additive element is at least one element selected from elements of Group 5, 6, 15, and 16 at a concentration of 0.003 atomic % or more but 3 atomic % or less.
    Type: Grant
    Filed: January 22, 2009
    Date of Patent: January 12, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuuichi Kamimuta, Akira Nishiyama, Yasushi Nakasaki, Tsunehiro Ino, Masato Koyama
  • Publication number: 20090326246
    Abstract: Aiming at production of an optically active 3-amino nitrogen-containing compound which is useful as an intermediate in synthesis of medicines and pesticides, in particular, an optically active 1-protected-3-aminopyrrolidine derivative, from an inexpensive and readily available raw material by a process which is efficient and can be practiced industrially, an optically active 3-amino nitrogen-containing compound is produced by performing a reaction of an optically active 3-substituted nitrogen-containing compound with ammonia, methylamine, ethylamine or dimethylamine in the presence of water. In addition, a 1-protected-3-aminopyrrolidine derivative is produced by performing a reaction of an optically active 1-protected-3-(sulfonyloxy)pyrrolidine derivative with ammonia, methylamine, ethylamine, or dimethylamine in the presence of methanol, ethanol, n-propanol, or isopropanol under a pressure of less than 30 barr.
    Type: Application
    Filed: July 23, 2007
    Publication date: December 31, 2009
    Applicant: Kaneka Corporation
    Inventors: Masatoshi Ohnuki, Masashi Izumida, Akira Nishiyama, Shingo Matsumoto
  • Patent number: 7632728
    Abstract: A semiconductor device includes a substrate, a p-channel MIS transistor formed on an n-type well on the substrate, having a first gate dielectric and a first gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 80% or more, and an n-channel MIS transistor formed on a p-type well on the substrate, having a second gate dielectric and a second gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 60% or less.
    Type: Grant
    Filed: September 10, 2008
    Date of Patent: December 15, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masato Koyama, Reika Ichihara, Yoshinori Tsuchiya, Yuuichi Kamimuta, Akira Nishiyama
  • Patent number: 7612413
    Abstract: A semiconductor device includes a substrate, a p-channel MIS transistor formed on the substrate, the p-channel MIS transistor having a first gate electrode, and an n-channel MIS transistor formed on the substrate separately from the p-channel MIS transistor, the n-channel MIS transistor having a second gate electrode. Each of the first gate electrode and the second gate electrode is formed of an alloy of Ta and C in which a mole ratio of C to Ta (C/Ta) is from 2 to 4.
    Type: Grant
    Filed: August 1, 2006
    Date of Patent: November 3, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masato Koyama, Reika Ichihara, Yoshinori Tsuchiya, Yuuichi Kamimuta, Akira Nishiyama
  • Patent number: 7606640
    Abstract: A cooling apparatus able to rotate cooling fans with required lowest limit speeds, and able to suppress power consumption and generated noise includes a cooling unit for cooling an object to be cooled by a cooling amount in accordance with a level of a supplied drive signal; a temperature detector for detecting the temperature of the object; a drive circuit for amplifying the drive signal and supplying an output signal to the cooling unit; a memory for storing correction data for correcting circuit error in the drive circuit; and a control unit for generating the drive signal based on the detected temperature of the object, correcting error in the output signal of the drive circuit based on the correction data stored in the memory, and outputting the generated drive signal to the drive circuit. The cooling apparatus may be used in a projection type display device.
    Type: Grant
    Filed: November 30, 2005
    Date of Patent: October 20, 2009
    Assignee: Sony Corporation
    Inventors: Koji Hirai, Yoshitake Kondo, Akira Nishiyama
  • Patent number: 7576397
    Abstract: A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected from Ti, Zr, Hf, Ta, Sc, Y, a lanthanoide and actinide series and of one selected from boride, silicide and germanide compounds of the one metal element, and a pMISFET formed on the substrate, the pMISFET including a second dielectric formed on the substrate and a second metal gate electrode formed on the second dielectric and made of the same material as that of the first metal gate electrode, at least a portion of the second dielectric facing the second metal gate electrode being made of an insulating material different from that of at least a portion of the first dielectric facing the first metal gate electrode.
    Type: Grant
    Filed: August 20, 2007
    Date of Patent: August 18, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Reika Ichihara, Yoshinori Tsuchiya, Masato Koyama, Akira Nishiyama
  • Publication number: 20090166767
    Abstract: It is possible to prevent the deterioration of device characteristic as much as possible. A semiconductor device includes: a semiconductor substrate; a gate insulating film provided above the semiconductor substrate and containing a metal, oxygen and an additive element; a gate electrode provided above the gate insulating film; and source/drain regions provided in the semiconductor substrate on both sides of the gate electrode. The additive element is at least one element selected from elements of Group 5, 6, 15, and 16 at a concentration of 0.003 atomic % or more but 3 atomic % or less.
    Type: Application
    Filed: January 22, 2009
    Publication date: July 2, 2009
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yuuichi Kamimuta, Akira Nishiyama, Yasushi Nakasaki, Tsunehiro Ino, Masato Koyama
  • Patent number: 7541657
    Abstract: There is disclosed a semiconductor device comprising a P-channel MIS transistor which includes an N-type semiconductor layer, a first gate insulating layer formed on the N-type semiconductor layer and containing a carbon compound of a metal, and an N-channel MIS transistor which includes a P-type semiconductor layer, a second gate insulating layer formed on the P-type semiconductor layer, and a second gate electrode formed on the second gate insulating layer.
    Type: Grant
    Filed: June 5, 2008
    Date of Patent: June 2, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masato Koyama, Akira Nishiyama, Yoshinori Tsuchiya, Reika Ichihara
  • Publication number: 20090134479
    Abstract: It is possible to prevent the deterioration of device characteristic as much as possible. A semiconductor device includes: a semiconductor substrate; a gate insulating film provided above the semiconductor substrate and containing a metal, oxygen and an additive element; a gate electrode provided above the gate insulating film; and source/drain regions provided in the semiconductor substrate on both sides of the gate electrode. The additive element is at least one element selected from elements of Group 5, 6, 15, and 16 at a concentration of 0.003 atomic % or more but 3 atomic % or less.
    Type: Application
    Filed: January 22, 2009
    Publication date: May 28, 2009
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yuuichi Kamimuta, Akira Nishiyama, Yasushi Nakasaki, Tsunehiro Ino, Masato Koyama
  • Publication number: 20090134480
    Abstract: It is possible to prevent the deterioration of device characteristic as much as possible. A semiconductor device includes: a semiconductor substrate; a gate insulating film provided above the semiconductor substrate and containing a metal, oxygen and an additive element; a gate electrode provided above the gate insulating film; and source/drain regions provided in the semiconductor substrate on both sides of the gate electrode. The additive element is at least one element selected from elements of Group 5, 6, 15, and 16 at a concentration of 0.003 atomic % or more but 3 atomic % or less.
    Type: Application
    Filed: January 22, 2009
    Publication date: May 28, 2009
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yuuichi Kamimuta, Akira Nishiyama, Yasushi Nakasaki, Tsunehiro Ino, Masato Koyama
  • Publication number: 20090072331
    Abstract: A semiconductor device includes a substrate, a p-channel MIS transistor formed on an n-type well on the substrate, having a first gate dielectric and a first gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 80% or more, and an n-channel MIS transistor formed on a p-type well on the substrate, having a second gate dielectric and a second gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 60% or less.
    Type: Application
    Filed: September 10, 2008
    Publication date: March 19, 2009
    Inventors: Masato Koyama, Reika Ichihara, Yoshinori Tsuchiya, Yuuchi Kamimuta, Akira Nishiyama
  • Publication number: 20090072330
    Abstract: A semiconductor device includes a substrate, a p-channel MIS transistor formed on an n-type well on the substrate, having a first gate dielectric and a first gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 80% or more, and an n-channel MIS transistor formed on a p-type well on the substrate, having a second gate dielectric and a second gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 60% or less.
    Type: Application
    Filed: September 10, 2008
    Publication date: March 19, 2009
    Inventors: Masato Koyama, Reika Ichihara, Yoshinori Tsuchiya, Yuuichi Kamimuta, Akira Nishiyama
  • Publication number: 20090075464
    Abstract: A semiconductor device includes a substrate, a p-channel MIS transistor formed on an n-type well on the substrate, having a first gate dielectric and a first gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 80% or more, and an n-channel MIS transistor formed on a p-type well on the substrate, having a second gate dielectric and a second gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 60% or less.
    Type: Application
    Filed: September 10, 2008
    Publication date: March 19, 2009
    Inventors: Masato Koyama, Reika Ichihara, Yoshinori Tsuchiya, Yuuichi Kamimuta, Akira Nishiyama
  • Patent number: 7498643
    Abstract: It is possible to prevent the deterioration of device characteristic as much as possible. A semiconductor device includes: a semiconductor substrate; a gate insulating film provided above the semiconductor substrate and containing a metal, oxygen and an additive element; a gate electrode provided above the gate insulating film; and source/drain regions provided in the semiconductor substrate on both sides of the gate electrode. The additive element is at least one element selected from elements of Group 5, 6, 15, and 16 at a concentration of 0.003 atomic % or more but 3 atomic % or less.
    Type: Grant
    Filed: March 13, 2006
    Date of Patent: March 3, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuuichi Kamimuta, Akira Nishiyama, Yasushi Nakasaki, Tsunehiro Ino, Masato Koyama
  • Publication number: 20080317440
    Abstract: A video receiving apparatus having an input terminal to receive pixel-based video data transmitted with pixel clock synchronized with the video data is provided. The video receiving apparatus may include a separation unit, an information acquisition unit, and a determination unit. The separation unit may be configured to separate auxiliary data added to the video data from the video data obtained at the input terminal. The information acquisition unit may be configured to acquire information on the number of horizontal pixels and the number of vertical pixels for the input video data from the auxiliary data separated at the separation unit. The determination unit may be configured to determine a type of the input video data based on the information on the number of horizontal pixels and the number of vertical pixels that is obtained at the information acquisition unit.
    Type: Application
    Filed: August 3, 2007
    Publication date: December 25, 2008
    Applicant: Sony Corporation
    Inventors: Takuro Shoji, Akira Nishiyama
  • Publication number: 20080258230
    Abstract: There is disclosed a semiconductor device comprising a P-channel MIS transistor which includes an N-type semiconductor layer, a first gate insulating layer formed on the N-type semiconductor layer and containing a carbon compound of a metal, and an N-channel MIS transistor which includes a P-type semiconductor layer, a second gate insulating layer formed on the P-type semiconductor layer, and a second gate electrode formed on the second gate insulating layer.
    Type: Application
    Filed: June 5, 2008
    Publication date: October 23, 2008
    Inventors: Masato KOYAMA, Akira Nishiyama, Yoshinori Tsuchiya, Reika Ichihara
  • Publication number: 20080258264
    Abstract: Disclosed is a semiconductor device comprising a Ge semiconductor area, and an insulating film area, formed in direct contact with the Ge semiconductor area, containing metal, germanium, and oxygen.
    Type: Application
    Filed: June 12, 2008
    Publication date: October 23, 2008
    Inventors: Yoshiki Kamata, Akira Nishiyama, Tsunehiro Ino, Yuuichi Kamimuta, Masahiro Koike
  • Publication number: 20080254581
    Abstract: There is disclosed a semiconductor device comprising a P-channel MIS transistor which includes an N-type semiconductor layer, a first gate insulating layer formed on the N-type semiconductor layer and containing a carbon compound of a metal, and an N-channel MIS transistor which includes a P-type semiconductor layer, a second gate insulating layer formed on the P-type semiconductor layer, and a second gate electrode formed on the second gate insulating layer.
    Type: Application
    Filed: June 5, 2008
    Publication date: October 16, 2008
    Inventors: Masato KOYAMA, Akira Nishiyama, Yoshinori Tsuchiya, Reika Ichihara
  • Patent number: 7435655
    Abstract: A semiconductor device includes a silicon substrate, a channel region formed in a surface of the silicon substrate, a gate insulating film formed on the channel region, a gate electrode formed on the gate insulating film, first gate side walls formed on the gate insulating film to sandwich the gate electrode in a gate length direction, second gate side walls which sandwich the gate electrode and the first gate side wall, first diffused layers formed on the surface of the silicon substrate to sandwich the channel region, second diffused layers which sandwich the channel region and the first diffused layer and have a larger depth than that of the first diffused layer, and low resistance layers which are formed between the first diffused layer and the second gate side wall and contain nitride, boride or carbide of Ti, Zr, Hf or Ta.
    Type: Grant
    Filed: April 17, 2007
    Date of Patent: October 14, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masato Koyama, Akira Nishiyama, Yuuichi Kamimuta
  • Patent number: 7432570
    Abstract: A semiconductor device includes a substrate, a p-channel MIS transistor formed on an n-type well on the substrate, having a first gate dielectric and a first gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 80% or more, and an n-channel MIS transistor formed on a p-type well on the substrate, having a second gate dielectric and a second gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 60% or less.
    Type: Grant
    Filed: December 7, 2006
    Date of Patent: October 7, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masato Koyama, Reika Ichihara, Yoshinori Tsuchiya, Yuuichi Kamimuta, Akira Nishiyama