Patents by Inventor Akira Yoshioka
Akira Yoshioka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20130062671Abstract: A nitride semiconductor device includes a first semiconductor layer, a second semiconductor layer, a conductive substrate, a first electrode, a second electrode, and a control electrode. The second semiconductor layer is directly bonded to the first semiconductor layer. The conductive substrate is provided on and electrically connected to the first semiconductor layer. The first electrode and the second electrode are provided on and electrically connected to a surface of the second semiconductor layer on a side opposite to the first semiconductor layer. The control electrode is provided on the surface of the second semiconductor layer between the first electrode and the second electrode. The first electrode is electrically connected to a drain electrode of a MOSFET formed of Si. The control electrode is electrically connected to a source electrode of the MOSFET. The conductive substrate is electrically connected to a gate electrode of the MOSFET.Type: ApplicationFiled: March 14, 2012Publication date: March 14, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Wataru SAITO, Yasunobu Saito, Hidetoshi Fujimoto, Akira Yoshioka, Testsuya Ohno
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Patent number: 8334132Abstract: According to the present invention, by using 4-halogeno-3-hydroxybutanamide as a substrate in quaternary amination reaction with trialkylamine which is an important step in betaine (such as carnitine) preparation processes, it becomes possible to reduce the production of crotonic acid derivatives (the major by-product) greatly compared to conventional processes. Consequently, it becomes possible to prepare a betaine, such as carnitine, at a high yield.Type: GrantFiled: November 9, 2007Date of Patent: December 18, 2012Assignee: Mitsubishi Rayon Co., Ltd.Inventors: Kosuke Oishi, Eiji Sato, Hiroyuki Mori, Akira Yoshioka
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Publication number: 20120241751Abstract: According to one embodiment, a nitride semiconductor device includes a first semiconductor layer, a second semiconductor layer, a first electrode, a second electrode, a third electrode, a first insulating film and a second insulating film. The first semiconductor layer includes a nitride semiconductor. The second semiconductor layer is provided on the first layer, includes a nitride semiconductor, and includes a hole. The first electrode is provided in the hole. The second electrode is provided on the second layer. The third electrode is provided on the second layer so that the first electrode is disposed between the third and second electrodes. The first insulating film is provided between the first electrode and an inner wall of the hole and between the first and second electrodes, and is provided spaced from the third electrode. The second insulating film is provided in contact with the second layer between the first and third electrodes.Type: ApplicationFiled: September 21, 2011Publication date: September 27, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Akira YOSHIOKA, Yasunobu Saito, Hidetoshi Fujimoto, Tetsuya Ohno, Wataru Saito, Toru Sugiyama
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Publication number: 20120187413Abstract: According to one embodiment, a nitride semiconductor device includes a first semiconductor, a second semiconductor layer, a third semiconductor layer, a fourth semiconductor layer, a first electrode, a second electrode and a third electrode. The first, second and fourth semiconductor layers include a nitride semiconductor. The second semiconductor layer is provided on the first semiconductor layer, has a band gap not less than that of the first semiconductor layer. The third semiconductor layer is provided on the second semiconductor layer. The third semiconductor layer is GaN. The fourth semiconductor layer is provided on the third semiconductor layer to have an interspace on a part of the third semiconductor layer, has a band gap not less than that of the second semiconductor layer. The first electrode is provided on a portion of the third semiconductor layer. The fourth semiconductor layer is not provided on the portion.Type: ApplicationFiled: September 21, 2011Publication date: July 26, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Yasunobu SAITO, Hidetoshi FUJIMOTO, Tetsuya OHNO, Akira YOSHIOKA, Wataru SAITO
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Patent number: 8227834Abstract: A semiconductor device includes: a first semiconductor layer including AlXGa1-XN (0?X?1); a second semiconductor layer provided on the first semiconductor layer, including AlYGa1-YN (0?Y?1, X<Y), and having a larger bandgap than the first semiconductor layer; a source electrode provided on the second semiconductor layer; a drain electrode provided on the second semiconductor layer; and a gate electrode provided on the second semiconductor layer between the source electrode and the drain electrode. A region of the second semiconductor layer below the gate electrode at a depth short of the first semiconductor layer is doped with atoms to be negatively charged in the second semiconductor layer.Type: GrantFiled: August 26, 2011Date of Patent: July 24, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Yasunobu Saito, Wataru Saito, Yorito Kakiuchi, Tomohiro Nitta, Akira Yoshioka, Tetsuya Ohno, Hidetoshi Fujimoto, Takao Noda
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Publication number: 20110309413Abstract: A semiconductor device includes: a first semiconductor layer including AlXGa1-XN (0?X?1); a second semiconductor layer provided on the first semiconductor layer, including AlYGa1-YN (0?Y?1, X<Y), and having a larger bandgap than the first semiconductor layer; a source electrode provided on the second semiconductor layer; a drain electrode provided on the second semiconductor layer; and a gate electrode provided on the second semiconductor layer between the source electrode and the drain electrode. A region of the second semiconductor layer below the gate electrode at a depth short of the first semiconductor layer is doped with atoms to be negatively charged in the second semiconductor layer.Type: ApplicationFiled: August 26, 2011Publication date: December 22, 2011Applicant: Kabushiki Kaisha ToshibaInventors: Yasunobu SAITO, Wataru SAITO, Yorito KAKIUCHI, Tomohiro NITTA, Akira YOSHIOKA, Totsuya OHNO, Hidetoshi FUJIMOTO, Takao NODA
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Publication number: 20110272708Abstract: According to one embodiment, a nitride semiconductor device includes a first, a second and a third semiconductor layer, a first and a second main electrode and a control electrode. The first layer made of a nitride semiconductor of a first conductivity type is provided on a substrate. The second layer made of a nitride semiconductor of a second conductivity type is provided on the first layer. The third layer made of a nitride semiconductor is provided on the second layer. The first electrode is electrically connected with the second layer. The second electrode is provided at a distance from the first electrode and electrically connected with the second layer. The control electrode is provided within a first trench via an insulating film. The first trench is disposed between the first and the second main electrodes, penetrates the third and the second layers, and reaches the first layer.Type: ApplicationFiled: March 21, 2011Publication date: November 10, 2011Applicant: Kabushiki Kaisha ToshibaInventors: Akira Yoshioka, Wataru Saito, Yasunobu Saito, Hidetoshi Fujimoto, Tetsuya Ohno
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Patent number: 8030660Abstract: A semiconductor device includes: a first semiconductor layer including AlXGa1-XN (0?X?1); a second semiconductor layer provided on the first semiconductor layer, including AlYGa1-YN (0?Y?1, X<Y), and having a larger bandgap than the first semiconductor layer; a source electrode provided on the second semiconductor layer; a drain electrode provided on the second semiconductor layer; and a gate electrode provided on the second semiconductor layer between the source electrode and the drain electrode. A region of the second semiconductor layer below the gate electrode at a depth short of the first semiconductor layer is doped with atoms to be negatively charged in the second semiconductor layer.Type: GrantFiled: February 13, 2009Date of Patent: October 4, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Yasunobu Saito, Wataru Saito, Yorito Kakiuchi, Tomohiro Nitta, Akira Yoshioka, Tetsuya Ohno, Hidetoshi Fujimoto, Takao Noda
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Publication number: 20110204380Abstract: According to an embodiment, in a nitride-based FET, a protrusion portion is formed at an upper portion of an undoped GaN layer by second recess etching. On the protrusion portion, an undoped AlGaN layer is provided which is formed by first recess etching the upper portion of the undoped AlGaN layer. A multilayer portion is composed of the protrusion portion of the undoped GaN layer, the undoped AlGaN layer, and an insulating film. A trench portion is formed by recess etching the insulating film, the undoped AlGaN layer and a surface of the undoped GaN layer. A gate insulating film is formed on the multilayer portion and the trench portion. A gate electrode is formed on the gate insulating film so as to cover the trench portion. A film thickness of the insulting film is set larger than that of the gate insulating film.Type: ApplicationFiled: February 22, 2011Publication date: August 25, 2011Applicant: Kabushiki Kaisha ToshibaInventors: Akira YOSHIOKA, Yasunobu Saito, Hidetoshi Fujimoto, Tetsuya Ohno, Takao Noda
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Patent number: 7728354Abstract: A semiconductor device includes: a first semiconductor layer of p-type AlxGa1-xN (0?x?1); a second semiconductor layer of n-type AlyGa1-yN (0<y<1, x<y) formed on the first semiconductor layer; a control electrode formed on the second semiconductor layer; a first main electrode connected to the first semiconductor layer and the second semiconductor layer; and a second main electrode connected to the second semiconductor layer. An interface between the first semiconductor layer and the second semiconductor layer has a surface orientation of (1-101) or (11-20).Type: GrantFiled: November 14, 2007Date of Patent: June 1, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Wataru Saito, Akira Yoshioka, Hidetoshi Fujimoto, Takao Noda, Yasunobu Saito, Tomohiro Nitta, Yorito Kakiuchi
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Publication number: 20090325246Abstract: According to the present invention, by using 4-halogeno-3-hydroxybutanamide as a substrate in quaternary amination reaction with trialkylamine which is an important step in betaine (such as carnitine) preparation processes, it becomes possible to reduce the production of crotonic acid derivatives (the major by-product) greatly compared to conventional processes. Consequently, it becomes possible to prepare a betaine, such as carnitine, at a high yield. The present invention also relates to a process for preparing a betaine represented by formula (1) below, comprising a step of quaternary aminating an amide represented by formula (2) below: wherein A1, A2 and A3 individually represent a C1-C20 hydrocarbon group which may have a substituent(s); and X1 is a halogen atom.Type: ApplicationFiled: November 9, 2007Publication date: December 31, 2009Applicant: MITSUBISHI RAYON CO., LTD.Inventors: Kosuke Oishi, Eiji Sato, Hiroyuki Mori, Akira Yoshioka
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Publication number: 20090200576Abstract: A semiconductor device includes: a first semiconductor layer including AlXGa1-XN (0?X?1); a second semiconductor layer provided on the first semiconductor layer, including AlYGa1-YN (0?Y?1, X<Y), and having a larger bandgap than the first semiconductor layer; a source electrode provided on the second semiconductor layer; a drain electrode provided on the second semiconductor layer; and a gate electrode provided on the second semiconductor layer between the source electrode and the drain electrode. A region of the second semiconductor layer below the gate electrode at a depth short of the first semiconductor layer is doped with atoms to be negatively charged in the second semiconductor layer.Type: ApplicationFiled: February 13, 2009Publication date: August 13, 2009Applicant: Kabushiki Kaisha ToshibaInventors: Yasunobu Saito, Wataru Saito, Yorito Kakiuchi, Tomohiro Nitta, Akira Yoshioka, Tetsuya Ohno, Hidetoshi Fujimoto, Takao Noda
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Patent number: 7538366Abstract: A nitride semiconductor device includes: a conductive substrate; a first semiconductor layer provided on the substrate; a second semiconductor layer provided on the first semiconductor layer; a third semiconductor layer on the second semiconductor layer; a first main electrode connected to the third semiconductor layer; a second main electrode connected to the third semiconductor layer; and a control electrode provided on the third semiconductor layer. The first semiconductor layer is made of AlXGa1?XN (0?X?1) of a first conductivity type. The second semiconductor layer is made of a first nitride semiconductor. The third semiconductor layer is made of a second nitride semiconductor which is undoped or of n-type and has a wider bandgap than the first nitride semiconductor.Type: GrantFiled: April 25, 2007Date of Patent: May 26, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Wataru Saito, Akira Yoshioka, Hidetoshi Fujimoto, Yasunobu Saito, Takao Noda, Tomohiro Nitta, Yorito Kakiuchi
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Publication number: 20090092958Abstract: A method of inactivating a blood coagulation factor is described. The method comprises a step of contacting a sample containing at least one of factors V and VIII with a compound having an iminodiacetate group, whereby at least one of factors V and VIII in the sample is changed into an inactivated form.Type: ApplicationFiled: September 24, 2008Publication date: April 9, 2009Applicant: Sysmex CorporationInventors: Masahiro OKUDA, Yoshihito Yamamoto, Akira Yoshioka, Midori Shima, Masahiro Takeyama
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Patent number: 7498618Abstract: A nitride semiconductor device comprises: a substrate body including a conductive substrate portion and a high resistance portion; a first semiconductor layer of a nitride semiconductor provided on the substrate body; a second semiconductor layer provided on the first semiconductor layer; a first main electrode provided on the second semiconductor layer; a second main electrode provided on the second semiconductor layer; and a control electrode provided on the second semiconductor layer between the first main electrode and the second main electrode. The second semiconductor layer is made of a nondoped or n-type nitride semiconductor having a wider bandgap than the first semiconductor layer. The first main electrode is provided above the conductive portion and the second main electrode is provided above the high resistance portion.Type: GrantFiled: August 22, 2006Date of Patent: March 3, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Wataru Saito, Masaaki Onomura, Akira Tanaka, Koichi Tachibana, Masahiko Kuraguchi, Takao Noda, Tomohiro Nitta, Akira Yoshioka
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Publication number: 20080116486Abstract: A semiconductor device includes: a first semiconductor layer of p-type AlxGa1-xN (0?x?1); a second semiconductor layer of n-type AlyGa1-yN (0<y<1, x<y) formed on the first semiconductor layer; a control electrode formed on the second semiconductor layer; a first main electrode connected to the first semiconductor layer and the second semiconductor layer; and a second main electrode connected to the second semiconductor layer. An interface between the first semiconductor layer and the second semiconductor layer has a surface orientation of (1-101) or (11-20).Type: ApplicationFiled: November 14, 2007Publication date: May 22, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Wataru SAITO, Akira Yoshioka, Hidetoshi Fujimoto, Takao Noda, Yasunobu Saito, Tomohiro Nitta, Yorito Kakiuchi
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Publication number: 20070254431Abstract: A nitride semiconductor device includes: a conductive substrate; a first semiconductor layer provided on the substrate; a second semiconductor layer provided on the first semiconductor layer; a third semiconductor layer on the second semiconductor layer; a first main electrode connected to the third semiconductor layer; a second main electrode connected to the third semiconductor layer; and a control electrode provided on the third semiconductor layer. The first semiconductor layer is made of AlXGa1?XN (0?X?1) of a first conductivity type. The second semiconductor layer is made of a first nitride semiconductor. The third semiconductor layer is made of a second nitride semiconductor which is undoped or of n-type and has a wider bandgap than the first nitride semiconductor.Type: ApplicationFiled: April 25, 2007Publication date: November 1, 2007Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Wataru Saito, Akira Yoshioka, Hidetoshi Fujimoto, Yasunobu Saito, Takao Noda, Tomohiro Nitta, Yorito Kakiuchi
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Publication number: 20070051977Abstract: A nitride semiconductor device comprises: a substrate body including a conductive substrate portion and a high resistance portion; a first semiconductor layer of a nitride semiconductor provided on the substrate body; a second semiconductor layer provided on the first semiconductor layer; a first main electrode provided on the second semiconductor layer; a second main electrode provided on the second semiconductor layer; and a control electrode provided on the second semiconductor layer between the first main electrode and the second main electrode. The second semiconductor layer is made of a nondoped or n-type nitride semiconductor having a wider bandgap than the first semiconductor layer. The first main electrode is provided above the conductive portion and the second main electrode is provided above the high resistance portion.Type: ApplicationFiled: August 22, 2006Publication date: March 8, 2007Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Wataru Saito, Masaaki Onomura, Akira Tanaka, Koichi Tachibana, Masahiko Kuraguchi, Takao Noda, Tomohiro Nitta, Akira Yoshioka
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Patent number: 7157749Abstract: A bipolar transistor is provided which includes a GaAs substrate, an n-type collector region formed on the GaAs substrate, a p-type base region formed on the n-type collector region and having a p-type base layer of SiGe having a composition lattice-matched with the GaAs substrate, and an n-type emitter region formed on the p-type base region. A bipolar transistor may include a GaAs substrate, a collector region of a first conductivity type formed on the GaAs substrate and including a collector contact layer of the first conductivity type SiGe, which has a composition lattice-matched with the GaAs substrate, a base region of a second conductivity type formed on the collector region of the first conductivity type, and an emitter region of the first conductivity type formed on the base region of the second conductivity type.Type: GrantFiled: February 9, 2005Date of Patent: January 2, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Hidetoshi Fujimoto, Tetsuro Nozu, Yoshitomo Sagae, Akira Yoshioka
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Publication number: 20060261372Abstract: A heterojunction bipolar transistor in which an emitter area has an undoped layer including InGaAs, InAlAs or Inx (GayAl1-y)1-x As and a first conductivity-type partial emitter formed on a part of a surface of the undoped layer and including a material matched to the undoped layer; a first conductivity-type impurity concentration in the undoped layer is lower than the first conductivity-type impurity concentration of the partial emitter or the first conductivity-type impurity concentration in the undoped layer is 0; and at least sides of the partial emitter are covered by a metal protective layer while a part of the metal protective layer forms a Schottky junction with the undoped layer. The metal protective layer is formed by vacuum evaporation.Type: ApplicationFiled: April 5, 2006Publication date: November 23, 2006Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Akira Yoshioka