Abstract: A method and a system for framing variable-length packets in a data communications system are disclosed. The successive variable-length packets carrying users' data, are formed in a stream of chained packets comprising a header. Two CRC's are computed. One over the data and another one over the header however, including also the data CRC of the immediate previous packet, thus chaining successive packets in a steam of such packets. The invention also assumes that encryption is performed independently over header and corresponding CRC's and, on the other hand, over the data of current packet. The invention allows to better adapt the transportation of multi-media users' data in packets of variable-lengths while securing transport by chaining successive packets, thus preventing that accidental or malicious deletion and insertion of packets occur and remain undetected.

Abstract: Automatic speed adaptation system in a Local Area Network (LAN) between a hub (10) including a hub adapter (20, 24, 28) and at least a workstation (12, 14, 16) including a workstation adapter (18, 22, 26) for exchanging data over a link connected between the hub adapter and the workstation adapter at a rate based on a frequency which is inversely proportional to the length of the link. Each adapter comprises a clock generator for generating a clock having a frequency between F1 and F2 and processing means for transmitting at least a check frame from the hub adapter to the workstation adapter at a rate based on a frequency VCLK generated by the clock generator under the control of the processing means and selected as being the frequency corresponding to the length of the link, and for transmitting an acknowledge frame from the workstation adapter to the hub adapter thereby ascertaining that the selected frequency is the right frequency resulting in the best quality of transmission.

Abstract: The invention relates to a Universal Serial Bus (USB) with two wireless communication hubs (USB hubs). One of these hubs is connected to a first host computer, and both USB hubs are connected to a plurality of I/O devices. Each USB hub includes a wireless adapter and an antenna connected to the wireless adapter. The wireless adapter of each USB hub comprises a transmitting/receiving unit for transmitting data via the antenna to the wireless adapter of the other USB hub or receiving data via the antenna from the wireless adapter of the other USB hub. The wireless adapter also comprises a wireless dual port, which is automatically configured upstream or downstream when the first host computer is connected to one of the USB hubs.

Abstract: A security system for preventing unauthorized use of a computer device. An extractable security piece includes an extractable main private key and a main PC public key. A PC security area which is a non-extractable part of the computer device includes a PC private key and an extractable main public key, which, together with the keys of the extractable security piece, constitute a Public Key Infrastructure. The extractable security piece and the PC security area include processing means for mutual authentication of the extractable security piece and the PC security area after the extractable security piece, which had been previously removed, has been reinserted in the computer device, thereby enabling the authorized user to access data stored in the computer device.

Abstract: Process for controlling frames transporting data from a transmitting Terminal (DTE 1) to at least a receiving Terminal (DTE 2) through a plurality of consecutive nodes including a start access node (NODE 1) connected to said transmitting Terminal and at least an end access node (NODE 6) connected to said receiving Terminal and intermediary nodes (NODE 2 to NODE 5), with each data frame comprising one or several protocol layers respectively associated with one or several communication protocols of controlling the frame flow at each node; such a process consisting in adding to each data frame a Data Manipulation Layer (DML) defining the parameters necessary for managing the manipulation (compression and/or encryption) of each field of the data frame located after the DML, and adding to each data frame a Control message for transporting a control protocol defining new parameters to be used by some ones nodes for managing the communication flow through the consecutive nodes.

Abstract: Hardware device for parallel processing a determined instruction of a set of instructions having a same format defining operand fields and other data fields, the execution of this determined instruction being represented as an algorithm comprising a plurality of processes, the processing of which depending on decisions. Such a device comprises means (22-30) for activating the processing of one or several processes (32-38) determined by the operand fields of the instruction, decision macroblocks (12-20) each being associated with a specific instruction of the set of instructions, only one decision marcoblock being selected by the determined instruction in order to determine which are the process(es) to be activated for executing the determined instruction.

Abstract: A switchover system and method is described. The invention preferably operates in a data packet switching system for transmitting through a switching arrangement data packets that comprise at least a data packet identifier. The switching arrangement comprises at least an active switch card associated to a backup switch card. And the active switch card and the backup switch card receive simultaneously at least a data packet and transmit it to a network adapter device. The switchover system comprises active and backup means for respectively storing at an active and backup data packet address the transmitted at least data packet. It also comprises switchover detecting means coupled to the active and backup storing means for detecting a switchover event, and control means coupled to the active and backup storing means and to the switchover detecting means for setting the backup storing means when a switchover event is detected.

Abstract: The present invention is directed to a hardware device for parallel processing a determined instruction of a set of programmable instructions having a same format with an operand field defining the execution steps of the instruction corresponding to the execution of micro-instructions, comprising decision blocks (12—20) being each associated with a specific instruction of the set of programmable instructions, only one decision block being selected by the determined instruction in order to define which are the specific micro-instructions to be processed for executing the determined instruction, activation blocks (22-30) respectively associated with the decision blocks for running one or several specific micro-instructions, only the activation block associated with said selected decision block being activated to run the specific micro-instructions, and a micro-instruction selection block (46) connected to each activation block for selecting the specific micro-instructions to be executed.

Abstract: A data transmission system comprising a packet switch module interconnecting LAN adapters, a plurality of input and output ports connected to the LAN adapters such that each pair of input and output ports defines a crosspoint within the switch module, and a memory block located at each crosspoint of the switch module for storing at least one data packet. At each clock time, a scheduler causes a data packet stored in a memory block, among all memory blocks corresponding to a given output port, to be transferred to that output port.

Abstract: A system and method to print graphic documents in booklet format. The system allows the user to have a booklet print option available as a print option of a graphic editor. The system comprises means for generating a plurality of graphic pages, and means for ordering the pages into logical sequences, each logical sequence being associated to a predefined layout. The ordering means further comprise means for ordering the plurality of graphic pages into a booklet logical sequence, where the booklet logical sequence is associated with a booklet layout. The pages are ordered according to the value of a remainder ‘R’ according to ‘R=Nmodulo(4)’, wherein ‘N’ is the number of graphic pages to be ordered.

Abstract: Data transmission system comprising a plurality of Local Area Networks (LANs) (10-1 to 10-4) interconnected by a hub (12) including the same plurality of LAN adapters (16-1 to 16-4) respectively connected to the LANs and a packet switch (14) comprising at least a packet switch module interconnecting all LAN adapters wherein a packet transmitted by any adapter to the packet switch includes a header containing at least the address of the adapter to which the packet is forwarded.

Abstract: A file manager (and method) provided for locating a file identified by a path referring to a logical unit and an identifier, includes a table associating the file with a priority list of physical units. The file manager can be incorporated into the controller of peripheral devices in a computer system or an operating system of the computer system.

Abstract: A device for parallel processing of subtrees within a binary tree for searching for the tree leaf matching a search key. The search is performed at each node by applying a recursive function associated with each node and whose parameters depend on the node for determining which branch, left or right, is to be taken in accordance with the search key. The device includes subtree register blocks for storing the recursive functions, processors for processing the recursive functions, a control unit that assigns one processor to the processing of the recursive functions contained in a block that sent the request to the control unit, and means for selecting subtrees included in the sequence of branches between the root and the leaf defined in accordance with the search key in response to the processing of blocks.

Abstract: An apparatus for keeping several versions of a file includes a memory and an overwriting unit coupled to the memory. An initial version of the file is stored in a first area of the memory, and a current version is stored in a second area of the memory, the current version resulting from a modification of the initial version. The overwriting unit substitutes the current version for the initial version in response to a validation signal. The validation signal is produced after the current version has been permanently stored.

Abstract: Method and system for assigning labels in a data transmission network in which flows of data, composed of packets, are transmitted from a source node to a destination node through a plurality of switching nodes. The network is further characterized in that a label, identifying each flow of data, is added to each packet of the flow of data before the packet is transmitted from a transmitting node to an adjacent receiving node in the network. This so-called identification label is recognized by the receiving node as the identification of the flow of data to be transmitted. Each node in the network assigns an identification label to the packets when a new flow of data is received by the node. Both the transmitting and receiving nodes in the network generate an identical label for a given flow of data. Thus, the overhead associated with the sending of assigned labels from assigning nodes to corresponding upstream or downstream transmitting or receiving nodes in the network is avoided.

Abstract: Data transmission system comprising a plurality of Local Area Networks (LANs) (10-1 to 10-4) interconnected by a hub (12) including the same plurality of LAN adapters (16-1 to 16-4) respectively connected to the LANs and a packet switch (14) interconnecting all LAN adapters wherein a packet transmitted by any adapter to the packet switch includes a header containing at least the address of the adapter to which the packet is forwarded. The system comprises a memory block located at each cross point of the switch module for storing any data packet which is received from the input port corresponding to the cross point and which is to be forwarded to the output port corresponding to this cross point, and a scheduler associated with each output port for selecting at each clock time a memory block among all memory blocks corresponding to the output port and causing the memory block to forward the stored data packet to the output port when predetermined criteria are met.

Abstract: Data transmission system comprising a plurality of Local Area Networks (LANs) (10-1 to 10-4) interconnected by a hub (12) including the same plurality of LAN adapters (16-1 to 16-4) respectively connected to the LANs and a packet switch (14) comprising at least a packet switch module interconnecting all LAN adapters wherein a packet transmitted by any adapter to the packet switch includes a header containing at least the address of the adapter to which the packet is forwarded. At each cross point is located a memory block for storing any data packet received from the input port corresponding to the cross point and which is to be forwarded to the output port corresponding to the cross point.

Abstract: Data transmission system comprising a plurality of Local Area Networks (LANs) (10-1 to 10-4) interconnected by a hub (12) including the same plurality of LAN adapters (16-1 to 16-4) respectively connected to the LANs and a packet switch (14) interconnecting all LAN adapters wherein a packet transmitted by any adapter to the packet switch includes a header containing at least the address of the adapter to which the packet is forwarded. At each cross point is located a memory block for storing any data packet received from the input port corresponding to the cross point and which is to be forwarded to the output port corresponding to the cross point.

Abstract: The present invention describes a switching module for use either in port or speed expansion mode. The switching module is preferably used in a data transmission system consisting of a number of Local Area Networks LANs interconnected by a hub which includes a number of LAN adapters respectively connected to said LANs.

Abstract: The ATM bus (100) is composed of a clock signal, CLK, a synchronization signal, -SYNC, a data bus, S(0-31), and an adapter identification bus, SID(0-3). It is a synchronous bus running at any clock rates. The clock signal is generated by the backplane (20) and transmitted to each adapter (10-1, . . . 10-N). During each clock cycle, the data bus has three serialized operation modes (or cycles) defined in this order: a bus_req cycle of 1 clock period, a bus_ack cycle of 1 clock period and an ATM cell_xfr cycle of 14 clock periods. The free-running synchronization signal is generated on the backplane (20) and transmitted to each adapter (10-1, . . . , 10-N). The activation of the synchronization signal of one bit of the data bus, S(0-31), starts the bus_req cycle. In each case, the remaining data bus signals are left in high impedance state. To increase the bus performance, the synchronization signal is held active until an adapter activates its bus_request signal.