Abstract: Method of reinitializing dictionaries in a data transmission system using data compression having a transmit device and a receive device, and in which strings of characters have to be transmitted in a compressed form, the transmit device having a transmit dictionary storing codewords associated with the strings of characters which are transmitted instead of the strings of characters, the receive device having a receive dictionary storing codewords associated with the strings of characters, and both dictionaries being updated each time a new string of characters has to be transmitted so that the contents of the dictionaries remain identical.

Abstract: A package for a communication equipment fitted with mechanical locking mechanism and electrical and communication connectivity for allowing power supply distribution as well as communication at least at four distinctive faces (UP, DOWN, RIGHT, LEFT). Each communicating face is fitted with optical transmission and reception devices allowing digital communication between adjacent apparatuses. Each package comprises two faces having each one protrusion at one surface that is intended to enter into a groove machined at a corresponding surface of the next adjacent package in said structure. Each protrusion comprises a locking mechanism for power supply that comprises a camming hook (2200) having a distal end which forceably engages a locking aperture (2210) when pivoted. The hook is pivotally coupled to an axel (2101) extending respectfully through an elongated aperture (2301) formed at one end of a lever arm (2300), and an elongated aperture (2302) of the hook.

Abstract: To establish the communication between two devices connected through an asynchronous data link, an adapter for automatically identifies configuration parameters. The configuration parameters may be the transmission speed, the data bits length (seven or eight), the parity (odd or even) if existing and the number of stop bits (one or two). Thus, there are six combinations of the four parameters. Each one of the configuration is detected by an adapter which is independent from the others. It comprises a control circuit (170) receiving deserialized data bits signal (RXD) from a connector (120), a clock generator (160) for generating clock signals and varying the clock frequency so as to adapt to asynchronous data transmission speed, a timer (220) for synchronizing the number of data bytes so as to adapt to the data bit length and counters for counting the number of times a predetermined configuration matches. A parity checker may be also implemented in case a parity bit is used in the data transmission.

Abstract: A process for operating a communication equipment having a set of mechanically connected apparatuses being vertically and horizontally packed. Each apparatus comprises telecommunication functions such as echo cancellation, data compression or ISDN gateway, as well as vertical and horizontal mechanical and communication connections respectively allowing the vertical and horizontal exchanges of frames with neighboring apparatuses. The communication is based on a frame comprising n bytes routing header with n being an integer and an Asynchronous Transfer Mode (ATM) cell.

Abstract: The invention relates to multilevel interrupt device (10) using a common microprocessor interrupt signal (101) to process interrupt signals (INT1, . . . , INTN) received from N peripheral chips. This device (10) is connected to a microprocessor (100) and N peripheral chips (200,210,230) through data/address busses (108,110) and it is also connected to a memory (150) by an additional bus (112). An interrupt operation starts when any one of the peripheral chips activates an interrupt signal through OR gate (220) detected by the microprocessor. The invention avoids to involve the microprocessor in the determination of the interrupt requester except for the generation of a common start.sub.-- address decoded by logic (180) for starting interrupt operations and a common end.sub.-- address decoded by logic (190) for ending it. Owing to the start.sub.

Abstract: An adapter for transferring blocks of data of a variable size to at least one destination adapter, each of the adapters being plugged in a respective slot and connected to a main system bus which is controlled by a central backplane card. In each adapter, the transmission of one block of data is provided, in part, by a device, operative in response to the detection of an ACK acknowledge word giving access to the bus, for generating a signalling word to be transmitted to a particular destination adapter which will actually receive the transmitted data; the signalling word comprising information characterizing the type of command which the transmitting adapter sends as a request to the backplane card, the address of the particular adapter which will receive the transmitted data, the size of the block of the transmitted data and the address of the transmitting adapter. The adapter is best suited for use in multimedia systems where variable size data blocks are required to transmit data, voice, video, etc.

Abstract: An apparatus and a method to synchronize the clock signal of a first (or slave) data terminal equipment A (240-1) to a second (or master) data terminal equipment B (240-2) connected to a communication network (10) through respectively a first network node (51) and a second network node (52). The communication network has a reference clock that it transmits to the second network node which compares it with the clock signal that it receives from the second data terminal equipment. The phase difference is then detected and converted into a frame which may be an ATM cell or any other frames so that it can be switched with the data frames sent by the second DTE and transmitted to the first DTE through the communication network. The frame containing the phase difference has a specific header so that it can be distinguished from the other transmitted data frames. The first network node receives the frames, detects the phase difference frame and decodes it before it is sent to a digital to analog converter.

Abstract: The invention provides an impedance adapter that automaticaly switches to impedances that match network transmit/receive lines impedances (105,106) by a controlled switching of various impedances mounted serially/parallely with connected transmitter/receiver (100,101). For a high speed adapter, a balanced transmitter/receiver is required for limiting crosstalk effect due to the high transmission rate. Transmit/Receive impedance adaptation networks (102-103) are composed of serial/parallel networks of resistors and relay contacts that are switched independently by magnetic coils of an impedance switching circuit (110) and having values conformable to the various network impedances imposed by different national regulations. By using the principle of double deviation voltage technique, a measuring circuit (108) detects upward and downward voltages (VA,VB), VB amplified by 2 to generate an analog signal VS (VS=VA-2VB) to a control logic circuit (109).

Abstract: The invention relates to a method and a system for routing messages or frames through network nodes connected to each other by network links and connected to a plurality of terminals by different input/output ports also called network attachment cards (NAC) in a multi-node communication network. In such a configuration, each terminal equipment stores a network table. The network table is updated in the terminal itself by a network manager which may by the way limit the access of the terminal to some terminals of the network. To route an incoming message or frame from a source terminal (T1) to the destination terminal (T7), a routing algorithm is implemented in each NAC. Each NAC has a different and unique integer address in the node, each node has a different and unique prime number address greater than the number of NACs in the node. Each terminal connected to a node sends frames with a routing identifier (RI). The different RIs are located in the network table.

Abstract: Data compression using a Liv-Zempel algorithm is enhanced by organizing strings of data in a dictionary using a set of related four related fields. The first field contains an index or codeword for the last character of the string currently being processed. The second field contains an index or codeword for a SON string, a string which includes all of the characters of the current string plus one additional character. The third field contains an index or codeword for a BROTHER string which is identical to the current string except that the last characters in the two strings differ. The fourth field contains an index or codeword for a PARENT to the current string. The PARENT includes all of the characters of the current string except the last character. The memory arrangement comprises a tree structure which can be efficiently accessed by a disclosed processor to perform data compression using minimal processing resources.

Abstract: A conversion cache circuit, interfacing RISC busses to CISC peripheral circuits, provides master/slave Write and Read operations in a shared memory (130) and in the internal registers of the processor of said peripheral circuits (210). It enables RISC processor to Write and Read in the internal registers of the 8-bit processor in a salve operation while the 32-bit processor may perform the Write or Read operations to the shared memory through the conversion cache circuit in a master mode. The 32-bit processor may have access directly to the memory through its own direct access memory mechanism.