Abstract: A controller for a shared memory is disclosed. The controller comprises a transaction scanner configured to scan-in a plurality of transactions to access the shared memory and to divide the transactions into beat-level memory access commands. The controller also comprises a command super-arbiter comprising a plurality of command arbiters corresponding to a plurality of shared memory blocks in the shared memory. The command super-arbiter is configured to access a quality of service for each of the transactions, arbitrate the beat-level memory access commands associated with the transactions based on the quality of service for each of the plurality of transactions, and dispatch the beat-level memory access commands to the shared memory blocks based on results of arbitrating the beat-level memory access commands.

Abstract: A controller for a shared memory is disclosed. The controller comprises a transaction scanner configured to scan-in a plurality of transactions to access the shared memory and to divide the transactions into beat-level memory access commands. The controller also comprises a command super-arbiter comprising a plurality of command arbiters corresponding to a plurality of shared memory blocks in the shared memory. The command super-arbiter is configured to access a quality of service for each of the transactions, arbitrate the beat-level memory access commands associated with the transactions based on the quality of service for each of the plurality of transactions, and dispatch the beat-level memory access commands to the shared memory blocks based on results of arbitrating the beat-level memory access commands.

Abstract: A described embodiment of the present invention includes a network having a first, second and third plurality of routers connected to a plurality of endpoints. At least one of the first plurality of routers includes a plurality of interposers having a number of queues. The at least one of the first plurality of routers has a demultiplexer for each interposer configured to receive multiplexed data from the interposer and provide demultiplexed data on to a plurality of second queues corresponding to the first queues of the number of queues. The at least one of the first plurality of routers also includes a number multiplexers, each of the number multiplexers having inputs configured to receive data from the number of queues.

Abstract: Methods and apparatus for inter-process communication are provided. A circuit may have a plurality of clusters, and at least one cluster may have a computation element (CE), a memory operatively coupled with the CE, and an autonomic transport system (ATS) block operatively coupled with the CE and the memory. The ATS block may be configured to perform inter-process communication (IPC) for the at least one cluster. In one embodiment, the ATS block may transfer a message to a different cluster based on a request from the CE. In another embodiment, the ATS block may receive a message by allocating a buffer in the memory and write the message into the buffer. The ATS block may also be configured to manage synchronization and schedule tasks for the CE.

Abstract: A method includes receiving a first request, from a first master core, to access data in one of a plurality of memory banks. It is determined whether an access to the data is stalled by virtue of a second request, from a second master core, to access the data in the one of the plurality of memory banks, the second request currently being serviced. In response to a determination that the access to the requested data is stalled, the first request is serviced by accessing data in one of a plurality of coding banks, each coding bank smaller in size than each memory bank.

Abstract: Technology for providing data to a processing unit is disclosed. A computer processor may be divided into a master processing unit and consumer processing units. The master processing unit at least partially decodes a machine instruction and determines whether data is needed to execute the machine instruction. The master processing unit sends a request to memory for the data. The request may indicate that the data is to be sent from the memory to a consumer processing unit. The data sent by the memory in response to the request may be stored in local read storage that is close to the consumer processing unit for fast access. The master processing unit may also provide the machine instruction to the consumer processing unit. The consumer processing unit may access the data from the local read storage and execute the machine instruction based on the accessed data.

Abstract: A method of operating a cache memory comprises receiving a first read or write command including at least a first address referring to first data and a first rank indicator associated with the first data, and in response to receiving the first read or write command, reading or writing the first data referenced by the first address, and storing the first rank indicator.

Abstract: A distributed and shared memory controller (DSMC) comprises at least one building block. comprising a plurality of switches distributed into a plurality of stages; a plurality of master ports coupled to a first stage of the switches; and a plurality of bank controllers with associated memory banks coupled to a last stage of the switches; wherein each of the switches connects to lower stage switches via internal connections, each of the switches of the first stage connects to at least one of the master ports via master connections and each of the switches of the last stage connects to at least one of the bank controllers via memory connections; wherein each of the switches of the first stage connects to second stage switches of a neighboring building block via outward connections and each of the switches of a second stage connects to first stage switches of the neighboring building block via inward connections.

Abstract: Systems and techniques for advance cache allocation are described. A described technique includes selecting a job from a plurality of jobs; selecting a processor core from a plurality of processor cores to execute the selected job; receiving a message which describes future memory accesses that will be generated by the selected job; generating a memory burst request based on the message; performing the memory burst request to load data from a memory to at least a dedicated portion of a cache, the cache corresponding to the selected processor core; and starting the selected job on the selected processor core. The technique can include performing an action indicated by a send message to write one or more values from another dedicated portion of the cache to the memory.

Abstract: A cache and a method for operating a cache are disclosed. In an embodiment, the cache includes a cache controller, data cache and a delay write through cache (DWTC), wherein the data cache is separate and distinct from the DWTC, wherein cacheable write accesses are split into shareable cacheable write accesses and non-shareable cacheable write accesses, wherein the cacheable shareable write accesses are allocated only to the DWTC, and wherein the non-shareable cacheable write accesses are not allocated to the DWTC.

Abstract: A method includes determining an error vector magnitude for analog signals received by multiple antennas in an array of antennas of a base station, assigning quantization bits to a plurality of analog-to-digital converters (ADCs) of the base station such that some ADCs have different numbers of quantization bits allocated from a fixed total number of available quantization bits of the base station, and applying the analog signals to the ADCs with quantization bits assigned to reduce the error vector magnitude of the analog signals.

Abstract: Systems and techniques for dynamic coding of memory regions are described. A described technique includes monitoring accesses to a group of memory regions, each region including two or more portions of a group of data banks; detecting a high-access memory region based on whether accesses to a region of the group of memory regions exceeds a threshold; generating coding values of a coding region corresponding to the high-access memory region, the high-access memory region including data values distributed across the group of banks; and storing the coding values of the coding region in a coding bank.

Abstract: It is possible to reduce the latency attributable to memory protection in shared memory systems by performing access protection at a central Data Ownership Manager (DOM), rather than at distributed memory management units in the central processing unit (CPU) elements (CEs) responsible for parallel thread processing. In particular, the DOM may monitor read requests communicated over a data plane between the CEs and a memory controller, and perform access protection verification in parallel with the memory controller's generation of the data response. The DOM may be separate and distinct from both the CEs and the memory controller, and therefore may generally be able to make the access determination without interfering with data plane processing/generation of the read requests and data responses exchanged between the memory controller and the CEs.

Abstract: A cache and a method for operating a cache are disclosed. In an embodiment, the cache includes a cache controller, data cache and a delay write through cache (DWTC), wherein the data cache is separate and distinct from the DWTC, wherein cacheable write accesses are split into shareable cacheable write accesses and non-shareable cacheable write accesses, wherein the cacheable shareable write accesses are allocated only to the DWTC, and wherein the non-shareable cacheable write accesses are not allocated to the DWTC.

Abstract: A described embodiment of the present invention includes a network having a first, second an d third plurality of routers connected to a plurality of endpoints. At least one of the first plurality of routers includes a plurality of interposers having a number of queues. The at least one of the first plurality of routers has a demultiplexer for each interposer configured to receive multiplexed data from the interposer and provide demultiplexed data on to a plurality of second queues corresponding to the first queues of the number of queues. The at least one of the first plurality of routers also includes a number multiplexers, each of the number multiplexers having inputs configured to receive data from the number of queues.

Abstract: Methods and apparatus for inter-process communication are provided. A circuit may have a plurality of clusters, and at least one cluster may have a computation element (CE), a memory operatively coupled with the CE, and an autonomic transport system (ATS) block operatively coupled with the CE and the memory. The ATS block may be configured to perform inter-process communication (IPC) for the at least one cluster. In one embodiment, the ATS block may transfer a message to a different cluster based on a request from the CE. In another embodiment, the ATS block may receive a message by allocating a buffer in the memory and write the message into the buffer. The ATS block may also be configured to manage synchronization and schedule tasks for the CE.

Abstract: Disclosed is method for operating an interposer that includes assigning a binary port weight to a plurality of input ports of the interposer. The sum of all of the port weights is less than or equal to a number of traversals available to the interposer in a cycle. A traversal counter is set zero at the beginning of each cycle. The output of the traversal counter is a binary number of m bits. A mask is generated when a bit of the traversal counter transitions from a zero to a one. The mask is generated having the m?k+1 bit of the mask equal to one and all other bits of the mask equal to zero. Data is transmitted from each port when both the binary port weight and the mask have a one in the same bit position.

Abstract: An intelligent code apparatus, method, and computer program are provided for use with memory. In operation, a subset of data stored in a first memory is identified. Such subset of the data stored in the first memory is processed, to generate a code. The code is then stored in a second memory, for use in reconstructing at least a portion of the data.

Abstract: A system includes a plurality of compute modules and a first processor configured to implement a virtualization layer, where the virtualization layer is configured to support real time jobs. The system also includes a hardware support layer coupled between the plurality of compute modules and the virtualization layer, where the hardware support layer is configured to provide an interface between the virtualization layer and the plurality of compute modules.

Abstract: The present disclosure relates to a system and method of managing operation of a cache memory. The system and method assign each nested task a level, and each task within a nested level an instance. Using the assigned task levels and instances, the cache management module is able to determine which cache entries to evict from cache when space is needed, and which evicted cache entries to recover upon completion of preempting tasks.