Patents by Inventor Alan Gatherer

Alan Gatherer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6904106
    Abstract: The interference cancellation (IC) system (500) includes a plurality of IC units, for which IC is applied. Each IC unit has its spread spectrum code generator, delay devices, correlators or matched filters (MF), spreading circuits and subtracting and adding devices. The IC process in accordance with the invention includes using a bank of MF to despread the received signal at every time instant corresponding to every identified multipath of every user's transmitted signal. Based on the despread signals, an initial decision for the present information symbol of every user can be made using a single-user receiver such as, for example, the conventional Rake receiver or an equalizer. Based on the initial decisions, IC regenerates the multipath signals for each user using timed versions of the spread spectrum code, the delays of the multipaths, and the corresponding channel medium estimates.
    Type: Grant
    Filed: October 9, 2001
    Date of Patent: June 7, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Aris Papasakellariou, Alan Gatherer
  • Patent number: 6831956
    Abstract: A wireless receiver (UST). The receiver comprises at least one antenna (ATU) for receiving a plurality of frames (FR) in a form of a plurality of paths. Each of the plurality of frames comprises a plurality of time slots (SLN), and each of the plurality of time slots comprises a plurality of symbols. Further, each of the plurality of paths has a corresponding sample position, wherein the plurality of symbols comprise a primary synchronization code symbol (PSC). The receiver further comprises circuitry (52) for correlating a primary synchronization code across a group of the plurality of symbols and circuitry (52) for identifying a plurality of path positions within the group. Each of the plurality of path positions corresponds to a respective one of a plurality of largest-amplitude paths represented within the group as detected in response to the circuitry for correlating. The receiver further comprises circuitry (56) for defining a plurality of sub-windows.
    Type: Grant
    Filed: September 26, 2000
    Date of Patent: December 14, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Timothy M. Schmidl, Alan Gatherer, Srinath Hosur, Anand G. Dabak
  • Patent number: 6829290
    Abstract: A wireless receiver (UST). The receiver comprises at least one antenna (ATU) for receiving a plurality of frames (FR) in a form of a plurality of paths. Each of the plurality of frames comprises a plurality of time slots (SLN), and each of the plurality of time slots comprises a plurality of symbols. Further, each of the plurality of paths has a corresponding sample position, wherein the plurality of symbols comprise a primary synchronization code symbol (PSC). The receiver further comprises circuitry (52) for correlating a primary synchronization code across a group of the plurality of symbols, and circuitry for identifying a plurality of path positions within the group. Each of the plurality of path positions corresponds to a respective one of a plurality of largest-amplitude paths represented within the group as detected in response to the circuitry for correlating.
    Type: Grant
    Filed: September 26, 2000
    Date of Patent: December 7, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Timothy M. Schmidl, Alan Gatherer, Srinath Hosur, Anand G. Dabak
  • Patent number: 6804311
    Abstract: A circuit for detecting a transmit diversity signal comprises a first circuit (706) arranged to receive a first synchronization code. The first synchronization code is modulated by a data signal. The first circuit produces a first output signal. A second circuit (732) is arranged to receive a plurality of predetermined signals. The second circuit produces a channel estimate. A detection circuit (710, 712) is arranged to receive the first output signal and the channel estimate. The detection circuit produces a signal corresponding to the data signal.
    Type: Grant
    Filed: March 15, 2000
    Date of Patent: October 12, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Anand G. Dabak, Srinath Hosur, Shigenori Kinjo, Alan Gatherer
  • Patent number: 6765956
    Abstract: A modem comprises circuitry for receiving an analog signal from a line and circuitry for converting the analog signal to a digital signal. The digital signal comprises a plurality of ideal sample points (P0-P3), each separated in time by a period T, and the plurality of ideal sample points comprises a sync sequence (14). The modem further comprises circuitry (34) for detecting the sequence comprising an integer number S of sampling circuits (38, 40), wherein S is two or greater. Each of the sampling circuits comprises circuitry for taking a sample corresponding to each of the plurality of ideal sample points at least once per the period T. Each of the sampling circuits also comprises circuitry for comparing a plurality of taken samples to a correlation sequence. Finally, each of the sampling circuits comprises circuitry for outputting a sync detected signal (SYNC0, SYNC1) in response to a sufficient match between the plurality of taken samples and the correlation sequence.
    Type: Grant
    Filed: March 21, 2000
    Date of Patent: July 20, 2004
    Assignee: Texas Instruments Incorporated
    Inventor: Alan Gatherer
  • Patent number: 6725025
    Abstract: An improved interference cancellation technique is disclosed. Digital baseband circuitry (40) includes user and symbol detection circuitry (50) for performing a Gibbs sampler type of interference cancellation, either embodied in custom hardware (44) or in software. Random initial guesses for a signal sample (either a symbol or chip) are made for each user. Interference cancellation is performed on a user-by-user basis, using the then-current data decision values for the other, interfering users. A soft data decision is used to derive a probability distribution function for the actual data decision for the sample for the user. A randomly selected value is applied against the probability distribution function to generate the next data decision value for that user, and the process is repeated until convergence. Following convergence, a statistic is used to select a final data decision value for each user, from the set of intermediate data decision values stored in memory.
    Type: Grant
    Filed: September 20, 2000
    Date of Patent: April 20, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Timothy M. Schmidl, Alan Gatherer, Xiaodong Wang, Rong Chen
  • Patent number: 6690750
    Abstract: A Viterbi decoder system is provided in accordance with the present invention. The decoder system includes a State Metric Update unit including a state metric memory and a cascaded Add/Compare/Select (ACS) unit. The cascaded ACS unit comprises a plurality of serially coupled ACS stages for performing a plurality of ACS operations in conjunction with the state metric memory. An ACS stage is operable to identify a plurality of path decisions and communicate the identified path decisions to a next ACS stage coupled thereto. A Traceback unit is provided for storing a set of accumulated path decisions in a traceback memory associated therewith, and performing a traceback on the set of accumulated path decisions. The path decisions associated with the ACS stage and the next ACS stage are accumulated as a set during the ACS operations before being written to the traceback memory, thereby minimizing accesses to the traceback memory.
    Type: Grant
    Filed: December 23, 1999
    Date of Patent: February 10, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Dale E. Hocevar, Alan Gatherer
  • Publication number: 20030202506
    Abstract: In one form of the invention, a process of sending real-time information from a sender computer (103) to a receiver computer (105) coupled to the sender computer (103) by a packet network (100) wherein packets (111,113) sometimes become lost, includes steps of directing (441) packets (111) containing the real-time information from the sender computer (103) by at least one path (119) in the packet network (100) to the receiver computer (105), and directing packets (113) containing information dependent on the real-time information from the sender computer (103) by at least one path diversity path (117) in the packet network (100) to the same receiver computer (105).
    Type: Application
    Filed: December 16, 2002
    Publication date: October 30, 2003
    Inventors: Stephen J. Perkins, Alan Gatherer, Krishanasamy Anandakumar, Alan V. McCree, Vishu Viswanathan
  • Patent number: 6636560
    Abstract: The operation of a line card in the local exchange of a point-to-point switched telephone network is modified to increase the data rate of voiceband modem transmission by increasing the sampling rate and providing controlled intersymbol interference using partial response techniques.
    Type: Grant
    Filed: January 20, 1999
    Date of Patent: October 21, 2003
    Assignee: Texas Instruments Incorporated
    Inventor: Alan Gatherer
  • Patent number: 6611857
    Abstract: A multiplier (12) is disclosed that includes an encoder (36), a hierarchy of compressors (40, 42, 44, 50, 52, 60 and 70), a bit detector (130) and a switch (134). The encoder (36) is operable to receive a first and second encoder input. The compressors (40, 42, 44, 50, 52, 60 and 70) are coupled to the encoder (36). The compressors (40,42, 44, 50, 52, 60 and 70) are operable to receive a first number of inputs and to generate a second number of outputs, with the second number being less than the first number. The bit detector (130) is operable to monitor the first encoder input to determine whether the first encoder input is in a reduced precision range (28). The bit detector (130) is also operable to deactivate a subset of the compressors (40 and 50) when the bit detector (130) determines that the first encoder input is in the reduced precision range (28). The switch (134) is coupled to a specified one of the compressors (42).
    Type: Grant
    Filed: November 15, 2000
    Date of Patent: August 26, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Carl E. Lemonds, Alan Gatherer
  • Publication number: 20030156630
    Abstract: This invention provide parallel interference cancellation for wireless communication base stations. Received user inputs symbols are spread by means of pseudo-noise sequences to form user input chip vectors. These are added together and interpreted to form chip vectors of interference samples. These chip vectores are despread to form interference output symbols by means of said pseudo-noise sequences. The interference output signals are subtracted from the received user input symbols to obtain a first estimate of transmitted symbols. This process may be continued for two or more iterations to obtain better interference cancellation.
    Type: Application
    Filed: February 11, 2003
    Publication date: August 21, 2003
    Inventors: Sundararajan Sriram, Alan Gatherer
  • Publication number: 20030148793
    Abstract: A programmable co-processor system comprising a datapath, a microprogram, and a microcontroller is provided. The datapath includes one or more datapath elements operable to receive input signals. The microprogram memory includes a microprogram operable to control the datapath in order to process the input signals. The microcontroller is operable to modify the microprogram based on a modification command.
    Type: Application
    Filed: September 4, 2002
    Publication date: August 7, 2003
    Inventors: Vijay Sundararajan, Sriram Sundararajan, Alan Gatherer
  • Patent number: 6603412
    Abstract: Quasi-parallel read/write interleaver architecture for data blocks by sequential spreading of variable size data subblocks into memory banks with bank address contention initiating the next data subblock. Iterative Turbo decoders with MAP decoders use such quasi-parallel interleavers and deinterleavers.
    Type: Grant
    Filed: December 28, 2001
    Date of Patent: August 5, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Alan Gatherer, Anand Dabak, Timothy M. Schmidl, John Linn
  • Publication number: 20030140305
    Abstract: MAP decoder with cascade architecture. Iterative Turbo decoders can use two such cascade MAP decoders with feedback in conjunction with interleaver and deinterleaver where the MAP decoders generate extrinsic information for iterations.
    Type: Application
    Filed: December 28, 2001
    Publication date: July 24, 2003
    Inventors: Alan Gatherer, Tod D. Wolf
  • Publication number: 20030133523
    Abstract: In a wireless communication receiver (31) of a wireless communication system that utilizes transmit diversity and turbo coding, symbol decisions are based at least in part on a posteriori probabilities (47, 48) produced by SISO decoders (35, 36). These probabilities are produced iteratively in alternating fashion to support the symbol decision process. The SISO decoder associated with the weakest (92) wireless communication channel goes first (93) in the iterative process.
    Type: Application
    Filed: January 11, 2002
    Publication date: July 17, 2003
    Inventors: Alan Gatherer, Everest W. Huang
  • Publication number: 20030097630
    Abstract: This invention describes implementation approaches for sliding window turbo decoders. Sliding windows are used for both the beta and alpha state metric calculations. Initialization of the beta/alpha prolog sections with data from a previous iteration is employed in conjunction with a reduced length prolog section. For subsequent sliding windows the trellis values of the prolog sections are dynamically initialized based upon data derived from the signal to noise ratio of the calculated extrinsic data or the difference between the two most probable trellis states.
    Type: Application
    Filed: September 27, 2002
    Publication date: May 22, 2003
    Inventors: Tod D. Wolf, Antonio F. Mondragon-Torres, Alan Gatherer
  • Patent number: 6560294
    Abstract: A cable modem (20) including a demodulator (25) having an improved carrier recovery circuit (35) is disclosed. The cable modem (20) demodulates phase-modulated signals, including phase and amplitude modulated signals such as quadrature amplitude modulation (QAM) information. The carrier recovery circuit (35) includes a phase detection function (40), preferably realized by way of programs executed by a digital signal processor, that generates a derivative signal (g(x″)) based upon a summation of a complex function of a corrected input signal (x″) over some or all of the possible points in the modulation constellation. In one embodiment of the invention, the derivative signal is an exact evaluation, considered over the sum of all points in the constellation; in another embodiment of the invention, only four small magnitude points, at relative quadrature phases, are included in the summation.
    Type: Grant
    Filed: September 10, 1999
    Date of Patent: May 6, 2003
    Assignee: Texas Instruments Incorporated
    Inventor: Alan Gatherer
  • Publication number: 20030084393
    Abstract: Operands (90) that are represented in two's complement format are prepared for use in binary arithmetic. For each operand, it is determined (91, 93) whether an original value thereof is within a predetermined proximity of a maximum positive/maximum negative value boundary associated with the two's complement format. If any of the original operand values is within the predetermined proximity, all of the original operand values are adjusted (95) to produce respectively corresponding adjusted operand values (96) for use in a binary arithmetic operation.
    Type: Application
    Filed: October 26, 2001
    Publication date: May 1, 2003
    Inventors: Tod David Wolf, Alan Gatherer
  • Patent number: 6549584
    Abstract: A modem (12) including a least-significant bit convolutional coding scheme is disclosed. In the transmit side of the modem (12), an encoder (28) is included, within which convolutional coders (35I, 35Q) are used to each encode one bit of each symbol applied to a phase and amplitude modulation constellation, preferably the least significant bits, such that the encoded bits select one of a plurality of sub-constellations in the modulated signal. Each of the coders (35, 35′) are arranged as finite state machines, of either thirty-two or sixty-four states. The minimum Hamming distance (dfree) provided by the codes is four, such that the resulting coding gain of the modem is improved over conventional encoding schemes.
    Type: Grant
    Filed: June 30, 1999
    Date of Patent: April 15, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Alan Gatherer, Murtaza Ali
  • Publication number: 20030067968
    Abstract: The interference cancellation (IC) system (500) includes a plurality of IC units, for which IC is applied. Each IC unit has its spread spectrum code generator, delay devices, correlators or matched filters (MF), spreading circuits and subtracting and adding devices. The IC process in accordance with the invention includes using a bank of MF to despread the received signal at every time instant corresponding to every identified multipath of every user's transmitted signal. Based on the despread signals, an initial decision for the present information symbol of every user can be made using a single-user receiver such as, for example, the conventional Rake receiver or an equalizer. Based on the initial decisions, IC regenerates the multipath signals for each user using timed versions of the spread spectrum code, the delays of the multipaths, and the corresponding channel medium estimates.
    Type: Application
    Filed: October 9, 2001
    Publication date: April 10, 2003
    Inventors: Aris Papasakellariou, Alan Gatherer