Abstract: Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and the high stress masked portion of the material is selectively removed, preferably by an etching process. The low stress portion of the material remains and forms a shaped structure. One preferred selective etching process uses a basic etchant. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.

Abstract: A microelectronic device fabricating method includes providing a substrate having a beveled portion and forming a layer of structural material on the beveled portion. Some of the structural material can be removed from the beveled portion by anisotropic etching to form a device feature from the structural material. The device feature can be formed on the beveled portion as with a pair of spaced, adjacent barrier material lines that are substantially void of residual shorting stringers extending therebetween. Structural material can be removed from the beveled portion to form an edge defined feature on a substantially perpendicular edge of the substrate. The beveled portion and perpendicular edge can be part of a mandril. The mandril can be removed from the substrate after forming the edge defined feature.

Abstract: In one aspect, the invention includes a method of forming a silicon-comprising material having a roughened outer surface. A semiconductive substrate is provided which comprises conductively doped silicon. A layer comprising silicon and germanium is formed over the substrate. The layer is exposed to conditions which cause crystalline grains within it to increase in size until roughness of a surface of the layer is increased. Dopant is out-diffused from the conductively doped silicon and into the crystalline grains of the layer to conductively dope the layer. In another aspect, the invention includes a method of forming a capacitor construction. A substrate is provided and a conductively doped silicon-comprising material is formed to be supported by the substrate. A layer is formed against the conductively doped silicon-comprising material. The layer has an outermost surface, and comprises silicon and germanium. The layer is subjected to conditions which increase a roughness of the outermost surface.

Abstract: A method and apparatus for performing multiple implantations in a semiconductor wafer is used to set variable implantation waveforms. An implanter is used, which allows for setting of variable waveforms, corresponding to energy, beam current, and angle, used for implantation. At least one of a ramping voltage, a ramping beam current source, and a programmable motor mechanically connected to a wafer table is used to obtain the variable waveforms. Using the implanter and method of the invention, detailed doping profiles are created using only a single implant. Such detailed doping profiles are used to create high gradient retrograde wells, and transistors with punch-through suppression implants and channel implants with controlled dopant gradients.

Abstract: There is disclosed a memory cell having a reduced active area. The memory cell may be incorporated into a memory array. A method of fabricating the memory cell and the memory array includes the fabrication of an access device, such as a diode, that protrudes above the semiconductor substrate. The memory element, such as a memory element formed of chalcogenide material, is disposed on the side of the protrusion to reduce the active area of the memory element as compared with conventional memory elements.

Abstract: Structures and methods involving n-channel flash memories with an ultrathin tunnel oxide thickness, have been provided. Both the write and erase operations are performed by tunneling. According to the teachings of the present invention, the n-channel flash memory cell with thin tunnel oxides will operate on a dynamic basis. The stored data can be refreshed every few seconds as necessary. However, the write and erase operations will however now be orders of magnitude faster than traditional n-channel flash memory and the cell provides a large gain. The present invention further provides structures and methods for n-channel floating gate transistors which avoid n-channel threshold voltage shifts and achieve source side tunneling erase. The n-channel memory cell structure includes a floating gate separated from a channel region by an oxide layer of less than 50 Angstroms (Å).

Abstract: Methods of forming electrical connections with an integrated circuitry substrate node location are described. According to one aspect of the invention, a substrate node location is laterally surrounded with insulating material and left outwardly exposed. Conductive material is deposited over the exposed node location. Subsequently, a photomaskless etch of the conductive material is conducted to a degree sufficient to leave a plug of conductive material over the node location. In a preferred implementation, the insulating material with which such node location is surrounded constitutes insulating material portions which are provided relative to conductive lines which are formed over the substrate. In another preferred implementation, such conductive lines form a grid of insulating material which, in turn, defines the node location. According to a preferred aspect of the invention, a plurality of insulated conductive lines are formed over a substrate.

Abstract: Improved methods and structures are provided that are lateral to surfaces with a (110) crystal plane orientation such that an electrical current of such structures is conducted in the <110> direction. Advantageously, improvements in hole carrier mobility of approximately 50% can be obtained by orienting the structure's channel in a (110) plane such that the electrical current flow is in the <110> direction. Moreover, these improved methods and structures can be used in conjunction with existing fabrication and processing techniques with minimal or no added complexity. Embodiments of a method of forming an integrated circuit include forming a trench in a silicon wafer. A trench wall of the trench has a (110) crystal plane orientation. A semiconductor device is also formed lateral to the trench wall such that the semiconductor device is capable of conducting an electrical current in a <110> direction. One method of the present invention provides for forming an integrated circuit.

Abstract: A memory cell and a method of fabricating the memory cell having a small active area. By forming a spacer in a window that is sized at the photolithographic limit, a pore may be formed in dielectric layer which is smaller than the photolithographic limit. Electrode material is deposited into the pore, and a layer of structure changing material, such as chalcogenide, is deposited onto the lower electrode, thus creating a memory element having an extremely small and reproducible active area.

Abstract: Methods of forming capacitors, methods of forming capacitor-over-bit line memory circuitry, and related integrated circuitry constructions are described. In one embodiment, a capacitor storage node is formed having an uppermost surface and an overlying insulative material over the uppermost surface. Subsequently, a capacitor dielectric functioning region is formed discrete from the overlying insulative material operably proximate at least a portion of the capacitor storage node. A cell electrode layer is formed over the capacitor dielectric functioning region and the overlying insulative material. In another embodiment, a capacitor storage node is formed having an uppermost surface and a side surface joined therewith. A protective cap is formed over the uppermost surface and a capacitor dielectric layer is formed over the side surface and protective cap. A cell electrode layer is formed over the side surface of the capacitor storage node.

Abstract: A microelectronic device fabricating method includes providing a substrate having a beveled portion and forming a layer of structural material on the beveled portion. Some of the structural material can be removed from the beveled portion by anisotropic etching to form a device feature from the structural material. The device feature can be formed on the beveled portion as with a pair of spaced, adjacent barrier material lines that are substantially void of residual shorting stringers extending therebetween. Structural material can be removed from the beveled portion to form an edge defined feature on a substantially perpendicular edge of the substrate. The beveled portion and perpendicular edge can be part of a mandril. The mandril can be removed from the substrate after forming the edge defined feature.

Abstract: A method and apparatus for performing multiple implantations in a semiconductor wafer is used to set variable implantation waveforms. An implanter is used, which allows for setting of variable waveforms, corresponding to energy, beam current, and angle, used for implantation. At least one of a ramping voltage, a ramping beam current source, and a programmable motor mechanically connected to a wafer table is used to obtain the variable waveforms. Using the implanter and method of the invention, detailed doping profiles are created using only a single implant. Such detailed doping profiles are used to create high gradient retrograde wells, and transistors with punch-through suppression implants and channel implants with controlled dopant gradients.

Abstract: There is disclosed a memory cell having a reduced active area. The memory cell may be incorporated into a memory array. A method of fabricating the memory cell and the memory array includes the fabrication of an access device, such as a diode, that protrudes above the semiconductor substrate. The memory element, such as a memory element formed of chalcogenide material, is disposed on the side of the protrusion to reduce the active area of the memory element as compared with conventional memory elements.

Abstract: A photomask for manufacturing a semiconductor device. The photomask is manufactured by a providing a photomask substrate and alternately depositing a plurality of layers of a light-absorbing material and of an etch-stop material on the photomask substrate. The light-absorbing material is selected as having a well-defined etching selectivity from that of the etch-stop material. The layers are successively patterned by removing by a selective etching process at least a portion of at least one of said layers, the portion removed from a lower, in relation to the substrate, layer a subset of the portion removed from a higher layer. Together, the patterned layers are used as a photomask to photolithographically imprint a pattern of a photoresist on a semiconductor wafer under manufacture. The photoresist is used in the etching process of the semiconductor wafer.

Abstract: A memory cell and a method of fabricating the memory cell having a small active area. By forming a spacer in a window that is sized at the photolithographic limit, a pore may be formed in dielectric layer which is smaller than the photolithographic limit. Electrode material is deposited into the pore, and a layer of structure changing material, such as chalcogenide, is deposited onto the lower electrode, thus creating a memory element having an extremely small and reproducible active area.

Abstract: In one aspect, the invention includes a method of densifying a silicon nitride layer comprising: after forming the silicon nitride layer, exposing the silicon nitride layer to atomic nitrogen, the exposing not increasing a thickness of the silicon nitride layer by more than about 10 Angstroms. In another aspect, the invention includes a method of densifying a silicon nitride layer comprising: after forming the silicon nitride layer, exposing the silicon nitride layer to atomic nitrogen in the substantial absence of a silicon-containing gas.

Abstract: The transfer device of a typical DRAM cell is replaced with a transistor having an additional gate. The unique cell can be accessed as a typical DRAM cell by reading from or writing to a storage capacitor or as a nonvolatile memory by storing charges on the additional gate. Thus, a DRAM cell having a nonvolatile memory component within its cell is formed in a simple and cost effective manner. Transistors in a typical SRAM cell are also replaced by the transistors with the additional gate to form a SRAM cell having a nonvolatile component built within its cell.

Abstract: A memory cell having first and second operating modes includes a transistor comprising a gate adjacent to a channel region coupling source and drain regions, a digitline coupled to one of the source and drain regions, a storage capacitor coupled to the other of the source and drain regions, a ferroelectric capacitor, and a wordline coupled to the gate by the ferroelectric capacitor. Preferably, data is written to and read out of the storage capacitor during the first operating mode and written to and read out of the ferroelectric capacitor during the second mode of operation. A memory cell array, a memory module, and a processor based system can all be fabricated from this memory cell. A method for reading data out of the memory cell in first and second operating modes is also described.

Abstract: The invention includes a multilayer resist method of patterning a substrate. In one implementation, a first etch mask layer is formed over a substrate. A second etch mask layer is deposited over the first etch mask layer at a temperature of less than or equal to 20.degree. C. A resist layer is formed and patterned over the second etch mask layer. The second etch mask layer is etched through, through an opening formed in the resist layer. The first etch mask layer is etched through using at least the etched second mask layer as a mask. In one implementation, a first etch mask layer is formed over a substrate. A second etch mask layer comprising a silanol is formed over the first etch mask layer. The silanol of the second etch mask layer is converted to a silicon oxide. H.sub.2 O from the second etch mask layer is driven out at a temperature of at least about 100.degree. C. A resist layer is formed and patterned over the silicon oxide containing second etch mask layer.

Abstract: A photomask for manufacturing a semiconductor device. The photomask is manufactured by a providing a photomask substrate and alternately depositing a plurality of layers of a light-absorbing material and of an etch-stop material on the photomask substrate. The light-absorbing material is selected as having a well-defined etching selectivity from that of the etch-stop material. The layers are successively patterned by removing by a selective etching process at least a portion of at least one of said layers, the portion removed from a lower, in relation to the substrate, layer a subset of the portion removed from a higher layer. Together, the patterned layers are used as a photomask to photolithographically imprint a pattern of a photoresist on a semiconductor wafer under manufacture. The photoresist is used in the etching process of the semiconductor wafer.