Abstract: The invention includes methods of patterning substrates. In one implementation, an electrically conductive etch mask layer is formed over a substrate. A resist layer, for example photoresist, is formed over the etch mask layer. The etch mask layer is etched into through an opening formed in the patterned resist. The etching preferably comprises dry etching within a dual source, high density plasma etcher using an oxygen containing gas. Substrate layers beneath the electrically conductive base layer are preferably etched through one or more openings formed in the conductive layer at least in part by the preferred dry etching. The etch mask layer and resist are ultimately removed from the substrate.

Abstract: There is disclosed a memory cell having a reduced active area. The memory cell may be incoporated into a memory array. A method of fabricating the memory cell and the memory array includes the fabrication of an access device, such as a diode, that protrudes above the semiconductor substrate. The memory element, such as a memory element formed of chalcogenide material, is disposed on the side of the protrusion to reduce the active area of the memory element as compared with conventional memory elements.

Abstract: The invention proposes methods for producing integrated circuits wherein the dielectric constant between closely spaced and adjacent metal lines is approaching 1. One method of the invention uses low-melting-point dielectric to form a barrier forming a void between conductive lines. Another method of the invention uses sidewall film to form a similar barrier.

Abstract: Stress resulting from silicon nitride is diminished by forming an oxidation mask with silicon nitride having a graded silicon concentration. Grading is accomplished by changing the silicon content in the silicon nitride by varying the amount of hydride, such as dichlorosilane (DCS), mixed with ammonia. The silicon nitride can be graded in a substantially linear or non-linear fashion. Silicon nitride formed with higher levels of DCS mixed with ammonia is referred to as silicon rich nitride because of its relatively higher silicon content. In one embodiment, the graded silicon nitride may be formed with one type of non-linear silicon grading, an abrupt junction. In other embodiments, the silicon nitride is formed in a variety of shapes fashioned during or after silicon nitride growth. In one embodiment, the stress from the silicon nitride is reduced by forming a polysilicon buffer layer between two silicon nitride layers.

Abstract: The invention provides methods for forming contact openings to a substrate location with which electrical connection is desired. According to one aspect, a multi-level layer comprising masking material or photoresist is formed atop an electrically conductive substrate surface and defines a mask opening through which a contact opening is to be formed to an elevationally lower substrate location. A single layer of photoresist is patterned to form an elevationally thicker first layer immediately laterally adjacent the mask opening than a second layer which is formed laterally outward of the first layer. The electrically conductive substrate surface is etched through the mask opening to form the contact opening. The photoresist second layer is removed and the conductive substrate surface is etched to form a portion of an outer conductive component. Thereafter, conductive material is formed in the contact opening to electrically connect elevationally separated layers.

Abstract: A method used during the formation of a semiconductor device comprises the steps of providing a semiconductor substrate assembly having at least one recess therein then forming a first dielectric layer within the recess. The first dielectric layer is formed with a thickness that will prevent the first dielectric layer from impinging on itself in the recess, for example with a thickness less than half a width of the trench. The dielectric layer is then annealed in a manner that will increase the volume of the first dielectric layer. After annealing the first dielectric layer, a second dielectric layer is formed over the first dielectric layer within the recess. The second dielectric layer is formed with a sufficient thickness such that it impinges on itself in the recess. The second dielectric layer is then annealed.

Abstract: A memory cell and a method of fabricating the memory cell having a small active area. By forming a spacer in a window that is sized at the photolithographic limit, a pore may be formed in dielectric layer which is smaller than the photolithographic limit. Electrode material is deposited into the pore, and a layer of structure changing material, such as chalcogenide, is deposited onto the lower electrode, thus creating a memory element having an extremely small and reproducible active area.

Abstract: A chalcogenide memory cell with chalcogenide electrodes positioned on both sides of the active chalcogenide region of the memory cell. The chalcogenide memory cell includes upper and lower chalcogenide electrodes with a dielectric layer positioned therebetween. The dielectric layer includes an opening defining a pore. A volume of chalcogenide material formed integral to the upper chalcogenide electrode is contained within the pore. The upper and lower chalcogenide electrodes both have greater cross sectional areas than the pore.

Abstract: Methods of forming electrical connections with an integrated circuitry substrate node location are described. According to one aspect of the invention, a substrate node location is laterally surrounded with insulating material and left outwardly exposed. Conductive material is deposited over the exposed node location. Subsequently, a photomaskless etch of the conductive material is conducted to a degree sufficient to leave a plug of conductive material over the node location. In a preferred implementation, the insulating material with which such node location is surrounded constitutes insulating material portions which are provided relative to conductive lines which are formed over the substrate. In another preferred implementation, such conductive lines form a grid of insulating material which, in turn, defines the node location. According to a preferred aspect of the invention, a plurality of insulated conductive lines are formed over a substrate.

Abstract: The invention proposes methods for producing integrated circuits wherein the dielectric constant between closely spaced and adjacent metal lines is approaching 1. One method of the invention uses low-melting-point dielectric to form a barrier form a void between conductive lines. Another method of the invention uses sidewall film to form a similar barrier.

Abstract: A method of fabricating a chalcogenide memory cell wherein a layer of chalcogenide material is deposited in an amorphous state. The layer of amorphous chalcogenide material is then etched to its final geometry while maintaining its amorphous structure. The final geometry of the chalcogenide material is then annealed thereby transforming it to a crystalline form.

Abstract: A method for fabricating chalcogenide memories in which ultra-small pores are formed in insulative layers using disposable spacers. The chalcogenide memory elements are positioned within the ultra-small pores. The chalcogenide memory elements thus defined have minimum lateral dimensions ranging from approximately 500 to 4000 Angstroms.

Abstract: A chalcogenide memory cell with chalcogenide electrodes positioned on both sides of the active chalcogenide region of the memory cell. The chalcogenide memory cell includes upper and lower chalcogenide electrodes with a dielectric layer positioned therebetween. The dielectric layer includes an opening defining a pore. A volume of chalcogenide material formed integral to the upper chalcogenide electrode is contained within the pore. The upper and lower chalcogenide electrodes both have greater cross sectional areas than the pore.

Abstract: The invention proposes methods for producing integrated circuits wherein the dielectric constant between closely spaced and adjacent metal lines is approaching 1. One method of the invention uses low-melting-point dielectric to form a barrier from a void between conductive lines by heating the dielectric. Another method of the invention uses sidewall film to form a similar barrier.

Abstract: An etch mask having a narrow spacer layer self-aligned and adjacent to a first portion of an inorganic first layered segment. An inorganic second layered segment comprises a portion of the etch mask and encompasses a perimeter of the first layered segment and is distanced from the first layered segment by a distance equal to a thickness of the narrow spacer layer. A first portion of the second layered segment is adjacent to the narrow spacer layer. A void exists between second portions of the first and the second layered segments. The area of the substrate exposed by the etch mask of the invention, when etched, forms a trench whose width is limited only by the width of the void which is equal to the width of the narrow spacer layer. The narrowness of the narrow isolated trench formed using the etch mask of the invention maximizes die space.

Abstract: A method of fabricating a phase shifting reticle that can be used as a mask in photolithographic processes such as semiconductor wafer patterning. A transparent quartz substrate is coated with a film of an oxidizable silicon material. The silicon is then coated with a material suitable for isolating the silicon material from an oxidizing environment. A resist coating is placed atop the isolation material, developed and etched, exposing the isolation in a predetermined pattern. The isolation material is etched and the substrate placed in an oxidizing environment. The silicon material expands to a predetermined thickness, forming a phase shifter on the substrate. Next, the remaining isolation material and unoxidized silicon are removed, forming transmission regions adjacent the phase shifters. Then the remaining resist is removed to form opaque or light blocking areas on the substrate to complete formation of a phase shifting reticle.

Abstract: An integrated circuit memory array has a data input/output, a Read/Write* signal input, a row decoder, and a column decoder. An input circuit inputs a beginning and ending address to an on-chip memory controller which then sequentially addresses the beginning address, all the cells between the beginning address and the ending address, and the ending address, causing the array to sequentially output or input data from the sequence of cells, depending on the state of the Read/Write* signal.

Abstract: The invention comprises a semiconductor package which allows pinouts and bond options to be customized after the encasement of a die in plastic, ceramic, or other suitable materials. A first embodiment of the invention has a first assembly comprising an encapsulated die having bond pads connected to bond wires which terminate in exterior pad portions on the exterior of the encapsulant. Conductive paths which are part of a second assembly electrically connect with the exterior pad portions of the first assembly and pass signals to device pinouts, which can be leads or other connecting means, to an electronic device into which the module is installed. By selectively connecting the exterior pad portions of the first assembly to the connection points of the conductive paths of the second assembly, the device pinouts and bond options can be selected. To manufacture a device having different pinouts or bond options, a bottom section having a different design is used.

Abstract: A method of producing sharp points on the surface of a substrate is described. The points are useful as field emitter tips, and may also be used to collect radiant energy and for the production of micromachined objects such as micron sized gears and levers. Conventional techniques of asperity fabrication typically use an undercut of a hard mask to etch away the substrate material. This conventional method is very time specific and difficult to control. The inventive process uses a more easily controlled etch than conventional asperity fabrication techniques. The inventive process begins with a substrate highly doped with a P-type dopant such as boron which prevents an etch with KOH or other material. A hard mask is patterned over the substrate surface, and an N-type dopant, such as phosphorous or arsenic, is implanted into the substrate surface. The N-type dopant diffuses under the hard mask at a rate more easily controlled than the etch used in conventional techniques.

Abstract: An improved DRAM cell having a tantalum metal lower plate, a tantalum-silicide buried contact, and a tantalum oxide capacitor dielectric layer is disclosed. Also disclosed are several methods for fabricating the improved cell. Fabrication of an array of the improved cells proceeds through the storage-node contact opening stage in a manner consistent with the fabrication process utilized for conventional stacked-cell DRAM arrays. The process for fabricating the improved cells deviates from convention after storage-node contact openings are formed. A tantalum metal layer is conformally deposited over the wafer surface, patterned and etched to create individual storage-node plates. The wafer is then subjected to an elevated temperature step in an oxygen ambient, which creates both a tantalum silicide layer at the tantalum-silicon interface of each storage-node contact, and a tantalum oxide dielectric layer on the exposed surfaces of each storage-node plate.