Patents by Inventor Alan Roth

Alan Roth has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240321513
    Abstract: An integrated circuit includes a first conductive path over a substrate, a coil structure over the substrate, and a ferromagnetic ring. The first conductive path is configured to generate a first time-varying magnetic field based on a first time-varying current. The coil structure is configured to generate an induced electrical potential responsive to the first time-varying magnetic field. The ferromagnetic ring includes an open portion. The first conductive path extending through the open portion of the ferromagnetic ring. The first conductive path includes a first conductive line on a first level that is below the ferromagnetic ring, a second conductive line on a second level that is above the ferromagnetic ring, and a first via on a third level that is coplanar with the ferromagnetic ring, the first via electrically coupling the first conductive line and the second conductive line together.
    Type: Application
    Filed: June 7, 2024
    Publication date: September 26, 2024
    Inventors: Alan ROTH, Eric SOENEN
  • Publication number: 20240298967
    Abstract: A system for tracking the location of an anatomical structure, the system comprising: a J-bar and electrical lead assembly comprising: a J-bar comprising a tracker, a distal electrical connector formed on the tracker, and at least one mount for mounting the tracker to tissue, wherein the tracker is configured to provide a signal representative of the position of the tracker when the tracker is supplied with electrical power; an expandable basket configured to assume (i) a radially-reduced profile when the expandable basket is radially constricted, and (ii) a radially-expanded profile when the expandable basket is not radially constricted, the expandable basket further comprising a distal electrical connector; and an electrical lead extending distally between the J-bar and the expandable basket, the electrical lead being electrically connected to (i) the distal electrical connector formed on the tracker, and (ii) the distal electrical connector of the expandable basket.
    Type: Application
    Filed: April 24, 2023
    Publication date: September 12, 2024
    Inventors: Raphael BUENO, Jayender JAGADEESAN, Alan D. LUCAS, Larry Roth, Tim Robinson
  • Patent number: 12072726
    Abstract: Voltage reference circuits are provided. A voltage reference circuit includes a first transistor, a flipped-gate transistor, a first current mirror unit, a second current mirror unit, and an output note. The first transistor is formed by a plurality of second transistors. A gate and a drain of the flipped-gate transistor are coupled to a gate and a drain of each second transistor. The first current mirror unit is configured to provide a first current to the flipped-gate transistor and a mirroring current in response to a bias current. The second current mirror unit is configured to drain a second current from the first transistor in response to the mirroring current. The output node is coupled to a source of each second transistor and the second current mirror unit, and configured to output a reference voltage. Size of the flipped-gate transistor is less than that of the first transistor.
    Type: Grant
    Filed: April 28, 2023
    Date of Patent: August 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yen-Ting Wang, Alan Roth, Eric Soenen, Alexander Kalnitsky, Liang-Tai Kuo, Hsin-Li Cheng
  • Publication number: 20240235393
    Abstract: A power converter module includes a ground terminal, an input voltage terminal configured to receive a raw input voltage, and an interconnection terminal configured to provide a regulated output voltage to a load such as a SOC or SIP system to be powered. A voltage regulator is connected to the ground terminal and the input voltage terminal. An inductor has an inductor output connected to the interconnection terminal.
    Type: Application
    Filed: December 26, 2023
    Publication date: July 11, 2024
    Inventors: Ying-Chih Hsu, Eric Soenen, Alan Roth
  • Publication number: 20240223085
    Abstract: Devices and methods are provided for controlling dead-time of a direct current to direct current (DC-DC) converter. A control circuit includes a first transistor having a source/drain terminal coupled to an output voltage of the DC-DC converter configured to provide current based on the output voltage. The control circuit also includes a digital up/down counter having an output terminal electrically coupled to an input terminal of a delay cell of the DC-DC converter. A current sensing circuit of the control circuit is electrically coupled to an input terminal of the digital up/down counter configured to receive the current and drive the digital up/down counter based on the current.
    Type: Application
    Filed: March 18, 2024
    Publication date: July 4, 2024
    Inventors: Chia-Chun Chang, Alan Roth, Eric Soenen, Tysh-Bin Liu
  • Patent number: 12009148
    Abstract: An integrated circuit includes a first conductive path over a substrate, a coil structure over the substrate, and a ferromagnetic structure. The first conductive path is configured to carry a first time-varying current and to generate a first time-varying magnetic field based on the first time-varying current. The coil structure is magnetically coupled with the first conductive path, and is configured to generate an induced electrical potential responsive to the first time-varying magnetic field. The ferromagnetic structure includes an open portion. The first conductive path extends through the open portion of the ferromagnetic structure. The first conductive path includes a first conductive line below the ferromagnetic structure, a second conductive line above the ferromagnetic structure, and a first via plug coplanar with the ferromagnetic structure. The first via plug electrically coupling the first conductive line and the second conductive line.
    Type: Grant
    Filed: January 19, 2023
    Date of Patent: June 11, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Alan Roth, Eric Soenen
  • Publication number: 20240162277
    Abstract: Various magnetic thin film inductor structures are disclosed that include one or more magnetic thin film (MTF) materials. During operation, an electric field passes through one or more conductive windings which, in turn, generates a magnetic field for storing energy within these magnetic thin film inductor structures. The magnetic thin film (MTF) materials within these magnetic thin film inductor structures effectively attract magnetic flux lines of this magnetic field. As a result, any magnetic leakage resulting from the magnetic field generated by these magnetic thin film inductor structures onto nearby electrical, mechanical, and/or electro-mechanical devices is lessened when compared to magnetic leakage resulting from the magnetic field generated by other inductor structures not having the one or more MTF materials.
    Type: Application
    Filed: January 24, 2024
    Publication date: May 16, 2024
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Alan ROTH, Eric SOENEN, Paul RANNUCI
  • Publication number: 20240154609
    Abstract: Devices and methods are described herein for a pulse amplitude modulation (PAM) driver. In one embodiment, the PAM driver includes a first high-speed buffer configured to output a first voltage, a second high-speed buffer configured to output a second voltage, and a plurality of transistors coupled to the first high-speed buffer and the second high-speed buffer. At least one of the first voltage or the second voltage facilitates selective operation of a transistor of the plurality of transistors to output a third voltage.
    Type: Application
    Filed: January 17, 2024
    Publication date: May 9, 2024
    Inventors: Paul Ranucci, Alan Roth
  • Patent number: 11962240
    Abstract: Devices and methods are provided for controlling dead-time of a direct current to direct current (DC-DC) converter. A control circuit includes a first transistor having a source/drain terminal coupled to an output voltage of the DC-DC converter configured to provide current based on the output voltage. The control circuit also includes a digital up/down counter having an output terminal electrically coupled to an input terminal of a delay cell of the DC-DC converter. A current sensing circuit of the control circuit is electrically coupled to an input terminal of the digital up/down counter configured to receive the current and drive the digital up/down counter based on the current.
    Type: Grant
    Filed: April 7, 2021
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chia-Chun Chang, Alan Roth, Eric Soenen, Tysh-Bin Liu
  • Patent number: 11935914
    Abstract: Various magnetic thin film inductor structures are disclosed that include one or more magnetic thin film (MTF) materials. During operation, an electric field passes through one or more conductive windings which, in turn, generates a magnetic field for storing energy within these magnetic thin film inductor structures. The magnetic thin film (MTF) materials within these magnetic thin film inductor structures effectively attract magnetic flux lines of this magnetic field. As a result, any magnetic leakage resulting from the magnetic field generated by these magnetic thin film inductor structures onto nearby electrical, mechanical, and/or electro-mechanical devices is lessened when compared to magnetic leakage resulting from the magnetic field generated by other inductor structures not having the one or more MTF materials.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: March 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Alan Roth, Eric Soenen, Paul Rannuci
  • Patent number: 11909402
    Abstract: Devices and methods are described herein for a pulse amplitude modulation (PAM) driver. In one embodiment, the PAM driver includes a first high-speed buffer configured to output a first voltage, a second high-speed buffer configured to output a second voltage, and a plurality of transistors coupled to the first high-speed buffer and the second high-speed buffer. At least one of the first voltage or the second voltage facilitates selective operation of a transistor of the plurality of transistors to output a third voltage.
    Type: Grant
    Filed: June 23, 2022
    Date of Patent: February 20, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Paul Ranucci, Alan Roth
  • Patent number: 11855539
    Abstract: A power converter module includes a ground terminal, an input voltage terminal configured to receive a raw input voltage, and an interconnection terminal configured to provide a regulated output voltage to a load such as a SOC or SIP system to be powered. A voltage regulator is connected to the ground terminal and the input voltage terminal. An inductor has an inductor output connected to the interconnection terminal.
    Type: Grant
    Filed: February 1, 2022
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ying-Chih Hsu, Eric Soenen, Alan Roth
  • Publication number: 20230408580
    Abstract: A duty cycle measurement (DCM) device includes a charge pump circuit and a clocked comparator circuit. The charge pump circuit is configured to receive a clock signal that has an unknown duty cycle and to generate a capacitor voltage based on the duty cycle of the clock signal. The clocked comparator circuit is configured to receive the capacitor voltage and a reference voltage and to generate a digital output code based on the capacitor voltage and the reference voltage. The digital output code is indicative of the duty cycle of the clock signal. The charge pump circuit is further configured to receive the digital output code. A method of determining a duty cycle of a clock signal is also disclosed.
    Type: Application
    Filed: May 31, 2022
    Publication date: December 21, 2023
    Inventors: Eric Soenen, Alan Roth
  • Publication number: 20230266785
    Abstract: Voltage reference circuits are provided. A voltage reference circuit includes a first transistor, a flipped-gate transistor, a first current mirror unit, a second current mirror unit, and an output note. The first transistor is formed by a plurality of second transistors. A gate and a drain of the flipped-gate transistor are coupled to a gate and a drain of each second transistor. The first current mirror unit is configured to provide a first current to the flipped-gate transistor and a mirroring current in response to a bias current. The second current mirror unit is configured to drain a second current from the first transistor in response to the mirroring current. The output node is coupled to a source of each second transistor and the second current mirror unit, and configured to output a reference voltage. Size of the flipped-gate transistor is less than that of the first transistor.
    Type: Application
    Filed: April 28, 2023
    Publication date: August 24, 2023
    Inventors: Yen-Ting WANG, Alan ROTH, Eric SOENEN, Alexander KALNITSKY, Liang-Tai KUO, Hsin-Li CHENG
  • Publication number: 20230268912
    Abstract: Devices and methods are described herein for a pulse amplitude modulation (PAM) driver. In one embodiment, the PAM driver includes a first high-speed buffer configured to output a first voltage, a second high-speed buffer configured to output a second voltage, and a plurality of transistors coupled to the first high-speed buffer and the second high-speed buffer. At least one of the first voltage or the second voltage facilitates selective operation of a transistor of the plurality of transistors to output a third voltage.
    Type: Application
    Filed: June 23, 2022
    Publication date: August 24, 2023
    Inventors: Paul Ranucci, Alan Roth
  • Publication number: 20230261572
    Abstract: A semiconductor structure includes a first substrate. A first die and a second die are disposed over the first substrate and are adjacent to one another. A plurality of first conductive bumps are disposed between the first substrate and the first die and between the first substrate and the second die. A second substrate is disposed below the first substrate. A plurality of second conductive bumps is disposed between the first substrate and the second substrate. An in-package voltage regulator (PVR) chip is disposed over the second substrate. A molding material is disposed over the first substrate and surrounds the first die, the second die, the plurality of first conductive bumps, the plurality of second conductive bumps, and the PVR chip.
    Type: Application
    Filed: April 24, 2023
    Publication date: August 17, 2023
    Inventors: Alan Roth, Haohua Zhou, Eric Soenen, Ying-Chih Hsu, Paul Ranucci, Mei Hsu Wong, Tze-Chiang Huang
  • Publication number: 20230223846
    Abstract: A charge pump circuit includes an output stage coupled to an output, a pumping stage between an input and the output stage, and a control circuit that outputs control signals. A pumping stage transistor includes S/D terminals coupled to input/output terminals, capacitive devices between signal terminals and either a transistor gate or a S/D terminal, and diode devices including either the anode/cathode or cathode/anode coupled to the respective gate and S/D terminal. An output stage transistor includes S/D terminals coupled to an input terminal and the output. One control signal includes a transition from first to second logic levels at a first time and another control signal includes a transition from the first to second logic levels at a second time, and a period between the transitions is sufficiently small to cause a change in a voltage at the pumping stage S/D terminal to be less than 100 millivolts.
    Type: Application
    Filed: March 16, 2023
    Publication date: July 13, 2023
    Inventors: Alan ROTH, Eric SOENEN
  • Patent number: 11675383
    Abstract: Voltage reference circuits are provided. A voltage reference circuit includes a transistor, a flipped-gate transistor, a first current mirror unit, a second current mirror unit and an output node. The gate and the drain of the flipped-gate transistor are coupled to the gate and the drain of the transistor. The first current mirror unit is configured to provide a first current to the flipped-gate transistor and the mirroring current in response to a bias current. The second current mirror unit is configured to drain a second current from the transistor in response to the mirroring current. The output node is coupled to the source of the transistor and the second current mirror unit, and is configured to output a reference voltage.
    Type: Grant
    Filed: January 7, 2021
    Date of Patent: June 13, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yen-Ting Wang, Alan Roth, Eric Soenen, Alexander Kalnitsky, Liang-Tai Kuo, Hsin-Li Cheng
  • Patent number: 11671010
    Abstract: A semiconductor structure includes a first substrate. A first die and a second die are disposed over the first substrate and are adjacent to one another. A plurality of first conductive bumps are disposed between the first substrate and the first die and between the first substrate and the second die. A second substrate is disposed below the first substrate. A plurality of second conductive bumps is disposed between the first substrate and the second substrate. An in-package voltage regulator (PVR) chip is disposed over the second substrate. A molding material is disposed over the first substrate and surrounds the first die, the second die, the plurality of first conductive bumps, the plurality of second conductive bumps, and the PVR chip.
    Type: Grant
    Filed: August 12, 2020
    Date of Patent: June 6, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Alan Roth, Haohua Zhou, Eric Soenen, Ying-Chih Hsu, Paul Ranucci, Mei Hsu Wong, Tze-Chiang Huang
  • Publication number: 20230154675
    Abstract: An integrated circuit includes a first conductive path over a substrate, a coil structure over the substrate, and a ferromagnetic structure. The first conductive path is configured to carry a first time-varying current and to generate a first time-varying magnetic field based on the first time-varying current. The coil structure is magnetically coupled with the first conductive path, and is configured to generate an induced electrical potential responsive to the first time-varying magnetic field. The ferromagnetic structure includes an open portion. The first conductive path extends through the open portion of the ferromagnetic structure. The first conductive path includes a first conductive line below the ferromagnetic structure, a second conductive line above the ferromagnetic structure, and a first via plug coplanar with the ferromagnetic structure. The first via plug electrically coupling the first conductive line and the second conductive line.
    Type: Application
    Filed: January 19, 2023
    Publication date: May 18, 2023
    Inventors: Alan ROTH, Eric SOENEN