Abstract: Devices and methods are provided for controlling dead-time of a direct current to direct current (DC-DC) converter. A control circuit includes a first transistor having a source/drain terminal coupled to an output voltage of the DC-DC converter configured to provide current based on the output voltage. The control circuit also includes a digital up/down counter having an output terminal electrically coupled to an input terminal of a delay cell of the DC-DC converter. A current sensing circuit of the control circuit is electrically coupled to an input terminal of the digital up/down counter configured to receive the current and drive the digital up/down counter based on the current.

Abstract: Various magnetic thin film inductor structures are disclosed that include one or more magnetic thin film (MTF) materials. During operation, an electric field passes through one or more conductive windings which, in turn, generates a magnetic field for storing energy within these magnetic thin film inductor structures. The magnetic thin film (MTF) materials within these magnetic thin film inductor structures effectively attract magnetic flux lines of this magnetic field. As a result, any magnetic leakage resulting from the magnetic field generated by these magnetic thin film inductor structures onto nearby electrical, mechanical, and/or electro-mechanical devices is lessened when compared to magnetic leakage resulting from the magnetic field generated by other inductor structures not having the one or more MTF materials.

Abstract: Photonic ring modulators with high tuning efficiency and small footprint can be formed in a hybrid material platform from a silicon bus waveguide vertically coupled to an optically active compound semiconductor (e.g., III-V) ring resonator. The performance of the modulator, e.g., in terms of the tuning efficiency and the maximum insertion loss, may be optimized by suitable levels of an applied bias voltage and a heater power of a heater optionally included in the ring modulator. The disclosed hybrid photonic ring modulators may be used, e.g., in photonic transceiver circuits with high lane count.

Abstract: Devices and methods are described herein for a pulse amplitude modulation (PAM) driver. In one embodiment, the PAM driver includes a first high-speed buffer configured to output a first voltage, a second high-speed buffer configured to output a second voltage, and a plurality of transistors coupled to the first high-speed buffer and the second high-speed buffer. At least one of the first voltage or the second voltage facilitates selective operation of a transistor of the plurality of transistors to output a third voltage.

Abstract: A power converter module includes a ground terminal, an input voltage terminal configured to receive a raw input voltage, and an interconnection terminal configured to provide a regulated output voltage to a load such as a SOC or SIP system to be powered. A voltage regulator is connected to the ground terminal and the input voltage terminal. An inductor has an inductor output connected to the interconnection terminal.

Abstract: A duty cycle measurement (DCM) device includes a charge pump circuit and a clocked comparator circuit. The charge pump circuit is configured to receive a clock signal that has an unknown duty cycle and to generate a capacitor voltage based on the duty cycle of the clock signal. The clocked comparator circuit is configured to receive the capacitor voltage and a reference voltage and to generate a digital output code based on the capacitor voltage and the reference voltage. The digital output code is indicative of the duty cycle of the clock signal. The charge pump circuit is further configured to receive the digital output code. A method of determining a duty cycle of a clock signal is also disclosed.

Abstract: Voltage reference circuits are provided. A voltage reference circuit includes a first transistor, a flipped-gate transistor, a first current mirror unit, a second current mirror unit, and an output note. The first transistor is formed by a plurality of second transistors. A gate and a drain of the flipped-gate transistor are coupled to a gate and a drain of each second transistor. The first current mirror unit is configured to provide a first current to the flipped-gate transistor and a mirroring current in response to a bias current. The second current mirror unit is configured to drain a second current from the first transistor in response to the mirroring current. The output node is coupled to a source of each second transistor and the second current mirror unit, and configured to output a reference voltage. Size of the flipped-gate transistor is less than that of the first transistor.

Abstract: Devices and methods are described herein for a pulse amplitude modulation (PAM) driver. In one embodiment, the PAM driver includes a first high-speed buffer configured to output a first voltage, a second high-speed buffer configured to output a second voltage, and a plurality of transistors coupled to the first high-speed buffer and the second high-speed buffer. At least one of the first voltage or the second voltage facilitates selective operation of a transistor of the plurality of transistors to output a third voltage.

Abstract: A semiconductor structure includes a first substrate. A first die and a second die are disposed over the first substrate and are adjacent to one another. A plurality of first conductive bumps are disposed between the first substrate and the first die and between the first substrate and the second die. A second substrate is disposed below the first substrate. A plurality of second conductive bumps is disposed between the first substrate and the second substrate. An in-package voltage regulator (PVR) chip is disposed over the second substrate. A molding material is disposed over the first substrate and surrounds the first die, the second die, the plurality of first conductive bumps, the plurality of second conductive bumps, and the PVR chip.

Abstract: A charge pump circuit includes an output stage coupled to an output, a pumping stage between an input and the output stage, and a control circuit that outputs control signals. A pumping stage transistor includes S/D terminals coupled to input/output terminals, capacitive devices between signal terminals and either a transistor gate or a S/D terminal, and diode devices including either the anode/cathode or cathode/anode coupled to the respective gate and S/D terminal. An output stage transistor includes S/D terminals coupled to an input terminal and the output. One control signal includes a transition from first to second logic levels at a first time and another control signal includes a transition from the first to second logic levels at a second time, and a period between the transitions is sufficiently small to cause a change in a voltage at the pumping stage S/D terminal to be less than 100 millivolts.

Abstract: Voltage reference circuits are provided. A voltage reference circuit includes a transistor, a flipped-gate transistor, a first current mirror unit, a second current mirror unit and an output node. The gate and the drain of the flipped-gate transistor are coupled to the gate and the drain of the transistor. The first current mirror unit is configured to provide a first current to the flipped-gate transistor and the mirroring current in response to a bias current. The second current mirror unit is configured to drain a second current from the transistor in response to the mirroring current. The output node is coupled to the source of the transistor and the second current mirror unit, and is configured to output a reference voltage.

Abstract: A semiconductor structure includes a first substrate. A first die and a second die are disposed over the first substrate and are adjacent to one another. A plurality of first conductive bumps are disposed between the first substrate and the first die and between the first substrate and the second die. A second substrate is disposed below the first substrate. A plurality of second conductive bumps is disposed between the first substrate and the second substrate. An in-package voltage regulator (PVR) chip is disposed over the second substrate. A molding material is disposed over the first substrate and surrounds the first die, the second die, the plurality of first conductive bumps, the plurality of second conductive bumps, and the PVR chip.

Abstract: An integrated circuit includes a first conductive path over a substrate, a coil structure over the substrate, and a ferromagnetic structure. The first conductive path is configured to carry a first time-varying current and to generate a first time-varying magnetic field based on the first time-varying current. The coil structure is magnetically coupled with the first conductive path, and is configured to generate an induced electrical potential responsive to the first time-varying magnetic field. The ferromagnetic structure includes an open portion. The first conductive path extends through the open portion of the ferromagnetic structure. The first conductive path includes a first conductive line below the ferromagnetic structure, a second conductive line above the ferromagnetic structure, and a first via plug coplanar with the ferromagnetic structure. The first via plug electrically coupling the first conductive line and the second conductive line.

Abstract: A charge pump circuit includes a sub-circuit, which is a pumping stage circuit or an output stage circuit. The sub-circuit includes an input terminal, an output terminal, a transistor, a first capacitive device, a first diode device, and a second diode device. The transistor has a first source/drain (S/D) terminal coupled with the input terminal, a second S/D terminal coupled with the output terminal, and a gate terminal. The first capacitive device has a first end coupled with the gate terminal of the transistor and a second end configured to receive a first driving signal. The first diode device has a cathode coupled with the second S/D terminal of the transistor and an anode coupled with the gate terminal of the transistor. The second diode device has a cathode coupled with the gate terminal of the transistor and an anode coupled with the second S/D terminal of the transistor.

Abstract: An integrated circuit includes a first and a second conductive path over a substrate, a coil structure over the substrate, a voltage sensing circuit electrically coupled with the coil structure, and a ferromagnetic structure including an open portion. The first conductive path is configured to carry a first time-varying current and to generate a first time-varying magnetic field. The second conductive path is configured to carry a second time-varying current and to generate a second time-varying magnetic field. The first conductive path and the second conductive path extend through the open portion of the ferromagnetic structure. The first conductive path includes a first conductive line below the ferromagnetic structure, a second conductive line above the ferromagnetic structure, and a first via plug coplanar with the ferromagnetic structure, the first via plug electrically coupling the first conductive line and the second conductive line.

Abstract: Various magnetic thin film inductor structures are disclosed that include one or more magnetic thin film (MTF) materials. During operation, an electric field passes through one or more conductive windings which, in turn, generates a magnetic field for storing energy within these magnetic thin film inductor structures. The magnetic thin film (MTF) materials within these magnetic thin film inductor structures effectively attract magnetic flux lines of this magnetic field. As a result, any magnetic leakage resulting from the magnetic field generated by these magnetic thin film inductor structures onto nearby electrical, mechanical, and/or electro-mechanical devices is lessened when compared to magnetic leakage resulting from the magnetic field generated by other inductor structures not having the one or more MTF materials.

Abstract: A power converter module includes a ground terminal, an input voltage terminal configured to receive a raw input voltage, and an interconnection terminal configured to provide a regulated output voltage to a load such as a SOC or SIP system to be powered. A voltage regulator is connected to the ground terminal and the input voltage terminal. An inductor has an inductor output connected to the interconnection terminal.

Abstract: An integrated transformer is disclosed. The integrated transformer includes a magnetic core situated in a first layer from among multiple layers of a semiconductor layer stack, a first conductor and a second conductor from among multiple conductors, and a via. The first conductor is situated within a second layer, above the first layer, from among the multiple layers of the semiconductor layer stack. The second conductor is situated within a third layer, below the first layer, from among the multiple layers of the semiconductor layer stack. The via physically and electrically connects the first conductor and the second conductor. The via, the first conductor, and the second conductor form a primary winding of the integrated transformer. The integrated transformer additionally includes a secondary winding, wrapped around the magnetic core, situated in the first layer, the second layer, and the third layer.

Abstract: Various magnetic thin film inductor structures are disclosed that include one or more magnetic thin film (MTF) materials. During operation, an electric field passes through one or mare conductive windings which, in turn, generates a magnetic field for storing energy within these magnetic thin film inductor structures. The magnetic thin film (MTF) materials within these magnetic thin film inductor structures effectively attract magnetic flux lines of this magnetic field. As a result, any magnetic leakage resulting from the magnetic field generated by these magnetic thin film inductor structures onto nearby electrical, mechanical, and/or electro-mechanical devices is lessened when compared to magnetic leakage resulting from the magnetic field generated by other inductor structures not having the one or more MTF materials.

Abstract: A DC-DC converter and a DC-DC converter operation method are provided. The DC-DC converter includes a power stage, an error amplifier, a pulse width modulation (PWM) generator, and a gate controller. The power stage includes a first transistor and a second transistor. The voltage dividers are configured to perform a voltage division on a first node of the power stage and a second node to generate a first voltage and a second voltage. The first node is an output node of the DC-DC converter and the second node is a node between the first transistor and the second transistor of the DC-DC converter. The comparator is configured to compare the first voltage and the second voltage to generate a turn-on time signal of the first transistor according to a comparison result.